pte.h revision 1.1
1 /* $NetBSD: pte.h,v 1.1 2000/01/05 08:48:59 nisimura Exp $ */ 2 3 /* 4 * Copyright (c) 1988 University of Utah. 5 * Copyright (c) 1982, 1986, 1990, 1993 6 * The Regents of the University of California. All rights reserved. 7 * 8 * This code is derived from software contributed to Berkeley by 9 * the Systems Programming Group of the University of Utah Computer 10 * Science Department. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. All advertising materials mentioning features or use of this software 21 * must display the following acknowledgement: 22 * This product includes software developed by the University of 23 * California, Berkeley and its contributors. 24 * 4. Neither the name of the University nor the names of its contributors 25 * may be used to endorse or promote products derived from this software 26 * without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 38 * SUCH DAMAGE. 39 * 40 * from: Utah $Hdr: pte.h 1.13 92/01/20$ 41 * 42 * @(#)pte.h 8.1 (Berkeley) 6/10/93 43 */ 44 45 #ifndef _MACHINE_PTE_H_ 46 #define _MACHINE_PTE_H_ 47 48 /* 49 * m68k hardware segment/page table entries 50 */ 51 52 #if 0 53 struct ste { 54 unsigned int sg_pfnum:20; /* page table frame number */ 55 unsigned int :8; /* reserved at 0 */ 56 unsigned int :1; /* reserved at 1 */ 57 unsigned int sg_prot:1; /* write protect bit */ 58 unsigned int sg_v:2; /* valid bits */ 59 }; 60 61 struct ste40 { 62 unsigned int sg_ptaddr:24; /* page table page addr */ 63 unsigned int :4; /* reserved at 0 */ 64 unsigned int sg_u; /* hardware modified (dirty) bit */ 65 unsigned int sg_prot:1; /* write protect bit */ 66 unsigned int sg_v:2; /* valid bits */ 67 }; 68 69 struct pte { 70 unsigned int pg_pfnum:20; /* page frame number or 0 */ 71 unsigned int :3; 72 unsigned int pg_w:1; /* is wired */ 73 unsigned int :1; /* reserved at zero */ 74 unsigned int pg_ci:1; /* cache inhibit bit */ 75 unsigned int :1; /* reserved at zero */ 76 unsigned int pg_m:1; /* hardware modified (dirty) bit */ 77 unsigned int pg_u:1; /* hardware used (reference) bit */ 78 unsigned int pg_prot:1; /* write protect bit */ 79 unsigned int pg_v:2; /* valid bit */ 80 }; 81 #endif 82 83 typedef int st_entry_t; /* segment table entry */ 84 typedef int pt_entry_t; /* Mach page table entry */ 85 86 #define PT_ENTRY_NULL ((pt_entry_t *) 0) 87 #define ST_ENTRY_NULL ((st_entry_t *) 0) 88 89 #define SG_V 0x00000002 /* segment is valid */ 90 #define SG_NV 0x00000000 91 #define SG_PROT 0x00000004 /* access protection mask */ 92 #define SG_RO 0x00000004 93 #define SG_RW 0x00000000 94 #define SG_U 0x00000008 /* modified bit (68040) */ 95 #define SG_FRAME 0xfffff000 96 #define SG_IMASK 0xffc00000 97 #define SG_ISHIFT 22 98 #define SG_PMASK 0x003ff000 99 #define SG_PSHIFT 12 100 101 /* 68040 additions */ 102 #define SG4_MASK1 0xfe000000 103 #define SG4_SHIFT1 25 104 #define SG4_MASK2 0x01fc0000 105 #define SG4_SHIFT2 18 106 #define SG4_MASK3 0x0003f000 107 #define SG4_SHIFT3 12 108 #define SG4_ADDR1 0xfffffe00 109 #define SG4_ADDR2 0xffffff00 110 #define SG4_LEV1SIZE 128 111 #define SG4_LEV2SIZE 128 112 #define SG4_LEV3SIZE 64 113 114 #define PG_V 0x00000001 115 #define PG_NV 0x00000000 116 #define PG_PROT 0x00000004 117 #define PG_U 0x00000008 118 #define PG_M 0x00000010 119 #define PG_W 0x00000100 120 #define PG_RO 0x00000004 121 #define PG_RW 0x00000000 122 #define PG_FRAME 0xfffff000 123 #define PG_CI 0x00000040 124 #define PG_SHIFT 12 125 #define PG_PFNUM(x) (((x) & PG_FRAME) >> PG_SHIFT) 126 127 /* 68040 additions */ 128 #define PG_CMASK 0x00000060 /* cache mode mask */ 129 #define PG_CWT 0x00000000 /* writethrough caching */ 130 #define PG_CCB 0x00000020 /* copyback caching */ 131 #define PG_CIS 0x00000040 /* cache inhibited serialized */ 132 #define PG_CIN 0x00000060 /* cache inhibited nonserialized */ 133 #define PG_SO 0x00000080 /* supervisor only */ 134 135 #define STSIZE (MAXUL2SIZE*SG4_LEV2SIZE*sizeof(st_entry_t)) 136 /* user process segment table size */ 137 #define MAX_PTSIZE 0x400000 /* max size of UPT */ 138 #define MAX_KPTSIZE 0x100000 /* max memory to allocate to KPT */ 139 #define PTBASE 0x10000000 /* UPT map base address */ 140 #define PTMAXSIZE 0x70000000 /* UPT map maximum size */ 141 142 /* 143 * Kernel virtual address to page table entry and to physical address. 144 */ 145 #define kvtopte(va) \ 146 (&Sysmap[((unsigned)(va) - VM_MIN_KERNEL_ADDRESS) >> PGSHIFT]) 147 #define ptetokv(pt) \ 148 ((((pt_entry_t *)(pt) - Sysmap) << PGSHIFT) + VM_MIN_KERNEL_ADDRESS) 149 #define kvtophys(va) \ 150 ((kvtopte(va)->pg_pfnum << PGSHIFT) | ((int)(va) & PGOFSET)) 151 152 #endif /* !_MACHINE_PTE_H_ */ 153
Indexes created Tue Sep 30 06:09:59 GMT 2025