locore.S revision 1.1
1 /* 2 * Copyright (c) 1992 OMRON Corporation. 3 * 4 * This code is derived from software contributed to Berkeley by 5 * OMRON Corporation. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the University of 18 * California, Berkeley and its contributors. 19 * 4. Neither the name of the University nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * @(#)locore.s 8.1 (Berkeley) 6/10/93 36 */ 37 /* 38 * Copyright (c) 1990, 1993 39 * The Regents of the University of California. All rights reserved. 40 * 41 * This code is derived from software contributed to Berkeley by 42 * OMRON Corporation. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 3. Neither the name of the University nor the names of its contributors 53 * may be used to endorse or promote products derived from this software 54 * without specific prior written permission. 55 * 56 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 57 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 58 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 59 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 60 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 61 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 62 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 63 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 64 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 65 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 66 * SUCH DAMAGE. 67 * 68 * @(#)locore.s 8.1 (Berkeley) 6/10/93 69 */ 70 71 /* For _C_LABEL() and friends. */ 72 #include <m68k/asm.h> 73 74 #define T_BUSERR 0 75 #define T_ADDRERR 1 76 #define T_ILLINST 2 77 #define T_ZERODIV 3 78 #define T_CHKINST 4 79 #define T_TRAPVINST 5 80 #define T_PRIVINST 6 81 #define T_MMUFLT 8 82 #define T_FMTERR 10 83 #define T_FPERR 11 84 #define T_COPERR 12 85 86 #define PSL_LOWIPL 8192 87 #define PSL_HIGHIPL 9984 88 89 #define SPL1 8448 90 #define SPL2 8704 91 #define SPL3 8960 92 #define SPL4 9216 93 #define SPL5 9472 94 #define SPL6 9728 95 96 #define CLOCK_REG 1660944384 97 #define CLK_CLR 1 98 99 #define ILLGINST 16 100 #define NMIVEC 124 101 #define EVTRAPF 188 102 103 .text 104 105 .globl Reset 106 .globl _buserr,_addrerr 107 .globl _illinst,_zerodiv,_chkinst,_trapvinst,_privinst 108 .globl _lev6intr,_lev5intr,_lev3intr,_lev2intr,_badtrap 109 110 ASENTRY_NOPROFILE(start) 111 Reset: 112 jmp _C_LABEL(start1) /* 0: NOT USED (reset PC) */ 113 .word 0 /* 1: NOT USED (reset PC) */ 114 .long _buserr /* 2: bus error */ 115 .long _addrerr /* 3: address error */ 116 .long _illinst /* 4: illegal instruction */ 117 .long _zerodiv /* 5: zero divide */ 118 .long _chkinst /* 6: CHK instruction */ 119 .long _trapvinst /* 7: TRAPV instruction */ 120 .long _privinst /* 8: privilege violation */ 121 .long _badtrap /* 9: trace */ 122 .long _illinst /* 10: line 1010 emulator */ 123 .long _illinst /* 11: line 1111 emulator */ 124 .long _badtrap /* 12: unassigned, reserved */ 125 .long _coperr /* 13: coprocessor protocol violation */ 126 .long _fmterr /* 14: format error */ 127 .long _badtrap /* 15: uninitialized interrupt vector */ 128 .long _badtrap /* 16: unassigned, reserved */ 129 .long _badtrap /* 17: unassigned, reserved */ 130 .long _badtrap /* 18: unassigned, reserved */ 131 .long _badtrap /* 19: unassigned, reserved */ 132 .long _badtrap /* 20: unassigned, reserved */ 133 .long _badtrap /* 21: unassigned, reserved */ 134 .long _badtrap /* 22: unassigned, reserved */ 135 .long _badtrap /* 23: unassigned, reserved */ 136 .long _badtrap /* 24: spurious interrupt */ 137 .long _badtrap /* 25: level 1 interrupt autovector */ 138 .long _lev2intr /* 26: level 2 interrupt autovector */ 139 .long _lev3intr /* 27: level 3 interrupt autovector */ 140 .long _badtrap /* 28: level 4 interrupt autovector */ 141 .long _lev5intr /* 29: level 5 interrupt autovector */ 142 .long _lev6intr /* 30: level 6 interrupt autovector */ 143 .long _badtrap /* 31: level 7 interrupt autovector */ 144 .long _illinst /* 32: syscalls */ 145 .long _illinst /* 33: sigreturn syscall or breakpoint */ 146 .long _illinst /* 34: breakpoint or sigreturn syscall */ 147 .long _illinst /* 35: TRAP instruction vector */ 148 .long _illinst /* 36: TRAP instruction vector */ 149 .long _illinst /* 37: TRAP instruction vector */ 150 .long _illinst /* 38: TRAP instruction vector */ 151 .long _illinst /* 39: TRAP instruction vector */ 152 .long _illinst /* 40: TRAP instruction vector */ 153 .long _illinst /* 41: TRAP instruction vector */ 154 .long _illinst /* 42: TRAP instruction vector */ 155 .long _illinst /* 43: TRAP instruction vector */ 156 .long _illinst /* 44: TRAP instruction vector */ 157 .long _illinst /* 45: TRAP instruction vector */ 158 .long _illinst /* 46: TRAP instruction vector */ 159 .long _illinst /* 47: TRAP instruction vector */ 160 .long _fptrap /* 48: FPCP branch/set on unordered cond */ 161 .long _fptrap /* 49: FPCP inexact result */ 162 .long _fptrap /* 50: FPCP divide by zero */ 163 .long _fptrap /* 51: FPCP underflow */ 164 .long _fptrap /* 52: FPCP operand error */ 165 .long _fptrap /* 53: FPCP overflow */ 166 .long _fptrap /* 54: FPCP signalling NAN */ 167 168 .long _badtrap /* 55: unassigned, reserved */ 169 .long _badtrap /* 56: unassigned, reserved */ 170 .long _badtrap /* 57: unassigned, reserved */ 171 .long _badtrap /* 58: unassigned, reserved */ 172 .long _badtrap /* 59: unassigned, reserved */ 173 .long _badtrap /* 60: unassigned, reserved */ 174 .long _badtrap /* 61: unassigned, reserved */ 175 .long _badtrap /* 62: unassigned, reserved */ 176 .long _badtrap /* 63: unassigned, reserved */ 177 #define BADTRAP16 .long _badtrap,_badtrap,_badtrap,_badtrap,\ 178 _badtrap,_badtrap,_badtrap,_badtrap,\ 179 _badtrap,_badtrap,_badtrap,_badtrap,\ 180 _badtrap,_badtrap,_badtrap,_badtrap 181 BADTRAP16 /* 64-255: user interrupt vectors */ 182 BADTRAP16 /* 64-255: user interrupt vectors */ 183 BADTRAP16 /* 64-255: user interrupt vectors */ 184 BADTRAP16 /* 64-255: user interrupt vectors */ 185 BADTRAP16 /* 64-255: user interrupt vectors */ 186 BADTRAP16 /* 64-255: user interrupt vectors */ 187 BADTRAP16 /* 64-255: user interrupt vectors */ 188 BADTRAP16 /* 64-255: user interrupt vectors */ 189 BADTRAP16 /* 64-255: user interrupt vectors */ 190 BADTRAP16 /* 64-255: user interrupt vectors */ 191 BADTRAP16 /* 64-255: user interrupt vectors */ 192 BADTRAP16 /* 64-255: user interrupt vectors */ 193 194 195 .globl _etext,_edata,_end 196 197 START = 0x700000 198 STACK = 0x800000 199 DIPSW = 0x49000000 200 201 ASENTRY_NOPROFILE(start1) 202 movw #PSL_HIGHIPL,%sr | no interrupts 203 movl #STACK,%sp | set SP 204 205 movl #_C_LABEL(prgcore), %a2 | save program address 206 movl #Reset, %a2@+ | save start of core 207 movl #_C_LABEL(end), %a2@+ | save end of core 208 movl #STACK, %a2@ | save initial stack addr 209 210 /* clear BSS area */ 211 movl #_C_LABEL(edata),%a2 | start of BSS 212 movl #_C_LABEL(end),%a3 | end 213 Lbssclr: 214 clrb %a2@+ | clear BSS 215 cmpl %a2,%a3 | done? 216 bne Lbssclr | no, keep going 217 218 /* save address to goto ROM monitor */ 219 movec %vbr,%a0 | ROM vbr to %a0 220 movl %a0@(NMIVEC),%d0 | restore NMIVEC 221 movl #_ASM_LABEL(gotoROM),%a0 | save to _gotoROM 222 movl %d0,%a0@ | 223 movl #Reset,%a0 | BP vbr to %a0 224 movl #_C_LABEL(exit),%a0@(NMIVEC) | save address 225 226 227 /* switch vector tabel */ 228 movec %vbr,%a0 229 movl %a0@(ILLGINST),%sp@- | save ILLINST vector for BrkPtr 230 movl %a0@(EVTRAPF),%sp@- 231 232 movl #Reset,%a0 233 movl %sp@+,%a0@(EVTRAPF) 234 movl %sp@+,%a0@(ILLGINST) | restore ILLINST vector 235 movec %a0,%vbr 236 237 movl #DIPSW,%a0 238 movw %a0@,%d0 239 lsrl #8,%d0 240 andl #0xFF,%d0 241 movl %d0,_C_LABEL(dipsw1) 242 movw %a0@,%d0 243 andl #0xFF,%d0 244 movl %d0,_C_LABEL(dipsw2) 245 246 /* final setup for C code */ 247 movw #PSL_LOWIPL,%sr | no interrupts 248 jsr _C_LABEL(main) | lets go 249 jsr start 250 251 /* 252 * exit to ROM monitor 253 */ 254 255 ROM_VBR = 0 256 257 ENTRY_NOPROFILE(exit) 258 GLOBAL(_rtt) 259 movw #PSL_HIGHIPL,%sr | no interrupts 260 movl #ROM_VBR,%a0 261 movec %a0,%vbr 262 movl #_ASM_LABEL(gotoROM),%a0 263 movl %a0@,%a1 264 jmp %a1@ 265 266 /* 267 * Trap/interrupt vector routines 268 */ 269 270 _buserr: 271 tstl _C_LABEL(nofault) | device probe? 272 jeq _addrerr | no, handle as usual 273 movl _C_LABEL(nofault),%sp@- | yes, 274 jbsr _C_LABEL(longjmp) | longjmp(nofault) 275 _addrerr: 276 clrw %sp@- | pad SR to longword 277 moveml #0xFFFF,%sp@- | save user registers 278 movl %usp,%a0 | save the user SP 279 movl %a0,%sp@(60) | in the savearea 280 lea %sp@(64),%a1 | grab base of HW berr frame 281 movw %a1@(12),%d0 | grab SSW for fault processing 282 btst #12,%d0 | RB set? 283 jeq LbeX0 | no, test RC 284 bset #14,%d0 | yes, must set FB 285 movw %d0,%a1@(12) | for hardware too 286 LbeX0: 287 btst #13,%d0 | RC set? 288 jeq LbeX1 | no, skip 289 bset #15,%d0 | yes, must set FC 290 movw %d0,%a1@(12) | for hardware too 291 LbeX1: 292 btst #8,%d0 | data fault? 293 jeq Lbe0 | no, check for hard cases 294 movl %a1@(18),%d1 | fault address is as given in frame 295 jra Lbe10 | thats it 296 Lbe0: 297 btst #4,%a1@(8) | long (type B) stack frame? 298 jne Lbe4 | yes, go handle 299 movl %a1@(4),%d1 | no, can use save PC 300 btst #14,%d0 | FB set? 301 jeq Lbe3 | no, try FC 302 addql #4,%d1 | yes, adjust address 303 jra Lbe10 | done 304 Lbe3: 305 btst #15,%d0 | FC set? 306 jeq Lbe10 | no, done 307 addql #2,%d1 | yes, adjust address 308 jra Lbe10 | done 309 Lbe4: 310 movl %a1@(38),%d1 | long format, use stage B address 311 btst #15,%d0 | FC set? 312 jeq Lbe10 | no, all done 313 subql #2,%d1 | yes, adjust address 314 Lbe10: 315 movl %d1,%sp@- | push fault VA 316 movw %d0,%sp@- | and SSW 317 clrw %sp@- | padded to longword 318 movw %a1@(8),%d0 | get frame format/vector offset 319 andw #0x0FFF,%d0 | clear out frame format 320 cmpw #12,%d0 | address error vector? 321 jeq Lisaerr | yes, go to it 322 #if 0 323 movl %d1,%a0 | fault address 324 .long 0xf0109e11 | ptestr #1,%a0@,#7 325 .long 0xf0176200 | pmove %psr,%sp@ 326 btst #7,%sp@ | bus error bit set? 327 jeq Lismerr | no, must be MMU fault 328 clrw %sp@ | yes, re-clear pad word 329 #endif 330 jra Lisberr | and process as normal bus error 331 Lismerr: 332 movl #T_MMUFLT,%sp@- | show that we are an MMU fault 333 jra Lbexit | and deal with it 334 Lisaerr: 335 movl #T_ADDRERR,%sp@- | mark address error 336 jra Lbexit | and deal with it 337 Lisberr: 338 movl #T_BUSERR,%sp@- | mark bus error 339 Lbexit: 340 jbsr _C_LABEL(trap) | handle the error 341 lea %sp@(12),%sp | pop value args 342 movl %sp@(60),%a0 | restore user SP 343 movl %a0,%usp | from save area 344 moveml %sp@+,#0x7FFF | restore most user regs 345 addql #4,%sp | toss SSP 346 tstw %sp@+ | do we need to clean up stack? 347 jeq rei | no, just continue 348 btst #7,%sp@(6) | type 9/10/11 frame? 349 jeq rei | no, nothing to do 350 btst #5,%sp@(6) | type 9? 351 jne Lbex1 | no, skip 352 movw %sp@,%sp@(12) | yes, push down SR 353 movl %sp@(2),%sp@(14) | and PC 354 clrw %sp@(18) | and mark as type 0 frame 355 lea %sp@(12),%sp | clean the excess 356 jra rei | all done 357 Lbex1: 358 btst #4,%sp@(6) | type 10? 359 jne Lbex2 | no, skip 360 movw %sp@,%sp@(24) | yes, push down SR 361 movl %sp@(2),%sp@(26) | and PC 362 clrw %sp@(30) | and mark as type 0 frame 363 lea %sp@(24),%sp | clean the excess 364 jra rei | all done 365 Lbex2: 366 movw %sp@,%sp@(84) | type 11, push down SR 367 movl %sp@(2),%sp@(86) | and PC 368 clrw %sp@(90) | and mark as type 0 frame 369 lea %sp@(84),%sp | clean the excess 370 jra rei | all done 371 372 _illinst: 373 clrw %sp@- 374 moveml #0xFFFF,%sp@- 375 moveq #T_ILLINST,%d0 376 jra _fault 377 378 _zerodiv: 379 clrw %sp@- 380 moveml #0xFFFF,%sp@- 381 moveq #T_ZERODIV,%d0 382 jra _fault 383 384 _chkinst: 385 clrw %sp@- 386 moveml #0xFFFF,%sp@- 387 moveq #T_CHKINST,%d0 388 jra _fault 389 390 _trapvinst: 391 clrw %sp@- 392 moveml #0xFFFF,%sp@- 393 moveq #T_TRAPVINST,%d0 394 jra _fault 395 396 _privinst: 397 clrw %sp@- 398 moveml #0xFFFF,%sp@- 399 moveq #T_PRIVINST,%d0 400 jra _fault 401 402 _coperr: 403 clrw %sp@- 404 moveml #0xFFFF,%sp@- 405 moveq #T_COPERR,%d0 406 jra _fault 407 408 _fmterr: 409 clrw %sp@- 410 moveml #0xFFFF,%sp@- 411 moveq #T_FMTERR,%d0 412 jra _fault 413 414 _fptrap: 415 #ifdef FPCOPROC 416 clrw %sp@- | pad SR to longword 417 moveml #0xFFFF,%sp@- | save user registers 418 movl %usp,%a0 | and save 419 movl %a0,%sp@(60) | the user stack pointer 420 clrl %sp@- | no VA arg 421 #if 0 422 lea _u+PCB_FPCTX,%a0 | address of FP savearea 423 .word 0xf310 | fsave %a0@ 424 tstb %a0@ | null state frame? 425 jeq Lfptnull | yes, safe 426 clrw %d0 | no, need to tweak BIU 427 movb a0@(1),d0 | get frame size 428 bset #3,%a0@(0,%d0:w) | set exc_pend bit of BIU 429 Lfptnull: 430 .word 0xf227,0xa800 | fmovem %fpsr,%sp@- (code arg) 431 .word 0xf350 | frestore %a0@ 432 #else 433 clrl %sp@- | push dummy FPSR 434 #endif 435 movl #T_FPERR,%sp@- | push type arg 436 jbsr _C_LABEL(trap) | call trap 437 lea %sp@(12),%sp | pop value args 438 movl %sp@(60),%a0 | restore 439 movl %a0,%usp | user SP 440 moveml %sp@+,#0x7FFF | and remaining user registers 441 addql #6,%sp | pop SSP and align word 442 jra rei | all done 443 #else 444 jra _badtrap | treat as an unexpected trap 445 #endif 446 447 .globl _fault 448 _fault: 449 movl %usp,%a0 | get and save 450 movl %a0,%sp@(60) | the user stack pointer 451 clrl %sp@- | no VA arg 452 clrl %sp@- | or code arg 453 movl %d0,%sp@- | push trap type 454 jbsr _C_LABEL(trap) | handle trap 455 lea %sp@(12),%sp | pop value args 456 movl %sp@(60),%a0 | restore 457 movl %a0,%usp | user SP 458 moveml %sp@+,#0x7FFF | restore most user regs 459 addql #6,%sp | pop SP and pad word 460 jra rei | all done 461 462 _badtrap: 463 clrw %sp@- 464 moveml #0xC0C0,%sp@- 465 movw %sp@(24),%sp@- 466 clrw %sp@- 467 jbsr _C_LABEL(straytrap) 468 addql #4,%sp 469 moveml %sp@+,#0x0303 470 addql #2,%sp 471 jra rei 472 473 /* 474 * Interrupt handlers. 475 * All device interrupts are auto-vectored. Most can be configured 476 * to interrupt in the range IPL2 to IPL6. Here are our assignments: 477 * 478 * Level 0: 479 * Level 1: 480 * Level 2: SCSI SPC 481 * Level 3: 482 * Level 4: 483 * Level 5: System Clock 484 * Level 6: Internal SIO used uPD7201A 485 * Level 7: Non-maskable: Abort Key (Dispatched vector to ROM monitor) 486 */ 487 488 _lev2intr: 489 clrw %sp@- 490 moveml #0xC0C0,%sp@- 491 jbsr _C_LABEL(scintr) 492 moveml %sp@+,#0x0303 493 addql #2,%sp 494 jra rei 495 496 _lev3intr: 497 clrw %sp@- 498 moveml #0xC0C0,%sp@- 499 moveml %sp@+,#0x0303 500 addql #2,%sp 501 jra rei 502 503 _lev5intr: 504 clrw %sp@- | push pad word 505 moveml #0xC0C0,%sp@- | save scratch regs 506 movl #CLOCK_REG,%a0 | get clock CR addr 507 movb #CLK_CLR,%a0@ | reset system clock 508 lea %sp@(16),%a1 | get pointer to PS 509 movl %a1@,%sp@- | push padded PS 510 movl %a1@(4),%sp@- | push PC 511 jbsr _C_LABEL(hardclock) | call generic clock int routine 512 addql #8,%sp | pop params 513 moveml %sp@+,#0x0303 | restore scratch regs 514 addql #2,%sp | pop pad word 515 jra rei | all done 516 ENTRY_NOPROFILE(hardclock) 517 rts 518 519 _lev6intr: 520 clrw %sp@- 521 moveml #0xC0C0,%sp@- 522 jbsr _C_LABEL(_siointr) 523 moveml %sp@+,#0x0303 524 addql #2,%sp 525 jra rei 526 527 528 /* 529 * Emulation of VAX REI instruction. 530 * 531 * This code deals with checking for and servicing ASTs 532 * (profiling, scheduling) and software interrupts (network, softclock). 533 * We check for ASTs first, just like the VAX. To avoid excess overhead 534 * the T_ASTFLT handling code will also check for software interrupts so we 535 * do not have to do it here. 536 * 537 * This code is complicated by the fact that sendsig may have been called 538 * necessitating a stack cleanup. A cleanup should only be needed at this 539 * point for coprocessor mid-instruction frames (type 9), but we also test 540 * for bus error frames (type 10 and 11). 541 */ 542 #if 0 543 .comm _ssir,1 544 rei: 545 #ifdef DEBUG 546 tstl _panicstr | have we paniced? 547 jne Ldorte | yes, do not make matters worse 548 #endif 549 btst #PCB_ASTB,_u+PCB_FLAGS+1| AST pending? 550 jeq Lchksir | no, go check for SIR 551 btst #5,%sp@ | yes, are we returning to user mode? 552 jne Lchksir | no, go check for SIR 553 clrw %sp@- | pad SR to longword 554 moveml #0xFFFF,%sp@- | save all registers 555 movl %usp,%a1 | including 556 movl %a1,%sp@(60) | the users SP 557 clrl %sp@- | VA == none 558 clrl %sp@- | code == none 559 movl #T_ASTFLT,%sp@- | type == async system trap 560 jbsr _trap | go handle it 561 lea %sp@(12),%sp | pop value args 562 movl %sp@(60),%a0 | restore 563 movl %a0,%usp | user SP 564 moveml %sp@+,#0x7FFF | and all remaining registers 565 addql #4,%sp | toss SSP 566 tstw %sp@+ | do we need to clean up stack? 567 jeq Ldorte | no, just continue 568 btst #7,%sp@(6) | type 9/10/11 frame? 569 jeq Ldorte | no, nothing to do 570 btst #5,%sp@(6) | type 9? 571 jne Last1 | no, skip 572 movw %sp@,%sp@(12) | yes, push down SR 573 movl %sp@(2),%sp@(14) | and PC 574 clrw %sp@(18) | and mark as type 0 frame 575 lea %sp@(12),%sp | clean the excess 576 jra Ldorte | all done 577 Last1: 578 btst #4,%sp@(6) | type 10? 579 jne Last2 | no, skip 580 movw %sp@,%sp@(24) | yes, push down SR 581 movl %sp@(2),%sp@(26) | and PC 582 clrw %sp@(30) | and mark as type 0 frame 583 lea %sp@(24),%sp | clean the excess 584 jra Ldorte | all done 585 Last2: 586 movw %sp@,%sp@(84) | type 11, push down SR 587 movl %sp@(2),%sp@(86) | and PC 588 clrw %sp@(90) | and mark as type 0 frame 589 lea %sp@(84),%sp | clean the excess 590 jra Ldorte | all done 591 Lchksir: 592 tstb _ssir | SIR pending? 593 jeq Ldorte | no, all done 594 movl %d0,%sp@- | need a scratch register 595 movw %sp@(4),%d0 | get SR 596 andw #PSL_IPL7,%d0 | mask all but IPL 597 jne Lnosir | came from interrupt, no can do 598 movl %sp@+,%d0 | restore scratch register 599 Lgotsir: 600 movw #SPL1,%sr | prevent others from servicing int 601 tstb _ssir | too late? 602 jeq Ldorte | yes, oh well... 603 clrw %sp@- | pad SR to longword 604 moveml #0xFFFF,%sp@- | save all registers 605 movl %usp,%a1 | including 606 movl %a1,%sp@(60) | the users SP 607 clrl %sp@- | VA == none 608 clrl %sp@- | code == none 609 movl #T_SSIR,%sp@- | type == software interrupt 610 jbsr _trap | go handle it 611 lea %sp@(12),%sp | pop value args 612 movl %sp@(60),%a0 | restore 613 movl %a0,%usp | user SP 614 moveml %sp@+,#0x7FFF | and all remaining registers 615 addql #6,%sp | pop SSP and align word 616 rte 617 Lnosir: 618 movl %sp@+,%d0 | restore scratch register 619 Ldorte: 620 #else 621 rei: | dummy Entry of rei 622 #endif 623 rte | real return 624 625 /* 626 * non-local gotos 627 */ 628 ALTENTRY(savectx, _setjmp) 629 ENTRY(setjmp) 630 movl %sp@(4),%a0 | savearea pointer 631 moveml #0xFCFC,%a0@ | save d2-d7/a2-a7 632 movl %sp@,%a0@(48) | and return address 633 moveq #0,%d0 | return 0 634 rts 635 636 ENTRY(qsetjmp) 637 movl %sp@(4),%a0 | savearea pointer 638 lea %a0@(40),%a0 | skip regs we do not save 639 movl %a6,%a0@+ | save FP 640 movl %sp,%a0@+ | save SP 641 movl %sp@,%a0@ | and return address 642 moveq #0,%d0 | return 0 643 rts 644 645 ENTRY(longjmp) 646 movl %sp@(4),%a0 647 moveml %a0@+,#0xFCFC 648 movl %a0@,%sp@ 649 moveq #1,%d0 650 rts 651 652 ENTRY_NOPROFILE(getsfc) 653 movc %sfc,%d0 654 rts 655 ENTRY_NOPROFILE(getdfc) 656 movc %dfc,%d0 657 rts 658 659 /* 660 * Set processor priority level calls. Most could (should) be replaced 661 * by inline asm expansions. However, SPL0 and SPLX require special 662 * handling. If we are returning to the base processor priority (SPL0) 663 * we need to check for our emulated software interrupts. 664 */ 665 666 ENTRY(spl0) 667 moveq #0,%d0 668 movw %sr,%d0 | get old SR for return 669 movw #PSL_LOWIPL,%sr | restore new SR 670 | jra Lsplsir 671 rts 672 673 ENTRY(splx) 674 moveq #0,%d0 675 movw %sr,%d0 | get current SR for return 676 movw %sp@(6),%d1 | get new value 677 movw %d1,%sr | restore new SR 678 | andw #PSL_IPL7,%d1 | mask all but PSL_IPL 679 | jne Lspldone | non-zero, all done 680 |Lsplsir: 681 | tstb _ssir | software interrupt pending? 682 | jeq Lspldone | no, all done 683 | subql #4,%sp | make room for RTE frame 684 | movl %sp@(4),%sp@(2) | position return address 685 | clrw %sp@(6) | set frame type 0 686 | movw #PSL_LOWIPL,%sp@ | and new SR 687 | jra Lgotsir | go handle it 688 |Lspldone: 689 rts 690 691 ENTRY(spl1) 692 moveq #0,%d0 693 movw %sr,%d0 694 movw #SPL1,%sr 695 rts 696 697 ALTENTRY(splscsi, _spl2) 698 ENTRY(spl2) 699 moveq #0,%d0 700 movw %sr,%d0 701 movw #SPL2,%sr 702 rts 703 704 ENTRY(spl3) 705 moveq #0,%d0 706 movw %sr,%d0 707 movw #SPL3,%sr 708 rts 709 710 ENTRY(spl4) 711 moveq #0,%d0 712 movw %sr,%d0 713 movw #SPL4,%sr 714 rts 715 716 ENTRY(spl5) 717 moveq #0,%d0 718 movw %sr,%d0 719 movw #SPL5,%sr 720 rts 721 722 ENTRY(spl6) 723 moveq #0,%d0 724 movw %sr,%d0 725 movw #SPL6,%sr 726 rts 727 728 ALTENTRY(splhigh, _spl7) 729 ENTRY(spl7) 730 moveq #0,%d0 731 movw %sr,%d0 732 movw #PSL_HIGHIPL,%sr 733 rts 734 735 736 .data 737 738 /* 739 * Memory Infomation Field for secondary booter memory allocator 740 */ 741 742 GLOBAL(prgcore) 743 .long 0 744 .long 0 745 .long 0 746 747 gotoROM: 748 .long 0 749 750 GLOBAL(dipsw1) 751 .long 0 752 753 GLOBAL(dipsw2) 754 .long 0 755
Indexes created Sat Oct 25 16:10:12 GMT 2025