locore.S revision 1.5
1 /* 2 * Copyright (c) 1992 OMRON Corporation. 3 * 4 * This code is derived from software contributed to Berkeley by 5 * OMRON Corporation. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the University of 18 * California, Berkeley and its contributors. 19 * 4. Neither the name of the University nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * @(#)locore.s 8.1 (Berkeley) 6/10/93 36 */ 37 /* 38 * Copyright (c) 1990, 1993 39 * The Regents of the University of California. All rights reserved. 40 * 41 * This code is derived from software contributed to Berkeley by 42 * OMRON Corporation. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 3. Neither the name of the University nor the names of its contributors 53 * may be used to endorse or promote products derived from this software 54 * without specific prior written permission. 55 * 56 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 57 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 58 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 59 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 60 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 61 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 62 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 63 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 64 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 65 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 66 * SUCH DAMAGE. 67 * 68 * @(#)locore.s 8.1 (Berkeley) 6/10/93 69 */ 70 71 /* For _C_LABEL() and friends. */ 72 #include <m68k/asm.h> 73 74 #define T_BUSERR 0 75 #define T_ADDRERR 1 76 #define T_ILLINST 2 77 #define T_ZERODIV 3 78 #define T_CHKINST 4 79 #define T_TRAPVINST 5 80 #define T_PRIVINST 6 81 #define T_MMUFLT 8 82 #define T_FMTERR 10 83 #define T_FPERR 11 84 #define T_COPERR 12 85 86 #define PSL_LOWIPL 8192 87 #define PSL_HIGHIPL 9984 88 89 #define SPL1 8448 90 #define SPL2 8704 91 #define SPL3 8960 92 #define SPL4 9216 93 #define SPL5 9472 94 #define SPL6 9728 95 96 #define CLOCK_REG 1660944384 97 #define CLK_CLR 1 98 99 #define ILLGINST 16 100 #define NMIVEC 124 101 #define EVTRAPF 188 102 103 .text 104 105 ASENTRY_NOPROFILE(start) 106 ASGLOBAL(Reset) 107 jmp _C_LABEL(start1) /* 0: NOT USED (reset PC) */ 108 .word 0 /* 1: NOT USED (reset PC) */ 109 VECTOR(buserr) /* 2: bus error */ 110 VECTOR(addrerr) /* 3: address error */ 111 VECTOR(illinst) /* 4: illegal instruction */ 112 VECTOR(zerodiv) /* 5: zero divide */ 113 VECTOR(chkinst) /* 6: CHK instruction */ 114 VECTOR(trapvinst) /* 7: TRAPV instruction */ 115 VECTOR(privinst) /* 8: privilege violation */ 116 VECTOR(badtrap) /* 9: trace */ 117 VECTOR(illinst) /* 10: line 1010 emulator */ 118 VECTOR(illinst) /* 11: line 1111 emulator */ 119 VECTOR(badtrap) /* 12: unassigned, reserved */ 120 VECTOR(coperr) /* 13: coprocessor protocol violation */ 121 VECTOR(fmterr) /* 14: format error */ 122 VECTOR(badtrap) /* 15: uninitialized interrupt vector */ 123 VECTOR(badtrap) /* 16: unassigned, reserved */ 124 VECTOR(badtrap) /* 17: unassigned, reserved */ 125 VECTOR(badtrap) /* 18: unassigned, reserved */ 126 VECTOR(badtrap) /* 19: unassigned, reserved */ 127 VECTOR(badtrap) /* 20: unassigned, reserved */ 128 VECTOR(badtrap) /* 21: unassigned, reserved */ 129 VECTOR(badtrap) /* 22: unassigned, reserved */ 130 VECTOR(badtrap) /* 23: unassigned, reserved */ 131 VECTOR(badtrap) /* 24: unassigned, reserved */ 132 VECTOR(badtrap) /* 25: unassigned, reserved */ 133 VECTOR(lev2intr) /* 26: level 2 interrupt autovector */ 134 VECTOR(lev3intr) /* 27: level 3 interrupt autovector */ 135 VECTOR(badtrap) /* 28: level 4 interrupt autovector */ 136 VECTOR(lev5intr) /* 29: level 5 interrupt autovector */ 137 VECTOR(lev6intr) /* 30: level 6 interrupt autovector */ 138 VECTOR(badtrap) /* 31: level 7 interrupt autovector */ 139 VECTOR(illinst) /* 32: syscalls */ 140 VECTOR(illinst) /* 33: sigreturn syscall or breakpoint */ 141 VECTOR(illinst) /* 34: breakpoint or sigreturn syscall */ 142 VECTOR(illinst) /* 35: TRAP instruction vector */ 143 VECTOR(illinst) /* 36: TRAP instruction vector */ 144 VECTOR(illinst) /* 37: TRAP instruction vector */ 145 VECTOR(illinst) /* 38: TRAP instruction vector */ 146 VECTOR(illinst) /* 39: TRAP instruction vector */ 147 VECTOR(illinst) /* 40: TRAP instruction vector */ 148 VECTOR(illinst) /* 41: TRAP instruction vector */ 149 VECTOR(illinst) /* 42: TRAP instruction vector */ 150 VECTOR(illinst) /* 43: TRAP instruction vector */ 151 VECTOR(illinst) /* 44: TRAP instruction vector */ 152 VECTOR(illinst) /* 45: TRAP instruction vector */ 153 VECTOR(illinst) /* 45: TRAP instruction vector */ 154 VECTOR(illinst) /* 47: TRAP instruction vector */ 155 VECTOR(fptrap) /* 48: FPCP branch/set on unordered cond */ 156 VECTOR(fptrap) /* 49: FPCP inexact result */ 157 VECTOR(fptrap) /* 50: FPCP divide by zero */ 158 VECTOR(fptrap) /* 51: FPCP underflow */ 159 VECTOR(fptrap) /* 52: FPCP operand error */ 160 VECTOR(fptrap) /* 53: FPCP overflow */ 161 VECTOR(fptrap) /* 54: FPCP signalling NAN */ 162 163 VECTOR(badtrap) /* 55: unassigned, reserved */ 164 VECTOR(badtrap) /* 56: unassigned, reserved */ 165 VECTOR(badtrap) /* 57: unassigned, reserved */ 166 VECTOR(badtrap) /* 58: unassigned, reserved */ 167 VECTOR(badtrap) /* 59: unassigned, reserved */ 168 VECTOR(badtrap) /* 60: unassigned, reserved */ 169 VECTOR(badtrap) /* 61: unassigned, reserved */ 170 VECTOR(badtrap) /* 62: unassigned, reserved */ 171 VECTOR(badtrap) /* 63: unassigned, reserved */ 172 #define BADTRAP16 \ 173 VECTOR(badtrap) ; VECTOR(badtrap) ; \ 174 VECTOR(badtrap) ; VECTOR(badtrap) ; \ 175 VECTOR(badtrap) ; VECTOR(badtrap) ; \ 176 VECTOR(badtrap) ; VECTOR(badtrap) ; \ 177 VECTOR(badtrap) ; VECTOR(badtrap) ; \ 178 VECTOR(badtrap) ; VECTOR(badtrap) ; \ 179 VECTOR(badtrap) ; VECTOR(badtrap) ; \ 180 VECTOR(badtrap) ; VECTOR(badtrap) 181 182 BADTRAP16 /* 64-255: user interrupt vectors */ 183 BADTRAP16 /* 64-255: user interrupt vectors */ 184 BADTRAP16 /* 64-255: user interrupt vectors */ 185 BADTRAP16 /* 64-255: user interrupt vectors */ 186 BADTRAP16 /* 64-255: user interrupt vectors */ 187 BADTRAP16 /* 64-255: user interrupt vectors */ 188 BADTRAP16 /* 64-255: user interrupt vectors */ 189 BADTRAP16 /* 64-255: user interrupt vectors */ 190 BADTRAP16 /* 64-255: user interrupt vectors */ 191 BADTRAP16 /* 64-255: user interrupt vectors */ 192 BADTRAP16 /* 64-255: user interrupt vectors */ 193 BADTRAP16 /* 64-255: user interrupt vectors */ 194 195 196 STACK = 0x800000 197 DIPSW = 0x49000000 198 199 ASENTRY_NOPROFILE(start1) 200 movw #PSL_HIGHIPL,%sr | no interrupts 201 movl #STACK,%sp | set SP 202 203 movl #_C_LABEL(prgcore), %a2 | save program address 204 movl #_ASM_LABEL(Reset), %a2@+ | save start of core 205 movl #_C_LABEL(end), %a2@+ | save end of core 206 movl #STACK, %a2@ | save initial stack addr 207 208 /* clear BSS area */ 209 movl #_C_LABEL(edata),%a2 | start of BSS 210 movl #_C_LABEL(end),%a3 | end 211 Lbssclr: 212 clrb %a2@+ | clear BSS 213 cmpl %a2,%a3 | done? 214 bne Lbssclr | no, keep going 215 216 /* save address to goto ROM monitor */ 217 movec %vbr,%a0 | ROM vbr to %a0 218 movl %a0@(NMIVEC),%d0 | restore NMIVEC 219 movl #_ASM_LABEL(gotoROM),%a0 | save to _gotoROM 220 movl %d0,%a0@ | 221 movl #_ASM_LABEL(Reset),%a0 | BP vbr to %a0 222 movl #_C_LABEL(exit),%a0@(NMIVEC) | save address 223 224 225 /* switch vector tabel */ 226 movec %vbr,%a0 227 movl %a0@(ILLGINST),%sp@- | save ILLINST vector for BrkPtr 228 movl %a0@(EVTRAPF),%sp@- 229 230 movl #_ASM_LABEL(Reset),%a0 231 movl %sp@+,%a0@(EVTRAPF) 232 movl %sp@+,%a0@(ILLGINST) | restore ILLINST vector 233 movec %a0,%vbr 234 235 movl #DIPSW,%a0 236 movw %a0@,%d0 237 lsrl #8,%d0 238 andl #0xFF,%d0 239 movl %d0,_C_LABEL(dipsw1) 240 movw %a0@,%d0 241 andl #0xFF,%d0 242 movl %d0,_C_LABEL(dipsw2) 243 244 /* determine our CPU */ 245 246 /* XXX should be generated via assym.h */ 247 CACHE_OFF = 0x0808 248 DC_FREEZE = 0x0200 249 CPU_68030 = 1 250 CPU_68040 = 2 251 252 movl #CACHE_OFF,%d0 253 movc %d0,%cacr | clear and disable on-chip cache(s) 254 movl #DC_FREEZE,%d0 | data freeze bit 255 movc %d0,%cacr | only exists on 68030 256 movc %cacr,%d0 | read it back 257 tstl %d0 | zero? 258 jeq Lnot68030 | yes, we have 68040 259 movl #CPU_68030,%d0 260 jra Lstart0 261 Lnot68030: 262 movl #CPU_68040,%d0 263 Lstart0: 264 movl %d0,_C_LABEL(cputype) 265 266 /* final setup for C code */ 267 movw #PSL_LOWIPL,%sr | no interrupts 268 jsr _C_LABEL(main) | lets go 269 jsr start 270 271 /* 272 * exit to ROM monitor 273 */ 274 275 ROM_VBR = 0 276 277 ENTRY_NOPROFILE(exit) 278 GLOBAL(_rtt) 279 movw #PSL_HIGHIPL,%sr | no interrupts 280 movl #ROM_VBR,%a0 281 movec %a0,%vbr 282 movl #_ASM_LABEL(gotoROM),%a0 283 movl %a0@,%a1 284 jmp %a1@ 285 286 /* 287 * Trap/interrupt vector routines 288 */ 289 290 ENTRY_NOPROFILE(buserr) 291 tstl _C_LABEL(nofault) | device probe? 292 jeq _C_LABEL(addrerr) | no, handle as usual 293 movl _C_LABEL(nofault),%sp@- | yes, 294 jbsr _C_LABEL(longjmp) | longjmp(nofault) 295 ENTRY_NOPROFILE(addrerr) 296 clrw %sp@- | pad SR to longword 297 moveml #0xFFFF,%sp@- | save user registers 298 movl %usp,%a0 | save the user SP 299 movl %a0,%sp@(60) | in the savearea 300 lea %sp@(64),%a1 | grab base of HW berr frame 301 movw %a1@(12),%d0 | grab SSW for fault processing 302 btst #12,%d0 | RB set? 303 jeq LbeX0 | no, test RC 304 bset #14,%d0 | yes, must set FB 305 movw %d0,%a1@(12) | for hardware too 306 LbeX0: 307 btst #13,%d0 | RC set? 308 jeq LbeX1 | no, skip 309 bset #15,%d0 | yes, must set FC 310 movw %d0,%a1@(12) | for hardware too 311 LbeX1: 312 btst #8,%d0 | data fault? 313 jeq Lbe0 | no, check for hard cases 314 movl %a1@(18),%d1 | fault address is as given in frame 315 jra Lbe10 | thats it 316 Lbe0: 317 btst #4,%a1@(8) | long (type B) stack frame? 318 jne Lbe4 | yes, go handle 319 movl %a1@(4),%d1 | no, can use save PC 320 btst #14,%d0 | FB set? 321 jeq Lbe3 | no, try FC 322 addql #4,%d1 | yes, adjust address 323 jra Lbe10 | done 324 Lbe3: 325 btst #15,%d0 | FC set? 326 jeq Lbe10 | no, done 327 addql #2,%d1 | yes, adjust address 328 jra Lbe10 | done 329 Lbe4: 330 movl %a1@(38),%d1 | long format, use stage B address 331 btst #15,%d0 | FC set? 332 jeq Lbe10 | no, all done 333 subql #2,%d1 | yes, adjust address 334 Lbe10: 335 movl %d1,%sp@- | push fault VA 336 movw %d0,%sp@- | and SSW 337 clrw %sp@- | padded to longword 338 movw %a1@(8),%d0 | get frame format/vector offset 339 andw #0x0FFF,%d0 | clear out frame format 340 cmpw #12,%d0 | address error vector? 341 jeq Lisaerr | yes, go to it 342 #if 0 343 movl %d1,%a0 | fault address 344 .long 0xf0109e11 | ptestr #1,%a0@,#7 345 .long 0xf0176200 | pmove %psr,%sp@ 346 btst #7,%sp@ | bus error bit set? 347 jeq Lismerr | no, must be MMU fault 348 clrw %sp@ | yes, re-clear pad word 349 #endif 350 jra Lisberr | and process as normal bus error 351 Lismerr: 352 movl #T_MMUFLT,%sp@- | show that we are an MMU fault 353 jra Lbexit | and deal with it 354 Lisaerr: 355 movl #T_ADDRERR,%sp@- | mark address error 356 jra Lbexit | and deal with it 357 Lisberr: 358 movl #T_BUSERR,%sp@- | mark bus error 359 Lbexit: 360 jbsr _C_LABEL(trap) | handle the error 361 lea %sp@(12),%sp | pop value args 362 movl %sp@(60),%a0 | restore user SP 363 movl %a0,%usp | from save area 364 moveml %sp@+,#0x7FFF | restore most user regs 365 addql #4,%sp | toss SSP 366 tstw %sp@+ | do we need to clean up stack? 367 jeq _ASM_LABEL(rei) | no, just continue 368 btst #7,%sp@(6) | type 9/10/11 frame? 369 jeq _ASM_LABEL(rei) | no, nothing to do 370 btst #5,%sp@(6) | type 9? 371 jne Lbex1 | no, skip 372 movw %sp@,%sp@(12) | yes, push down SR 373 movl %sp@(2),%sp@(14) | and PC 374 clrw %sp@(18) | and mark as type 0 frame 375 lea %sp@(12),%sp | clean the excess 376 jra _ASM_LABEL(rei) | all done 377 Lbex1: 378 btst #4,%sp@(6) | type 10? 379 jne Lbex2 | no, skip 380 movw %sp@,%sp@(24) | yes, push down SR 381 movl %sp@(2),%sp@(26) | and PC 382 clrw %sp@(30) | and mark as type 0 frame 383 lea %sp@(24),%sp | clean the excess 384 jra _ASM_LABEL(rei) | all done 385 Lbex2: 386 movw %sp@,%sp@(84) | type 11, push down SR 387 movl %sp@(2),%sp@(86) | and PC 388 clrw %sp@(90) | and mark as type 0 frame 389 lea %sp@(84),%sp | clean the excess 390 jra _ASM_LABEL(rei) | all done 391 392 ENTRY_NOPROFILE(illinst) 393 clrw %sp@- 394 moveml #0xFFFF,%sp@- 395 moveq #T_ILLINST,%d0 396 jra _C_LABEL(fault) 397 398 ENTRY_NOPROFILE(zerodiv) 399 clrw %sp@- 400 moveml #0xFFFF,%sp@- 401 moveq #T_ZERODIV,%d0 402 jra _C_LABEL(fault) 403 404 ENTRY_NOPROFILE(chkinst) 405 clrw %sp@- 406 moveml #0xFFFF,%sp@- 407 moveq #T_CHKINST,%d0 408 jra _C_LABEL(fault) 409 410 ENTRY_NOPROFILE(trapvinst) 411 clrw %sp@- 412 moveml #0xFFFF,%sp@- 413 moveq #T_TRAPVINST,%d0 414 jra _C_LABEL(fault) 415 416 ENTRY_NOPROFILE(privinst) 417 clrw %sp@- 418 moveml #0xFFFF,%sp@- 419 moveq #T_PRIVINST,%d0 420 jra _C_LABEL(fault) 421 422 ENTRY_NOPROFILE(coperr) 423 clrw %sp@- 424 moveml #0xFFFF,%sp@- 425 moveq #T_COPERR,%d0 426 jra _C_LABEL(fault) 427 428 ENTRY_NOPROFILE(fmterr) 429 clrw %sp@- 430 moveml #0xFFFF,%sp@- 431 moveq #T_FMTERR,%d0 432 jra _C_LABEL(fault) 433 434 ENTRY_NOPROFILE(fptrap) 435 #ifdef FPCOPROC 436 clrw %sp@- | pad SR to longword 437 moveml #0xFFFF,%sp@- | save user registers 438 movl %usp,%a0 | and save 439 movl %a0,%sp@(60) | the user stack pointer 440 clrl %sp@- | no VA arg 441 #if 0 442 lea _u+PCB_FPCTX,%a0 | address of FP savearea 443 .word 0xf310 | fsave %a0@ 444 tstb %a0@ | null state frame? 445 jeq Lfptnull | yes, safe 446 clrw %d0 | no, need to tweak BIU 447 movb a0@(1),d0 | get frame size 448 bset #3,%a0@(0,%d0:w) | set exc_pend bit of BIU 449 Lfptnull: 450 .word 0xf227,0xa800 | fmovem %fpsr,%sp@- (code arg) 451 .word 0xf350 | frestore %a0@ 452 #else 453 clrl %sp@- | push dummy FPSR 454 #endif 455 movl #T_FPERR,%sp@- | push type arg 456 jbsr _C_LABEL(trap) | call trap 457 lea %sp@(12),%sp | pop value args 458 movl %sp@(60),%a0 | restore 459 movl %a0,%usp | user SP 460 moveml %sp@+,#0x7FFF | and remaining user registers 461 addql #6,%sp | pop SSP and align word 462 jra _ASM_LABEL(rei) | all done 463 #else 464 jra _C_LABEL(badtrap) | treat as an unexpected trap 465 #endif 466 467 ENTRY_NOPROFILE(fault) 468 movl %usp,%a0 | get and save 469 movl %a0,%sp@(60) | the user stack pointer 470 clrl %sp@- | no VA arg 471 clrl %sp@- | or code arg 472 movl %d0,%sp@- | push trap type 473 jbsr _C_LABEL(trap) | handle trap 474 lea %sp@(12),%sp | pop value args 475 movl %sp@(60),%a0 | restore 476 movl %a0,%usp | user SP 477 moveml %sp@+,#0x7FFF | restore most user regs 478 addql #6,%sp | pop SP and pad word 479 jra _ASM_LABEL(rei) | all done 480 481 ENTRY_NOPROFILE(badtrap) 482 clrw %sp@- 483 moveml #0xC0C0,%sp@- 484 movw %sp@(24),%sp@- 485 clrw %sp@- 486 jbsr _C_LABEL(straytrap) 487 addql #4,%sp 488 moveml %sp@+,#0x0303 489 addql #2,%sp 490 jra _ASM_LABEL(rei) 491 492 /* 493 * Interrupt handlers. 494 * All device interrupts are auto-vectored. Most can be configured 495 * to interrupt in the range IPL2 to IPL6. Here are our assignments: 496 * 497 * Level 0: 498 * Level 1: 499 * Level 2: SCSI SPC 500 * Level 3: 501 * Level 4: 502 * Level 5: System Clock 503 * Level 6: Internal SIO used uPD7201A 504 * Level 7: Non-maskable: Abort Key (Dispatched vector to ROM monitor) 505 */ 506 507 ENTRY_NOPROFILE(lev2intr) 508 clrw %sp@- 509 moveml #0xC0C0,%sp@- 510 jbsr _C_LABEL(scintr) 511 moveml %sp@+,#0x0303 512 addql #2,%sp 513 jra _ASM_LABEL(rei) 514 515 ENTRY_NOPROFILE(lev3intr) 516 clrw %sp@- 517 moveml #0xC0C0,%sp@- 518 jbsr _C_LABEL(lance_intr) 519 moveml %sp@+,#0x0303 520 addql #2,%sp 521 jra _ASM_LABEL(rei) 522 523 ENTRY_NOPROFILE(lev5intr) 524 clrw %sp@- | push pad word 525 moveml #0xC0C0,%sp@- | save scratch regs 526 movl #CLOCK_REG,%a0 | get clock CR addr 527 movb #CLK_CLR,%a0@ | reset system clock 528 lea %sp@(16),%a1 | get pointer to PS 529 movl %a1@,%sp@- | push padded PS 530 movl %a1@(4),%sp@- | push PC 531 jbsr _C_LABEL(hardclock) | call generic clock int routine 532 addql #8,%sp | pop params 533 moveml %sp@+,#0x0303 | restore scratch regs 534 addql #2,%sp | pop pad word 535 jra _ASM_LABEL(rei) | all done 536 ENTRY_NOPROFILE(hardclock) 537 rts 538 539 ENTRY_NOPROFILE(lev6intr) 540 clrw %sp@- 541 moveml #0xC0C0,%sp@- 542 jbsr _C_LABEL(_siointr) 543 moveml %sp@+,#0x0303 544 addql #2,%sp 545 jra _ASM_LABEL(rei) 546 547 548 /* 549 * Emulation of VAX REI instruction. 550 * 551 * This code deals with checking for and servicing ASTs 552 * (profiling, scheduling) and software interrupts (network, softclock). 553 * We check for ASTs first, just like the VAX. To avoid excess overhead 554 * the T_ASTFLT handling code will also check for software interrupts so we 555 * do not have to do it here. 556 * 557 * This code is complicated by the fact that sendsig may have been called 558 * necessitating a stack cleanup. A cleanup should only be needed at this 559 * point for coprocessor mid-instruction frames (type 9), but we also test 560 * for bus error frames (type 10 and 11). 561 */ 562 #if 0 563 .comm _ssir,1 564 ASENTRY_NOPROFILE(rei) 565 #ifdef DEBUG 566 tstl _C_LABEL(panicstr) | have we paniced? 567 jne Ldorte | yes, do not make matters worse 568 #endif 569 btst #PCB_ASTB,_u+PCB_FLAGS+1| AST pending? 570 jeq Lchksir | no, go check for SIR 571 btst #5,%sp@ | yes, are we returning to user mode? 572 jne Lchksir | no, go check for SIR 573 clrw %sp@- | pad SR to longword 574 moveml #0xFFFF,%sp@- | save all registers 575 movl %usp,%a1 | including 576 movl %a1,%sp@(60) | the users SP 577 clrl %sp@- | VA == none 578 clrl %sp@- | code == none 579 movl #T_ASTFLT,%sp@- | type == async system trap 580 jbsr _C_LABEL(trap) | go handle it 581 lea %sp@(12),%sp | pop value args 582 movl %sp@(60),%a0 | restore 583 movl %a0,%usp | user SP 584 moveml %sp@+,#0x7FFF | and all remaining registers 585 addql #4,%sp | toss SSP 586 tstw %sp@+ | do we need to clean up stack? 587 jeq Ldorte | no, just continue 588 btst #7,%sp@(6) | type 9/10/11 frame? 589 jeq Ldorte | no, nothing to do 590 btst #5,%sp@(6) | type 9? 591 jne Last1 | no, skip 592 movw %sp@,%sp@(12) | yes, push down SR 593 movl %sp@(2),%sp@(14) | and PC 594 clrw %sp@(18) | and mark as type 0 frame 595 lea %sp@(12),%sp | clean the excess 596 jra Ldorte | all done 597 Last1: 598 btst #4,%sp@(6) | type 10? 599 jne Last2 | no, skip 600 movw %sp@,%sp@(24) | yes, push down SR 601 movl %sp@(2),%sp@(26) | and PC 602 clrw %sp@(30) | and mark as type 0 frame 603 lea %sp@(24),%sp | clean the excess 604 jra Ldorte | all done 605 Last2: 606 movw %sp@,%sp@(84) | type 11, push down SR 607 movl %sp@(2),%sp@(86) | and PC 608 clrw %sp@(90) | and mark as type 0 frame 609 lea %sp@(84),%sp | clean the excess 610 jra Ldorte | all done 611 Lchksir: 612 tstb _ssir | SIR pending? 613 jeq Ldorte | no, all done 614 movl %d0,%sp@- | need a scratch register 615 movw %sp@(4),%d0 | get SR 616 andw #PSL_IPL7,%d0 | mask all but IPL 617 jne Lnosir | came from interrupt, no can do 618 movl %sp@+,%d0 | restore scratch register 619 Lgotsir: 620 movw #SPL1,%sr | prevent others from servicing int 621 tstb _ssir | too late? 622 jeq Ldorte | yes, oh well... 623 clrw %sp@- | pad SR to longword 624 moveml #0xFFFF,%sp@- | save all registers 625 movl %usp,%a1 | including 626 movl %a1,%sp@(60) | the users SP 627 clrl %sp@- | VA == none 628 clrl %sp@- | code == none 629 movl #T_SSIR,%sp@- | type == software interrupt 630 jbsr _trap | go handle it 631 lea %sp@(12),%sp | pop value args 632 movl %sp@(60),%a0 | restore 633 movl %a0,%usp | user SP 634 moveml %sp@+,#0x7FFF | and all remaining registers 635 addql #6,%sp | pop SSP and align word 636 rte 637 Lnosir: 638 movl %sp@+,%d0 | restore scratch register 639 Ldorte: 640 #else 641 ASENTRY_NOPROFILE(rei) | dummy Entry of rei 642 #endif 643 rte | real return 644 645 /* 646 * non-local gotos 647 */ 648 ALTENTRY(savectx, _setjmp) 649 ENTRY(setjmp) 650 movl %sp@(4),%a0 | savearea pointer 651 moveml #0xFCFC,%a0@ | save d2-d7/a2-a7 652 movl %sp@,%a0@(48) | and return address 653 moveq #0,%d0 | return 0 654 rts 655 656 ENTRY(qsetjmp) 657 movl %sp@(4),%a0 | savearea pointer 658 lea %a0@(40),%a0 | skip regs we do not save 659 movl %a6,%a0@+ | save FP 660 movl %sp,%a0@+ | save SP 661 movl %sp@,%a0@ | and return address 662 moveq #0,%d0 | return 0 663 rts 664 665 ENTRY(longjmp) 666 movl %sp@(4),%a0 667 moveml %a0@+,#0xFCFC 668 movl %a0@,%sp@ 669 moveq #1,%d0 670 rts 671 672 ENTRY_NOPROFILE(getsfc) 673 movc %sfc,%d0 674 rts 675 ENTRY_NOPROFILE(getdfc) 676 movc %dfc,%d0 677 rts 678 679 /* 680 * Set processor priority level calls. Most could (should) be replaced 681 * by inline asm expansions. However, SPL0 and SPLX require special 682 * handling. If we are returning to the base processor priority (SPL0) 683 * we need to check for our emulated software interrupts. 684 */ 685 686 ENTRY(spl0) 687 moveq #0,%d0 688 movw %sr,%d0 | get old SR for return 689 movw #PSL_LOWIPL,%sr | restore new SR 690 | jra Lsplsir 691 rts 692 693 ENTRY(splx) 694 moveq #0,%d0 695 movw %sr,%d0 | get current SR for return 696 movw %sp@(6),%d1 | get new value 697 movw %d1,%sr | restore new SR 698 | andw #PSL_IPL7,%d1 | mask all but PSL_IPL 699 | jne Lspldone | non-zero, all done 700 |Lsplsir: 701 | tstb _ssir | software interrupt pending? 702 | jeq Lspldone | no, all done 703 | subql #4,%sp | make room for RTE frame 704 | movl %sp@(4),%sp@(2) | position return address 705 | clrw %sp@(6) | set frame type 0 706 | movw #PSL_LOWIPL,%sp@ | and new SR 707 | jra Lgotsir | go handle it 708 |Lspldone: 709 rts 710 711 ENTRY(spl1) 712 moveq #0,%d0 713 movw %sr,%d0 714 movw #SPL1,%sr 715 rts 716 717 ALTENTRY(splscsi, _spl2) 718 ENTRY(spl2) 719 moveq #0,%d0 720 movw %sr,%d0 721 movw #SPL2,%sr 722 rts 723 724 ENTRY(spl3) 725 moveq #0,%d0 726 movw %sr,%d0 727 movw #SPL3,%sr 728 rts 729 730 ENTRY(spl4) 731 moveq #0,%d0 732 movw %sr,%d0 733 movw #SPL4,%sr 734 rts 735 736 ENTRY(spl5) 737 moveq #0,%d0 738 movw %sr,%d0 739 movw #SPL5,%sr 740 rts 741 742 ENTRY(spl6) 743 moveq #0,%d0 744 movw %sr,%d0 745 movw #SPL6,%sr 746 rts 747 748 ALTENTRY(splhigh, _spl7) 749 ENTRY(spl7) 750 moveq #0,%d0 751 movw %sr,%d0 752 movw #PSL_HIGHIPL,%sr 753 rts 754 755 756 .data 757 758 /* 759 * Memory Infomation Field for secondary booter memory allocator 760 */ 761 762 GLOBAL(prgcore) 763 .long 0 764 .long 0 765 .long 0 766 767 ASLOCAL(gotoROM) 768 .long 0 769 770 GLOBAL(dipsw1) 771 .long 0 772 773 GLOBAL(dipsw2) 774 .long 0 775 776 GLOBAL(cputype) 777 .long CPU_68030 778
Indexes created Sun Oct 26 13:09:57 GMT 2025