sioreg.h revision 1.4
1 /* $NetBSD: sioreg.h,v 1.4 2015/02/14 05:03:09 tsutsui Exp $ */ 2 3 /* 4 * Copyright (c) 1992 OMRON Corporation. 5 * 6 * This code is derived from software contributed to Berkeley by 7 * OMRON Corporation. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by the University of 20 * California, Berkeley and its contributors. 21 * 4. Neither the name of the University nor the names of its contributors 22 * may be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * @(#)sioreg.h 8.1 (Berkeley) 6/10/93 38 */ 39 /* 40 * Copyright (c) 1992, 1993 41 * The Regents of the University of California. All rights reserved. 42 * 43 * This code is derived from software contributed to Berkeley by 44 * OMRON Corporation. 45 * 46 * Redistribution and use in source and binary forms, with or without 47 * modification, are permitted provided that the following conditions 48 * are met: 49 * 1. Redistributions of source code must retain the above copyright 50 * notice, this list of conditions and the following disclaimer. 51 * 2. Redistributions in binary form must reproduce the above copyright 52 * notice, this list of conditions and the following disclaimer in the 53 * documentation and/or other materials provided with the distribution. 54 * 3. Neither the name of the University nor the names of its contributors 55 * may be used to endorse or promote products derived from this software 56 * without specific prior written permission. 57 * 58 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 59 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 60 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 61 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 62 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 63 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 64 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 65 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 66 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 67 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 68 * SUCH DAMAGE. 69 * 70 * @(#)sioreg.h 8.1 (Berkeley) 6/10/93 71 */ 72 73 /* sioreg.h NOV-26-1991 */ 74 75 struct siodevice { 76 volatile uint8_t sio_data; 77 uint8_t sio_pad1; 78 volatile uint8_t sio_cmd; 79 uint8_t sio_pad2; 80 }; 81 82 #define sio_stat sio_cmd 83 84 #define splsio spl6 85 86 87 #define REG(u, r) (((u) << 4) | (r)) 88 #define CHANNEL(r) ((r) >> 4) 89 #define REGNO(r) ((r) & 0x07) 90 #define isStatusReg(r) ((r) & 0x08) 91 92 #define WR0 0x00 93 #define WR1 0x01 94 #define WR2 0x02 95 #define WR3 0x03 96 #define WR4 0x04 97 #define WR5 0x05 98 #define WR6 0x06 99 #define WR7 0x07 100 101 #define WR2A 0x02 102 #define WR2B 0x12 103 104 #define RR0 0x08 105 #define RR1 0x09 106 #define RR2 0x0A 107 #define RR3 0x0B 108 #define RR4 0x0C 109 110 #define RR2A 0x0A 111 #define RR2B 0x1A 112 113 #define WR0_NOP 0x00 /* No Operation */ 114 #define WR0_SNDABRT 0x08 /* Send Abort (HDLC) */ 115 #define WR0_RSTINT 0x10 /* Reset External/Status Interrupt */ 116 #define WR0_CHANRST 0x18 /* Channel Reset */ 117 #define WR0_INTNXT 0x20 /* Enable Interrupt on Next Receive Character */ 118 #define WR0_RSTPEND 0x28 /* Reset Transmitter Interrput/DMA Pending */ 119 #define WR0_ERRRST 0x30 /* Error Reset */ 120 #define WR0_ENDINTR 0x38 /* End of Interrupt */ 121 122 #define WR1_ESENBL 0x01 /* External/Status Interrupt Enable */ 123 #define WR1_TXENBL 0x02 /* Tx Interrupt/DMA Enable */ 124 #define WR1_STATVEC 0x04 /* Status Affects Vector (Only Chan-B) */ 125 #define WR1_RXDSEBL 0x00 /* Rx Interrupt/DMA Disable */ 126 #define WR1_RXFIRST 0x08 /* Interrupt only First Character Received */ 127 #define WR1_RXALLS 0x10 /* Interrupt Every Characters Received (with Special Char.) */ 128 #define WR1_RXALL 0x18 /* Interrupt Every Characters Received (without Special Char.) */ 129 130 #define WR2_INTR_0 0x00 /* Interrupt Priority: RxA TxA RxB TxB E/SA E/SA */ 131 #define WR2_INTR_1 0x04 /* Interrupt Priority: RxA RxB TxA TxB E/SA E/SA */ 132 #define WR2_VEC85_1 0x00 /* 8085 Vectored Mode - 1 */ 133 #define WR2_VEC85_2 0x08 /* 8085 Vectored Mode - 2 */ 134 #define WR2_VEC86 0x10 /* 8086 Vectored */ 135 #define WR2_VEC85_3 0x18 /* 8085 Vectored Mode - 3 */ 136 137 #define WR3_RXENBL 0x01 /* Rx Enable */ 138 #define WR3_RXCRC 0x08 /* Rx CRC Check */ 139 #define WR3_AUTOEBL 0x20 /* Auto Enable (flow control for MODEM) */ 140 #define WR3_RX5BIT 0x00 /* Rx Bits/Character: 5 Bits */ 141 #define WR3_RX7BIT 0x40 /* Rx Bits/Character: 7 Bits */ 142 #define WR3_RX6BIT 0x80 /* Rx Bits/Character: 6 Bits */ 143 #define WR3_RX8BIT 0xc0 /* Rx Bits/Character: 8 Bits */ 144 145 #define WR4_NPARITY 0x00 /* No Parity */ 146 #define WR4_OPARITY 0x01 /* Parity Odd */ 147 #define WR4_EPARITY 0x02 /* Parity Even */ 148 #define WR4_STOP1 0x04 /* Stop Bits (1bit) */ 149 #define WR4_STOP15 0x08 /* Stop Bits (1.5bit) */ 150 #define WR4_STOP2 0x0c /* Stop Bits (2bit) */ 151 #define WR4_BAUD96 0x40 /* Clock Rate (9600 BAUD) */ 152 #define WR4_BAUD48 0x80 /* Clock Rate (4800 BAUD) */ 153 #define WR4_BAUD24 0xc0 /* Clock Rate (2400 BAUD) */ 154 155 #define WR5_TXCRC 0x01 /* Tx CRC Check */ 156 #define WR5_RTS 0x02 /* Request To Send [RTS] */ 157 #define WR5_TXENBL 0x08 /* Transmit Enable */ 158 #define WR5_BREAK 0x10 /* Send Break */ 159 #define WR5_TX5BIT 0x00 /* Tx Bits/Character: 5 Bits */ 160 #define WR5_TX7BIT 0x20 /* Tx Bits/Character: 7 Bits */ 161 #define WR5_TX6BIT 0x40 /* Tx Bits/Character: 6 Bits */ 162 #define WR5_TX8BIT 0x60 /* Tx Bits/Character: 8 Bits */ 163 #define WR5_DTR 0x80 /* Data Terminal Ready [DTR] */ 164 165 #define RR0_RXAVAIL 0x01 /* Rx Character Available */ 166 #define RR0_INTRPEND 0x02 /* Interrupt Pending (Channel-A Only) */ 167 #define RR0_TXEMPTY 0x04 /* Tx Buffer Empty */ 168 #define RR0_BREAK 0x80 /* Break Detected */ 169 170 #define RR1_PARITY 0x10 /* Parity Error */ 171 #define RR1_OVERRUN 0x20 /* Data Over Run */ 172 #define RR1_FRAMING 0x40 /* Framing Error */ 173
Indexes created Thu Oct 02 14:10:14 GMT 2025