README revision 1.2
11.2Sbriggs* $NetBSD: README,v 1.2 1995/11/03 04:48:22 briggs Exp $
21.1Sbriggs* NetBSD/m68k FPE (floating point emulation) README file
31.1Sbriggs* Created Oct/??/95 by kenn@romulus.rutgers.edu (Ken Nakata)
41.1Sbriggs* Last updated Nov/02/95 by kenn
51.1Sbriggs
61.1Sbriggs1. INSTALLATION AND COMPILATION
71.1Sbriggs
81.1SbriggsTo compile a kernel with FPE built-in, do the following:
91.1Sbriggs
101.2Sbriggs1) Add a line "options FPU_EMULATE" to your config file.  If you are
111.1Sbriggsgoing to use the resulted kernel on a machine with an FPU for
121.1Sbriggsdebugging purpose, add "options DEBUG_WITH_FPU" as well.
131.1Sbriggs
141.2Sbriggs2) Follow the usual procedure to build a new kernel.
151.1Sbriggs
161.1SbriggsNOTE:  If you add "options DEBUG_WITH_FPU", FPE will accept cpID=6 as
171.1Sbriggsemulated FPU.  You will need a modified gas that generates cpID=6 for
181.1Sbriggsfloating point instructions, instead of normal cpID=1.  Mount unionfs
191.1Sbriggsor copy the gas source directory as you did with the kernel source tree,
201.1Sbriggsand apply the following patch:
211.1Sbriggs
221.1Sbriggs*** /usr/src/gnu/usr.bin/gas/config/tc-m68k.c   Mon Nov 21 16:30:41 1994
231.1Sbriggs--- gas/config/tc-m68k.c    Fri Sep 29 07:59:06 1995
241.1Sbriggs***************
251.1Sbriggs*** 1275,1281 ****
261.1Sbriggs                /* memcpy((char *)(&the_ins.operands[1]), (char *)(&the_ins.operands[0]), opsfound*sizeof(the_ins.operands[0])); */
271.1Sbriggs                memset((char *)(&the_ins.operands[0]), '\0', sizeof(the_ins.operands[0]));
281.1Sbriggs                the_ins.operands[0].mode=MSCR;
291.1Sbriggs!               the_ins.operands[0].reg=COPNUM;         /* COP #1 */
301.1Sbriggs                opsfound++;
311.1Sbriggs        }
321.1Sbriggs  
331.1Sbriggs--- 1275,1281 ----
341.1Sbriggs                /* memcpy((char *)(&the_ins.operands[1]), (char *)(&the_ins.operands[0]), opsfound*sizeof(the_ins.operands[0])); */
351.1Sbriggs                memset((char *)(&the_ins.operands[0]), '\0', sizeof(the_ins.operands[0]));
361.1Sbriggs                the_ins.operands[0].mode=MSCR;
371.1Sbriggs!               the_ins.operands[0].reg=COP5;           /* COP #6 */
381.1Sbriggs                opsfound++;
391.1Sbriggs        }
401.1Sbriggs  
411.1Sbriggs
421.1SbriggsAlso, with the DEBUG_WITH_FPU option, you will be able to run only ONE
431.1Sbriggsprocess that uses FPE at once to get correct results.
441.1Sbriggs
451.1Sbriggs
461.1Sbriggs2. MISSING PARTS
471.1Sbriggs
481.1SbriggsFor missing instructions, refer to the Section 3.  Other than that,
491.1Sbriggsthere is one thing that is missing from this version of FPE: packed
501.1SbriggsBCD support.
511.1Sbriggs
521.1SbriggsI have no plan to support it since it's rarely used.  However, all we
531.1Sbriggsneed to support it is explosion/implosion functions between the
541.1Sbriggsinternal FP representation and the m68k PBCD format, so you are more
551.1Sbriggsthan welcome to write such functions if you wish to.
561.1Sbriggs
571.1Sbriggs
581.1Sbriggs3. IMPLEMENTED INSTRUCTIONS
591.1Sbriggs
601.1SbriggsThis is the list of implemented and unimplemented FPU instructions.
611.1SbriggsMost 040's directly supported type 0 instructions are already
621.1Sbriggsimplemented except FSGLDIV, FSGLMUL, FMOVE(M) FPcr, and FMOVECR.
631.1Sbriggs
641.1SbriggsType field = bit 8-6 of opcode word
651.1Sbriggs
661.1Sbriggs* Implemented Instructions
671.1Sbriggs
681.1SbriggsType=0: FMOVE (mem->FPr), FINT, FINTRZ, FSQRT, FABS, FNEG, FGETEXP,
691.1Sbriggs	FGETMAN, FDIV, FADD, FMUL, FSGLDIV, FSCALE, FSGLMUL, FSUB,
701.1Sbriggs	FCMP, FTST, FMOVE (FPr->mem), FMOVEM (FPr), FMOVEM (FPcr),
711.1Sbriggs	FMOVECR, FLOGNP1, FLOGN, FLOG10, FLOG2, FMOD, FREM
721.1Sbriggs
731.1SbriggsType=1: FDBcc, FScc, FTRAPcc,
741.1Sbriggs
751.1SbriggsType=2: FBcc (word, incl. FNOP)
761.1Sbriggs
771.1SbriggsType=3: FBcc (long)
781.1Sbriggs
791.1SbriggsType=4: none
801.1Sbriggs
811.1SbriggsType=5: none
821.1Sbriggs
831.1Sbriggs	*: currently FSGLMUL and FSGLDIV are just aliases of
841.1Sbriggs	   FMUL and FDIV, respectively
851.1Sbriggs
861.1Sbriggs* Unimplemented Instructions
871.1Sbriggs
881.1SbriggsType=0: FSINH, FETOXM1, FTANH, FATAN, FASIN, FATANH, FSIN, FTAN,
891.1Sbriggs	FETOX, FTWOTOX, FTENTOX, FCOSH, FACOS, FCOS, FSINCOS
901.1Sbriggs
911.1SbriggsType=1: none
921.1Sbriggs
931.1SbriggsType=2: none
941.1Sbriggs
951.1SbriggsType=3: none
961.1Sbriggs
971.1SbriggsType=4: FSAVE
981.1Sbriggs
991.1SbriggsType=5: FRESTORE
1001.1Sbriggs
1011.1Sbriggs
1021.1Sbriggs4. HOW TO ADD A NEW INSTRUCTION SUPPORT
1031.1Sbriggs
1041.1SbriggsSince we need not support FSAVE and FRESTORE operations, all
1051.1Sbriggsinstructions we have to implement are type 0, all of which are
1061.1Sbriggsarithmetic operations.  It is particularly easy to add a new
1071.1Sbriggsarithmetic instruction to the existing ones (not that it is easy to
1081.1Sbriggswrite a "stable" function to perform floating point operation. That's
1091.1Sbriggsentirely another matter).  In "fpu_emulate.c", there's a function
1101.1Sbriggsfpu_emul_arith() which calls emulation functions for all arithmetic
1111.1Sbriggsoperations.  In it, there's a large switch() { case ... } which
1121.1Sbriggsdispatches each instruction emulator.  An emulation function of any
1131.1Sbriggstype 0 arithmetic instruction follows this prototype:
1141.1Sbriggs
1151.1Sbriggs	struct fpn *fpu_op(struct fpemu *fe);
1161.1Sbriggs
1171.1SbriggsWhere fe is a pointer to a struct fpemu in which frame, fpframe, and
1181.1Sbriggsfetched operands are accessible.  That's right, you don't have to
1191.1Sbriggsfetch the operands by yourself in your emulation funtion.  For
1201.1Sbriggsinstance, the parts calling FSQRT, FSUB, FADD and FTST look like:
1211.1Sbriggs
1221.1Sbriggs	switch(word1 & 0x3F) {
1231.1Sbriggs[...]
1241.1Sbriggs	case 0x04:	/* fsqrt */
1251.1Sbriggs		res = fpu_sqrt(fe);
1261.1Sbriggs		break;
1271.1Sbriggs[...]
1281.1Sbriggs	case 0x28:	/* fsub */
1291.1Sbriggs		fe->fe_f2.fp_sign = !fe->fe_f2.fp_sign; /* f2 = -f2 */
1301.1Sbriggs	case 0x22:	/* fadd */
1311.1Sbriggs		res = fpu_add(fe);
1321.1Sbriggs		break;
1331.1Sbriggs[...]
1341.1Sbriggs	case 0x3A:	/* ftst */
1351.1Sbriggs		res = &fe->fe_f2;
1361.1Sbriggs		no_store = 1;
1371.1Sbriggs		break;
1381.1Sbriggs[...]
1391.1Sbriggs	default:
1401.1Sbriggs		sig = SIGILL;
1411.1Sbriggs	} /* switch */
1421.1Sbriggs
1431.1SbriggsHere, fe->fe_f1 and fe->fe_f2 are fetched operands.  You can use
1441.1Sbriggsfe->fe_f3 for storing the result, or you can return a pointer to
1451.1Sbriggseither operand if you want to.  At any rate, you have to follow
1461.1Sbriggsthe following rules:
1471.1Sbriggs
1481.1Sbriggs	1) A dyadic instruction takes two operands fe->fe_f1 and fe->fe_f2.
1491.1Sbriggs	2) A monadic instruction takes one operands fe->fe_f2 (NOT fe_f1).
1501.1Sbriggs	3) Must return a pointer to struct fpn where the result is stored,
1511.1Sbriggs	and assign the pointer to the variable "res".
1521.1Sbriggs	4) If exceptions are detected, set corresponding bits in fe->fe_fpsr.
1531.1Sbriggs	The rest is taken care of in fpu_emul_arith().
1541.1Sbriggs	5) Condition code need not be calculated.  It's taken care of in
1551.1Sbriggs	fpu_emul_arith().
1561.1Sbriggs
1571.1SbriggsIt's easy to interface, isn't it?
1581.1Sbriggs
1591.1Sbriggs* Actually, after above was written, stubs for the missing functions
1601.1Sbriggsare added to the source, so you do not have to change fpu_emul_arith()
1611.1Sbriggsat all.  Function names and prototypes are in fpu_arith_proto.h, and
1621.1Sbriggsall (except fpu_sincos()) follows the rules above.
1631.1Sbriggs
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