fpu_calcea.c revision 1.8 1 1.8 briggs /* $NetBSD: fpu_calcea.c,v 1.8 1999/05/30 20:17:48 briggs Exp $ */
2 1.1 briggs
3 1.1 briggs /*
4 1.1 briggs * Copyright (c) 1995 Gordon W. Ross
5 1.1 briggs * portion Copyright (c) 1995 Ken Nakata
6 1.1 briggs * All rights reserved.
7 1.1 briggs *
8 1.1 briggs * Redistribution and use in source and binary forms, with or without
9 1.1 briggs * modification, are permitted provided that the following conditions
10 1.1 briggs * are met:
11 1.1 briggs * 1. Redistributions of source code must retain the above copyright
12 1.1 briggs * notice, this list of conditions and the following disclaimer.
13 1.1 briggs * 2. Redistributions in binary form must reproduce the above copyright
14 1.1 briggs * notice, this list of conditions and the following disclaimer in the
15 1.1 briggs * documentation and/or other materials provided with the distribution.
16 1.1 briggs * 3. The name of the author may not be used to endorse or promote products
17 1.1 briggs * derived from this software without specific prior written permission.
18 1.1 briggs * 4. All advertising materials mentioning features or use of this software
19 1.1 briggs * must display the following acknowledgement:
20 1.1 briggs * This product includes software developed by Gordon Ross
21 1.1 briggs *
22 1.1 briggs * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
23 1.1 briggs * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
24 1.1 briggs * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
25 1.1 briggs * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
26 1.1 briggs * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 1.1 briggs * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 1.1 briggs * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 1.1 briggs * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 1.1 briggs * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 1.1 briggs * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 1.1 briggs */
33 1.1 briggs
34 1.3 briggs #include <sys/param.h>
35 1.1 briggs #include <sys/signal.h>
36 1.4 briggs #include <sys/systm.h>
37 1.1 briggs #include <machine/frame.h>
38 1.1 briggs
39 1.1 briggs #include "fpu_emulate.h"
40 1.1 briggs
41 1.1 briggs /*
42 1.1 briggs * Prototypes of static functions
43 1.1 briggs */
44 1.1 briggs static int decode_ea6 __P((struct frame *frame, struct instruction *insn,
45 1.1 briggs struct insn_ea *ea, int modreg));
46 1.1 briggs static int fetch_immed __P((struct frame *frame, struct instruction *insn,
47 1.1 briggs int *dst));
48 1.1 briggs static int fetch_disp __P((struct frame *frame, struct instruction *insn,
49 1.1 briggs int size, int *res));
50 1.1 briggs static int calc_ea __P((struct insn_ea *ea, char *ptr, char **eaddr));
51 1.4 briggs
52 1.1 briggs /*
53 1.1 briggs * Helper routines for dealing with "effective address" values.
54 1.1 briggs */
55 1.1 briggs
56 1.1 briggs /*
57 1.1 briggs * Decode an effective address into internal form.
58 1.1 briggs * Returns zero on success, else signal number.
59 1.1 briggs */
60 1.1 briggs int
61 1.1 briggs fpu_decode_ea(frame, insn, ea, modreg)
62 1.1 briggs struct frame *frame;
63 1.1 briggs struct instruction *insn;
64 1.1 briggs struct insn_ea *ea;
65 1.1 briggs int modreg;
66 1.1 briggs {
67 1.4 briggs int sig;
68 1.1 briggs
69 1.1 briggs #ifdef DEBUG
70 1.1 briggs if (insn->is_datasize < 0) {
71 1.1 briggs panic("decode_ea: called with uninitialized datasize\n");
72 1.1 briggs }
73 1.1 briggs #endif
74 1.1 briggs
75 1.1 briggs sig = 0;
76 1.1 briggs
77 1.1 briggs /* Set the most common value here. */
78 1.1 briggs ea->ea_regnum = 8 + (modreg & 7);
79 1.1 briggs
80 1.8 briggs if ((modreg & 060) == 0) {
81 1.8 briggs /* register direct */
82 1.8 briggs ea->ea_regnum = modreg & 0xf;
83 1.1 briggs ea->ea_flags = EA_DIRECT;
84 1.8 briggs #ifdef DEBUG_FPE
85 1.8 briggs printf("decode_ea: register direct reg=%d\n", ea->ea_regnum);
86 1.8 briggs #endif
87 1.8 briggs } else if (modreg == 074) {
88 1.8 briggs /* immediate */
89 1.8 briggs ea->ea_flags = EA_IMMED;
90 1.8 briggs sig = fetch_immed(frame, insn, &ea->ea_immed[0]);
91 1.8 briggs #ifdef DEBUG_FPE
92 1.8 briggs printf("decode_ea: immediate size=%d\n", insn->is_datasize);
93 1.8 briggs #endif
94 1.8 briggs }
95 1.8 briggs /*
96 1.8 briggs * rest of the address modes need to be separately
97 1.8 briggs * handled for the LC040 and the others.
98 1.8 briggs */
99 1.8 briggs else if (frame->f_format == 4) {
100 1.8 briggs /* LC040 */
101 1.8 briggs ea->ea_flags = EA_FRAME_EA;
102 1.8 briggs ea->ea_fea = frame->f_fmt4.f_fa;
103 1.8 briggs #ifdef DEBUG_FPE
104 1.8 briggs printf("decode_ea: 68LC040 - in-frame EA (%p)\n", (void *)ea->ea_fea);
105 1.8 briggs #endif
106 1.8 briggs if ((modreg & 070) == 030) {
107 1.8 briggs /* postincrement mode */
108 1.8 briggs ea->ea_flags |= EA_POSTINCR;
109 1.8 briggs } else if ((modreg & 070) == 040) {
110 1.8 briggs /* predecrement mode */
111 1.8 briggs ea->ea_flags |= EA_PREDECR;
112 1.1 briggs }
113 1.8 briggs } else {
114 1.8 briggs /* 020/030 */
115 1.8 briggs switch (modreg & 070) {
116 1.1 briggs
117 1.8 briggs case 020: /* (An) */
118 1.8 briggs ea->ea_flags = 0;
119 1.8 briggs #ifdef DEBUG_FPE
120 1.8 briggs printf("decode_ea: register indirect reg=%d\n", ea->ea_regnum);
121 1.8 briggs #endif
122 1.8 briggs break;
123 1.1 briggs
124 1.8 briggs case 030: /* (An)+ */
125 1.8 briggs ea->ea_flags = EA_POSTINCR;
126 1.8 briggs #ifdef DEBUG_FPE
127 1.8 briggs printf("decode_ea: reg indirect postincrement reg=%d\n",
128 1.1 briggs ea->ea_regnum);
129 1.8 briggs #endif
130 1.8 briggs break;
131 1.1 briggs
132 1.8 briggs case 040: /* -(An) */
133 1.8 briggs ea->ea_flags = EA_PREDECR;
134 1.8 briggs #ifdef DEBUG_FPE
135 1.8 briggs printf("decode_ea: reg indirect predecrement reg=%d\n",
136 1.1 briggs ea->ea_regnum);
137 1.8 briggs #endif
138 1.1 briggs break;
139 1.1 briggs
140 1.8 briggs case 050: /* (d16,An) */
141 1.8 briggs ea->ea_flags = EA_OFFSET;
142 1.8 briggs sig = fetch_disp(frame, insn, 1, &ea->ea_offset);
143 1.8 briggs #ifdef DEBUG_FPE
144 1.8 briggs printf("decode_ea: reg indirect with displacement reg=%d\n",
145 1.8 briggs ea->ea_regnum);
146 1.8 briggs #endif
147 1.1 briggs break;
148 1.1 briggs
149 1.8 briggs case 060: /* (d8,An,Xn) */
150 1.8 briggs ea->ea_flags = EA_INDEXED;
151 1.8 briggs sig = decode_ea6(frame, insn, ea, modreg);
152 1.1 briggs break;
153 1.1 briggs
154 1.8 briggs case 070: /* misc. */
155 1.8 briggs ea->ea_regnum = (modreg & 7);
156 1.8 briggs switch (modreg & 7) {
157 1.8 briggs
158 1.8 briggs case 0: /* (xxxx).W */
159 1.8 briggs ea->ea_flags = EA_ABS;
160 1.8 briggs sig = fetch_disp(frame, insn, 1, &ea->ea_absaddr);
161 1.8 briggs #ifdef DEBUG_FPE
162 1.8 briggs printf("decode_ea: absolute address (word)\n");
163 1.8 briggs #endif
164 1.8 briggs break;
165 1.1 briggs
166 1.8 briggs case 1: /* (xxxxxxxx).L */
167 1.8 briggs ea->ea_flags = EA_ABS;
168 1.8 briggs sig = fetch_disp(frame, insn, 2, &ea->ea_absaddr);
169 1.8 briggs #ifdef DEBUG_FPE
170 1.8 briggs printf("decode_ea: absolute address (long)\n");
171 1.8 briggs #endif
172 1.8 briggs break;
173 1.1 briggs
174 1.8 briggs case 2: /* (d16,PC) */
175 1.8 briggs ea->ea_flags = EA_PC_REL | EA_OFFSET;
176 1.8 briggs sig = fetch_disp(frame, insn, 1, &ea->ea_absaddr);
177 1.8 briggs #ifdef DEBUG_FPE
178 1.8 briggs printf("decode_ea: pc relative word displacement\n");
179 1.8 briggs #endif
180 1.8 briggs break;
181 1.1 briggs
182 1.8 briggs case 3: /* (d8,PC,Xn) */
183 1.8 briggs ea->ea_flags = EA_PC_REL | EA_INDEXED;
184 1.8 briggs sig = decode_ea6(frame, insn, ea, modreg);
185 1.8 briggs break;
186 1.8 briggs
187 1.8 briggs case 4: /* #data */
188 1.8 briggs /* it should have been taken care of earlier */
189 1.8 briggs default:
190 1.8 briggs #ifdef DEBUG_FPE
191 1.8 briggs printf("decode_ea: invalid addr mode (7,%d)\n", modreg & 7);
192 1.8 briggs #endif
193 1.8 briggs return SIGILL;
194 1.8 briggs } /* switch for mode 7 */
195 1.8 briggs break;
196 1.8 briggs } /* switch mode */
197 1.8 briggs }
198 1.8 briggs ea->ea_moffs = 0;
199 1.1 briggs
200 1.1 briggs return sig;
201 1.1 briggs }
202 1.1 briggs
203 1.1 briggs /*
204 1.1 briggs * Decode Mode=6 address modes
205 1.1 briggs */
206 1.1 briggs static int
207 1.1 briggs decode_ea6(frame, insn, ea, modreg)
208 1.1 briggs struct frame *frame;
209 1.1 briggs struct instruction *insn;
210 1.1 briggs struct insn_ea *ea;
211 1.1 briggs int modreg;
212 1.1 briggs {
213 1.4 briggs int extword, idx;
214 1.1 briggs int basedisp, outerdisp;
215 1.1 briggs int bd_size, od_size;
216 1.1 briggs int sig;
217 1.1 briggs
218 1.8 briggs extword = fusword((void *) (insn->is_pc + insn->is_advance));
219 1.1 briggs if (extword < 0) {
220 1.1 briggs return SIGSEGV;
221 1.1 briggs }
222 1.1 briggs insn->is_advance += 2;
223 1.1 briggs
224 1.1 briggs /* get register index */
225 1.1 briggs ea->ea_idxreg = (extword >> 12) & 0xf;
226 1.1 briggs idx = frame->f_regs[ea->ea_idxreg];
227 1.1 briggs if ((extword & 0x0800) == 0) {
228 1.1 briggs /* if word sized index, sign-extend */
229 1.1 briggs idx &= 0xffff;
230 1.1 briggs if (idx & 0x8000) {
231 1.1 briggs idx |= 0xffff0000;
232 1.1 briggs }
233 1.1 briggs }
234 1.1 briggs /* scale register index */
235 1.1 briggs idx <<= ((extword >>9) & 3);
236 1.1 briggs
237 1.1 briggs if ((extword & 0x100) == 0) {
238 1.1 briggs /* brief extention word - sign-extend the displacement */
239 1.1 briggs basedisp = (extword & 0xff);
240 1.1 briggs if (basedisp & 0x80) {
241 1.1 briggs basedisp |= 0xffffff00;
242 1.1 briggs }
243 1.1 briggs
244 1.1 briggs ea->ea_basedisp = idx + basedisp;
245 1.1 briggs ea->ea_outerdisp = 0;
246 1.8 briggs #if DEBUG_FPE
247 1.8 briggs printf("decode_ea6: brief ext word idxreg=%d, basedisp=%08x\n",
248 1.8 briggs ea->ea_idxreg, ea->ea_basedisp);
249 1.8 briggs #endif
250 1.1 briggs } else {
251 1.1 briggs /* full extention word */
252 1.1 briggs if (extword & 0x80) {
253 1.1 briggs ea->ea_flags |= EA_BASE_SUPPRSS;
254 1.1 briggs }
255 1.1 briggs bd_size = ((extword >> 4) & 3) - 1;
256 1.1 briggs od_size = (extword & 3) - 1;
257 1.1 briggs sig = fetch_disp(frame, insn, bd_size, &basedisp);
258 1.1 briggs if (sig) {
259 1.1 briggs return sig;
260 1.1 briggs }
261 1.1 briggs if (od_size >= 0) {
262 1.1 briggs ea->ea_flags |= EA_MEM_INDIR;
263 1.1 briggs }
264 1.1 briggs sig = fetch_disp(frame, insn, od_size, &outerdisp);
265 1.1 briggs if (sig) {
266 1.1 briggs return sig;
267 1.1 briggs }
268 1.1 briggs
269 1.1 briggs switch (extword & 0x44) {
270 1.1 briggs case 0: /* preindexed */
271 1.1 briggs ea->ea_basedisp = basedisp + idx;
272 1.1 briggs ea->ea_outerdisp = outerdisp;
273 1.1 briggs break;
274 1.1 briggs case 4: /* postindexed */
275 1.1 briggs ea->ea_basedisp = basedisp;
276 1.1 briggs ea->ea_outerdisp = outerdisp + idx;
277 1.1 briggs break;
278 1.1 briggs case 0x40: /* no index */
279 1.1 briggs ea->ea_basedisp = basedisp;
280 1.1 briggs ea->ea_outerdisp = outerdisp;
281 1.1 briggs break;
282 1.1 briggs default:
283 1.1 briggs #ifdef DEBUG
284 1.8 briggs printf("decode_ea6: invalid indirect mode: ext word %04x\n",
285 1.1 briggs extword);
286 1.1 briggs #endif
287 1.1 briggs return SIGILL;
288 1.1 briggs break;
289 1.1 briggs }
290 1.8 briggs #if DEBUG_FPE
291 1.8 briggs printf("decode_ea6: full ext idxreg=%d, basedisp=%x, outerdisp=%x\n",
292 1.8 briggs ea->ea_idxreg, ea->ea_basedisp, ea->ea_outerdisp);
293 1.8 briggs #endif
294 1.1 briggs }
295 1.8 briggs #if DEBUG_FPE
296 1.8 briggs printf("decode_ea6: regnum=%d, flags=%x\n",
297 1.8 briggs ea->ea_regnum, ea->ea_flags);
298 1.8 briggs #endif
299 1.1 briggs return 0;
300 1.1 briggs }
301 1.1 briggs
302 1.1 briggs /*
303 1.1 briggs * Load a value from an effective address.
304 1.1 briggs * Returns zero on success, else signal number.
305 1.1 briggs */
306 1.1 briggs int
307 1.1 briggs fpu_load_ea(frame, insn, ea, dst)
308 1.1 briggs struct frame *frame;
309 1.1 briggs struct instruction *insn;
310 1.1 briggs struct insn_ea *ea;
311 1.1 briggs char *dst;
312 1.1 briggs {
313 1.1 briggs int *reg;
314 1.1 briggs char *src;
315 1.1 briggs int len, step;
316 1.4 briggs int sig;
317 1.1 briggs
318 1.8 briggs #ifdef DIAGNOSTIC
319 1.1 briggs if (ea->ea_regnum & ~0xF) {
320 1.8 briggs panic("load_ea: bad regnum");
321 1.1 briggs }
322 1.1 briggs #endif
323 1.1 briggs
324 1.8 briggs #ifdef DEBUG_FPE
325 1.8 briggs printf("load_ea: frame at %p\n", frame);
326 1.8 briggs #endif
327 1.8 briggs /* dst is always int or larger. */
328 1.1 briggs len = insn->is_datasize;
329 1.1 briggs if (len < 4) {
330 1.1 briggs dst += (4 - len);
331 1.1 briggs }
332 1.1 briggs step = (len == 1 && ea->ea_regnum == 15 /* sp */) ? 2 : len;
333 1.1 briggs
334 1.8 briggs if (ea->ea_flags & EA_FRAME_EA) {
335 1.8 briggs /* Using LC040 frame EA */
336 1.8 briggs #ifdef DEBUG_FPE
337 1.8 briggs if (ea->ea_flags & (EA_PREDECR|EA_POSTINCR)) {
338 1.8 briggs printf("load_ea: frame ea %08x w/r%d\n",
339 1.8 briggs ea->ea_fea, ea->ea_regnum);
340 1.8 briggs } else {
341 1.8 briggs printf("load_ea: frame ea %08x\n", ea->ea_fea);
342 1.8 briggs }
343 1.8 briggs #endif
344 1.8 briggs src = (char *)ea->ea_fea;
345 1.8 briggs copyin(src + ea->ea_moffs, dst, len);
346 1.8 briggs if (ea->ea_flags & EA_PREDECR) {
347 1.8 briggs frame->f_regs[ea->ea_regnum] = ea->ea_fea;
348 1.8 briggs ea->ea_fea -= step;
349 1.8 briggs ea->ea_moffs = 0;
350 1.8 briggs } else if (ea->ea_flags & EA_POSTINCR) {
351 1.8 briggs ea->ea_fea += step;
352 1.8 briggs frame->f_regs[ea->ea_regnum] = ea->ea_fea;
353 1.8 briggs ea->ea_moffs = 0;
354 1.8 briggs } else {
355 1.8 briggs ea->ea_moffs += step;
356 1.8 briggs }
357 1.8 briggs /* That's it, folks */
358 1.8 briggs } else if (ea->ea_flags & EA_DIRECT) {
359 1.1 briggs if (len > 4) {
360 1.1 briggs #ifdef DEBUG
361 1.8 briggs printf("load_ea: operand doesn't fit cpu reg\n");
362 1.1 briggs #endif
363 1.1 briggs return SIGILL;
364 1.1 briggs }
365 1.8 briggs if (ea->ea_moffs > 0) {
366 1.1 briggs #ifdef DEBUG
367 1.8 briggs printf("load_ea: more than one move from cpu reg\n");
368 1.1 briggs #endif
369 1.1 briggs return SIGILL;
370 1.1 briggs }
371 1.1 briggs src = (char *)&frame->f_regs[ea->ea_regnum];
372 1.1 briggs /* The source is an int. */
373 1.1 briggs if (len < 4) {
374 1.1 briggs src += (4 - len);
375 1.8 briggs #ifdef DEBUG_FPE
376 1.8 briggs printf("load_ea: short/byte opr - addr adjusted\n");
377 1.8 briggs #endif
378 1.1 briggs }
379 1.8 briggs #ifdef DEBUG_FPE
380 1.8 briggs printf("load_ea: src %p\n", src);
381 1.8 briggs #endif
382 1.1 briggs bcopy(src, dst, len);
383 1.1 briggs } else if (ea->ea_flags & EA_IMMED) {
384 1.8 briggs #ifdef DEBUG_FPE
385 1.8 briggs printf("load_ea: immed %08x%08x%08x size %d\n",
386 1.8 briggs ea->ea_immed[0], ea->ea_immed[1], ea->ea_immed[2], len);
387 1.8 briggs #endif
388 1.1 briggs src = (char *)&ea->ea_immed[0];
389 1.1 briggs if (len < 4) {
390 1.1 briggs src += (4 - len);
391 1.8 briggs #ifdef DEBUG_FPE
392 1.8 briggs printf("load_ea: short/byte immed opr - addr adjusted\n");
393 1.8 briggs #endif
394 1.1 briggs }
395 1.1 briggs bcopy(src, dst, len);
396 1.1 briggs } else if (ea->ea_flags & EA_ABS) {
397 1.8 briggs #ifdef DEBUG_FPE
398 1.8 briggs printf("load_ea: abs addr %08x\n", ea->ea_absaddr);
399 1.8 briggs #endif
400 1.1 briggs src = (char *)ea->ea_absaddr;
401 1.1 briggs copyin(src, dst, len);
402 1.1 briggs } else /* register indirect */ {
403 1.1 briggs if (ea->ea_flags & EA_PC_REL) {
404 1.8 briggs #ifdef DEBUG_FPE
405 1.8 briggs printf("load_ea: using PC\n");
406 1.8 briggs #endif
407 1.1 briggs reg = NULL;
408 1.1 briggs /* Grab the register contents. 4 is offset to the first
409 1.1 briggs extention word from the opcode */
410 1.8 briggs src = (char *)insn->is_pc + 4;
411 1.8 briggs #ifdef DEBUG_FPE
412 1.8 briggs printf("load_ea: pc relative pc+4 = %p\n", src);
413 1.8 briggs #endif
414 1.1 briggs } else /* not PC relative */ {
415 1.8 briggs #ifdef DEBUG_FPE
416 1.8 briggs printf("load_ea: using register %c%d\n",
417 1.8 briggs (ea->ea_regnum >= 8) ? 'a' : 'd', ea->ea_regnum & 7);
418 1.8 briggs #endif
419 1.1 briggs /* point to the register */
420 1.1 briggs reg = &frame->f_regs[ea->ea_regnum];
421 1.1 briggs
422 1.1 briggs if (ea->ea_flags & EA_PREDECR) {
423 1.8 briggs #ifdef DEBUG_FPE
424 1.8 briggs printf("load_ea: predecr mode - reg decremented\n");
425 1.8 briggs #endif
426 1.1 briggs *reg -= step;
427 1.8 briggs ea->ea_moffs = 0;
428 1.1 briggs }
429 1.1 briggs
430 1.1 briggs /* Grab the register contents. */
431 1.1 briggs src = (char *)*reg;
432 1.8 briggs #ifdef DEBUG_FPE
433 1.8 briggs printf("load_ea: reg indirect reg = %p\n", src);
434 1.8 briggs #endif
435 1.1 briggs }
436 1.1 briggs
437 1.1 briggs sig = calc_ea(ea, src, &src);
438 1.1 briggs if (sig)
439 1.1 briggs return sig;
440 1.1 briggs
441 1.8 briggs copyin(src + ea->ea_moffs, dst, len);
442 1.1 briggs
443 1.1 briggs /* do post-increment */
444 1.1 briggs if (ea->ea_flags & EA_POSTINCR) {
445 1.1 briggs if (ea->ea_flags & EA_PC_REL) {
446 1.1 briggs #ifdef DEBUG
447 1.8 briggs printf("load_ea: tried to postincrement PC\n");
448 1.1 briggs #endif
449 1.1 briggs return SIGILL;
450 1.1 briggs }
451 1.1 briggs *reg += step;
452 1.8 briggs ea->ea_moffs = 0;
453 1.8 briggs #ifdef DEBUG_FPE
454 1.8 briggs printf("load_ea: postinc mode - reg incremented\n");
455 1.8 briggs #endif
456 1.1 briggs } else {
457 1.8 briggs ea->ea_moffs += len;
458 1.1 briggs }
459 1.1 briggs }
460 1.1 briggs
461 1.1 briggs return 0;
462 1.1 briggs }
463 1.1 briggs
464 1.1 briggs /*
465 1.1 briggs * Store a value at the effective address.
466 1.1 briggs * Returns zero on success, else signal number.
467 1.1 briggs */
468 1.1 briggs int
469 1.1 briggs fpu_store_ea(frame, insn, ea, src)
470 1.1 briggs struct frame *frame;
471 1.1 briggs struct instruction *insn;
472 1.1 briggs struct insn_ea *ea;
473 1.1 briggs char *src;
474 1.1 briggs {
475 1.1 briggs int *reg;
476 1.1 briggs char *dst;
477 1.1 briggs int len, step;
478 1.4 briggs int sig;
479 1.1 briggs
480 1.1 briggs #ifdef DIAGNOSTIC
481 1.8 briggs if (ea->ea_regnum & ~0xf) {
482 1.8 briggs panic("store_ea: bad regnum");
483 1.1 briggs }
484 1.1 briggs #endif
485 1.1 briggs
486 1.1 briggs if (ea->ea_flags & (EA_IMMED|EA_PC_REL)) {
487 1.1 briggs /* not alterable address mode */
488 1.1 briggs #ifdef DEBUG
489 1.8 briggs printf("store_ea: not alterable address mode\n");
490 1.1 briggs #endif
491 1.1 briggs return SIGILL;
492 1.1 briggs }
493 1.1 briggs
494 1.8 briggs /* src is always int or larger. */
495 1.1 briggs len = insn->is_datasize;
496 1.1 briggs if (len < 4) {
497 1.1 briggs src += (4 - len);
498 1.1 briggs }
499 1.1 briggs step = (len == 1 && ea->ea_regnum == 15 /* sp */) ? 2 : len;
500 1.1 briggs
501 1.8 briggs if (ea->ea_flags & EA_FRAME_EA) {
502 1.8 briggs /* Using LC040 frame EA */
503 1.8 briggs #ifdef DEBUG_FPE
504 1.8 briggs if (ea->ea_flags & (EA_PREDECR|EA_POSTINCR)) {
505 1.8 briggs printf("store_ea: frame ea %08x w/r%d\n",
506 1.8 briggs ea->ea_fea, ea->ea_regnum);
507 1.8 briggs } else {
508 1.8 briggs printf("store_ea: frame ea %08x\n", ea->ea_fea);
509 1.8 briggs }
510 1.8 briggs #endif
511 1.8 briggs dst = (char *)ea->ea_fea;
512 1.8 briggs copyout(src, dst + ea->ea_moffs, len);
513 1.8 briggs if (ea->ea_flags & EA_PREDECR) {
514 1.8 briggs frame->f_regs[ea->ea_regnum] = ea->ea_fea;
515 1.8 briggs ea->ea_fea -= step;
516 1.8 briggs ea->ea_moffs = 0;
517 1.8 briggs } else if (ea->ea_flags & EA_POSTINCR) {
518 1.8 briggs ea->ea_fea += step;
519 1.8 briggs frame->f_regs[ea->ea_regnum] = ea->ea_fea;
520 1.8 briggs ea->ea_moffs = 0;
521 1.8 briggs } else {
522 1.8 briggs ea->ea_moffs += step;
523 1.1 briggs }
524 1.8 briggs /* That's it, folks */
525 1.8 briggs } else if (ea->ea_flags & EA_ABS) {
526 1.8 briggs #ifdef DEBUG_FPE
527 1.8 briggs printf("store_ea: abs addr %08x\n", ea->ea_absaddr);
528 1.8 briggs #endif
529 1.1 briggs dst = (char *)ea->ea_absaddr;
530 1.8 briggs copyout(src, dst + ea->ea_moffs, len);
531 1.8 briggs ea->ea_moffs += len;
532 1.1 briggs } else if (ea->ea_flags & EA_DIRECT) {
533 1.1 briggs if (len > 4) {
534 1.1 briggs #ifdef DEBUG
535 1.8 briggs printf("store_ea: operand doesn't fit cpu reg\n");
536 1.1 briggs #endif
537 1.1 briggs return SIGILL;
538 1.1 briggs }
539 1.8 briggs if (ea->ea_moffs > 0) {
540 1.1 briggs #ifdef DEBUG
541 1.8 briggs printf("store_ea: more than one move to cpu reg\n");
542 1.1 briggs #endif
543 1.1 briggs return SIGILL;
544 1.1 briggs }
545 1.1 briggs dst = (char*)&frame->f_regs[ea->ea_regnum];
546 1.1 briggs /* The destination is an int. */
547 1.1 briggs if (len < 4) {
548 1.1 briggs dst += (4 - len);
549 1.8 briggs #ifdef DEBUG_FPE
550 1.8 briggs printf("store_ea: short/byte opr - dst addr adjusted\n");
551 1.8 briggs #endif
552 1.1 briggs }
553 1.8 briggs #ifdef DEBUG_FPE
554 1.8 briggs printf("store_ea: dst %p\n", dst);
555 1.8 briggs #endif
556 1.1 briggs bcopy(src, dst, len);
557 1.1 briggs } else /* One of MANY indirect forms... */ {
558 1.8 briggs #ifdef DEBUG_FPE
559 1.8 briggs printf("store_ea: using register %c%d\n",
560 1.8 briggs (ea->ea_regnum >= 8) ? 'a' : 'd', ea->ea_regnum & 7);
561 1.8 briggs #endif
562 1.1 briggs /* point to the register */
563 1.1 briggs reg = &(frame->f_regs[ea->ea_regnum]);
564 1.1 briggs
565 1.1 briggs /* do pre-decrement */
566 1.1 briggs if (ea->ea_flags & EA_PREDECR) {
567 1.8 briggs #ifdef DEBUG_FPE
568 1.8 briggs printf("store_ea: predecr mode - reg decremented\n");
569 1.8 briggs #endif
570 1.1 briggs *reg -= step;
571 1.8 briggs ea->ea_moffs = 0;
572 1.1 briggs }
573 1.1 briggs
574 1.1 briggs /* calculate the effective address */
575 1.1 briggs sig = calc_ea(ea, (char *)*reg, &dst);
576 1.1 briggs if (sig)
577 1.1 briggs return sig;
578 1.1 briggs
579 1.8 briggs #ifdef DEBUG_FPE
580 1.8 briggs printf("store_ea: dst addr=%p+%d\n", dst, ea->ea_moffs);
581 1.8 briggs #endif
582 1.8 briggs copyout(src, dst + ea->ea_moffs, len);
583 1.1 briggs
584 1.1 briggs /* do post-increment */
585 1.1 briggs if (ea->ea_flags & EA_POSTINCR) {
586 1.1 briggs *reg += step;
587 1.8 briggs ea->ea_moffs = 0;
588 1.8 briggs #ifdef DEBUG_FPE
589 1.8 briggs printf("store_ea: postinc mode - reg incremented\n");
590 1.8 briggs #endif
591 1.1 briggs } else {
592 1.8 briggs ea->ea_moffs += len;
593 1.1 briggs }
594 1.1 briggs }
595 1.1 briggs
596 1.1 briggs return 0;
597 1.1 briggs }
598 1.1 briggs
599 1.1 briggs /*
600 1.1 briggs * fetch_immed: fetch immediate operand
601 1.1 briggs */
602 1.1 briggs static int
603 1.1 briggs fetch_immed(frame, insn, dst)
604 1.1 briggs struct frame *frame;
605 1.1 briggs struct instruction *insn;
606 1.1 briggs int *dst;
607 1.1 briggs {
608 1.1 briggs int data, ext_bytes;
609 1.1 briggs
610 1.1 briggs ext_bytes = insn->is_datasize;
611 1.1 briggs
612 1.1 briggs if (0 < ext_bytes) {
613 1.8 briggs data = fusword((void *) (insn->is_pc + insn->is_advance));
614 1.1 briggs if (data < 0) {
615 1.1 briggs return SIGSEGV;
616 1.1 briggs }
617 1.1 briggs if (ext_bytes == 1) {
618 1.1 briggs /* sign-extend byte to long */
619 1.1 briggs data &= 0xff;
620 1.1 briggs if (data & 0x80) {
621 1.1 briggs data |= 0xffffff00;
622 1.1 briggs }
623 1.1 briggs } else if (ext_bytes == 2) {
624 1.1 briggs /* sign-extend word to long */
625 1.1 briggs data &= 0xffff;
626 1.1 briggs if (data & 0x8000) {
627 1.1 briggs data |= 0xffff0000;
628 1.1 briggs }
629 1.1 briggs }
630 1.1 briggs insn->is_advance += 2;
631 1.1 briggs dst[0] = data;
632 1.1 briggs }
633 1.1 briggs if (2 < ext_bytes) {
634 1.8 briggs data = fusword((void *) (insn->is_pc + insn->is_advance));
635 1.1 briggs if (data < 0) {
636 1.1 briggs return SIGSEGV;
637 1.1 briggs }
638 1.1 briggs insn->is_advance += 2;
639 1.1 briggs dst[0] <<= 16;
640 1.1 briggs dst[0] |= data;
641 1.1 briggs }
642 1.1 briggs if (4 < ext_bytes) {
643 1.8 briggs data = fusword((void *) (insn->is_pc + insn->is_advance));
644 1.1 briggs if (data < 0) {
645 1.1 briggs return SIGSEGV;
646 1.1 briggs }
647 1.1 briggs dst[1] = data << 16;
648 1.8 briggs data = fusword((void *) (insn->is_pc + insn->is_advance + 2));
649 1.1 briggs if (data < 0) {
650 1.1 briggs return SIGSEGV;
651 1.1 briggs }
652 1.1 briggs insn->is_advance += 4;
653 1.1 briggs dst[1] |= data;
654 1.1 briggs }
655 1.1 briggs if (8 < ext_bytes) {
656 1.8 briggs data = fusword((void *) (insn->is_pc + insn->is_advance));
657 1.1 briggs if (data < 0) {
658 1.1 briggs return SIGSEGV;
659 1.1 briggs }
660 1.1 briggs dst[2] = data << 16;
661 1.8 briggs data = fusword((void *) (insn->is_pc + insn->is_advance + 2));
662 1.1 briggs if (data < 0) {
663 1.1 briggs return SIGSEGV;
664 1.1 briggs }
665 1.1 briggs insn->is_advance += 4;
666 1.1 briggs dst[2] |= data;
667 1.1 briggs }
668 1.1 briggs
669 1.1 briggs return 0;
670 1.1 briggs }
671 1.1 briggs
672 1.1 briggs /*
673 1.1 briggs * fetch_disp: fetch displacement in full extention words
674 1.1 briggs */
675 1.1 briggs static int
676 1.1 briggs fetch_disp(frame, insn, size, res)
677 1.1 briggs struct frame *frame;
678 1.1 briggs struct instruction *insn;
679 1.1 briggs int size, *res;
680 1.1 briggs {
681 1.1 briggs int disp, word;
682 1.1 briggs
683 1.1 briggs if (size == 1) {
684 1.8 briggs word = fusword((void *) (insn->is_pc + insn->is_advance));
685 1.1 briggs if (word < 0) {
686 1.1 briggs return SIGSEGV;
687 1.1 briggs }
688 1.1 briggs disp = word & 0xffff;
689 1.1 briggs if (disp & 0x8000) {
690 1.1 briggs /* sign-extend */
691 1.1 briggs disp |= 0xffff0000;
692 1.1 briggs }
693 1.1 briggs insn->is_advance += 2;
694 1.1 briggs } else if (size == 2) {
695 1.8 briggs word = fusword((void *) (insn->is_pc + insn->is_advance));
696 1.1 briggs if (word < 0) {
697 1.1 briggs return SIGSEGV;
698 1.1 briggs }
699 1.1 briggs disp = word << 16;
700 1.8 briggs word = fusword((void *) (insn->is_pc + insn->is_advance + 2));
701 1.1 briggs if (word < 0) {
702 1.1 briggs return SIGSEGV;
703 1.1 briggs }
704 1.1 briggs disp |= (word & 0xffff);
705 1.1 briggs insn->is_advance += 4;
706 1.1 briggs } else {
707 1.1 briggs disp = 0;
708 1.1 briggs }
709 1.1 briggs *res = disp;
710 1.1 briggs return 0;
711 1.1 briggs }
712 1.1 briggs
713 1.1 briggs /*
714 1.1 briggs * Calculates an effective address for all address modes except for
715 1.1 briggs * register direct, absolute, and immediate modes. However, it does
716 1.1 briggs * not take care of predecrement/postincrement of register content.
717 1.1 briggs * Returns a signal value (0 == no error).
718 1.1 briggs */
719 1.1 briggs static int
720 1.1 briggs calc_ea(ea, ptr, eaddr)
721 1.1 briggs struct insn_ea *ea;
722 1.1 briggs char *ptr; /* base address (usually a register content) */
723 1.1 briggs char **eaddr; /* pointer to result pointer */
724 1.1 briggs {
725 1.4 briggs int data, word;
726 1.1 briggs
727 1.8 briggs #if DEBUG_FPE
728 1.8 briggs printf("calc_ea: reg indirect (reg) = %p\n", ptr);
729 1.8 briggs #endif
730 1.1 briggs
731 1.1 briggs if (ea->ea_flags & EA_OFFSET) {
732 1.1 briggs /* apply the signed offset */
733 1.8 briggs #if DEBUG_FPE
734 1.8 briggs printf("calc_ea: offset %d\n", ea->ea_offset);
735 1.8 briggs #endif
736 1.1 briggs ptr += ea->ea_offset;
737 1.1 briggs } else if (ea->ea_flags & EA_INDEXED) {
738 1.8 briggs #if DEBUG_FPE
739 1.8 briggs printf("calc_ea: indexed mode\n");
740 1.8 briggs #endif
741 1.1 briggs
742 1.1 briggs if (ea->ea_flags & EA_BASE_SUPPRSS) {
743 1.1 briggs /* base register is suppressed */
744 1.1 briggs ptr = (char *)ea->ea_basedisp;
745 1.1 briggs } else {
746 1.1 briggs ptr += ea->ea_basedisp;
747 1.1 briggs }
748 1.1 briggs
749 1.1 briggs if (ea->ea_flags & EA_MEM_INDIR) {
750 1.8 briggs #if DEBUG_FPE
751 1.8 briggs printf("calc_ea: mem indir mode: basedisp=%08x, outerdisp=%08x\n",
752 1.8 briggs ea->ea_basedisp, ea->ea_outerdisp);
753 1.8 briggs printf("calc_ea: addr fetched from %p\n", ptr);
754 1.8 briggs #endif
755 1.1 briggs /* memory indirect modes */
756 1.1 briggs word = fusword(ptr);
757 1.1 briggs if (word < 0) {
758 1.1 briggs return SIGSEGV;
759 1.1 briggs }
760 1.1 briggs word <<= 16;
761 1.1 briggs data = fusword(ptr + 2);
762 1.1 briggs if (data < 0) {
763 1.1 briggs return SIGSEGV;
764 1.1 briggs }
765 1.1 briggs word |= data;
766 1.8 briggs #if DEBUG_FPE
767 1.8 briggs printf("calc_ea: fetched ptr 0x%08x\n", word);
768 1.8 briggs #endif
769 1.1 briggs ptr = (char *)word + ea->ea_outerdisp;
770 1.1 briggs }
771 1.1 briggs }
772 1.1 briggs
773 1.1 briggs *eaddr = ptr;
774 1.1 briggs
775 1.1 briggs return 0;
776 1.1 briggs }
777