fpu_emulate.c revision 1.21
1 /* $NetBSD: fpu_emulate.c,v 1.21 1999/05/30 20:17:48 briggs Exp $ */ 2 3 /* 4 * Copyright (c) 1995 Gordon W. Ross 5 * some portion Copyright (c) 1995 Ken Nakata 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. The name of the author may not be used to endorse or promote products 17 * derived from this software without specific prior written permission. 18 * 4. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Gordon Ross 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * mc68881 emulator 36 * XXX - Just a start at it for now... 37 */ 38 39 #include <sys/types.h> 40 #include <sys/signal.h> 41 #include <sys/systm.h> 42 #include <machine/frame.h> 43 44 #if defined(DDB) && defined(DEBUG_FPE) 45 # include <m68k/db_machdep.h> 46 #endif 47 48 #include "fpu_emulate.h" 49 50 static int fpu_emul_fmovmcr __P((struct fpemu *fe, struct instruction *insn)); 51 static int fpu_emul_fmovm __P((struct fpemu *fe, struct instruction *insn)); 52 static int fpu_emul_arith __P((struct fpemu *fe, struct instruction *insn)); 53 static int fpu_emul_type1 __P((struct fpemu *fe, struct instruction *insn)); 54 static int fpu_emul_brcc __P((struct fpemu *fe, struct instruction *insn)); 55 static int test_cc __P((struct fpemu *fe, int pred)); 56 static struct fpn *fpu_cmp __P((struct fpemu *fe)); 57 58 #if DEBUG_FPE 59 # define DUMP_INSN(insn) \ 60 printf("fpu_emulate: insn={adv=%d,siz=%d,op=%04x,w1=%04x}\n", \ 61 (insn)->is_advance, (insn)->is_datasize, \ 62 (insn)->is_opcode, (insn)->is_word1) 63 #else 64 # define DUMP_INSN(insn) 65 #endif 66 67 /* 68 * Emulate a floating-point instruction. 69 * Return zero for success, else signal number. 70 * (Typically: zero, SIGFPE, SIGILL, SIGSEGV) 71 */ 72 int 73 fpu_emulate(frame, fpf) 74 struct frame *frame; 75 struct fpframe *fpf; 76 { 77 static struct instruction insn; 78 static struct fpemu fe; 79 #if 0 80 u_int savedpc = 0; /* XXX work around gcc -O lossage */ 81 #endif 82 int word, optype, sig; 83 84 85 /* initialize insn.is_datasize to tell it is *not* initialized */ 86 insn.is_datasize = -1; 87 88 fe.fe_frame = frame; 89 fe.fe_fpframe = fpf; 90 fe.fe_fpsr = fpf->fpf_fpsr; 91 fe.fe_fpcr = fpf->fpf_fpcr; 92 93 #if DEBUG_FPE 94 printf("ENTERING fpu_emulate: FPSR=%08x, FPCR=%08x\n", 95 fe.fe_fpsr, fe.fe_fpcr); 96 #endif 97 98 /* always set this (to avoid a warning) */ 99 insn.is_pc = frame->f_pc; 100 insn.is_nextpc = 0; 101 if (frame->f_format == 4) { 102 /* 103 * A format 4 is generated by the 68{EC,LC}040. The PC is 104 * already set to the instruction following the faulting 105 * instruction. We need to calculate that, anyway. The 106 * fslw is the PC of the faulted instruction, which is what 107 * we expect to be in f_pc. 108 * 109 * XXX - This is a hack; it assumes we at least know the 110 * sizes of all instructions we run across. This may not 111 * be true, so we save the PC in order to restore it later. 112 */ 113 insn.is_pc = frame->f_fmt4.f_fslw; 114 insn.is_nextpc = frame->f_pc; 115 } 116 117 word = fusword((void *) (insn.is_pc)); 118 if (word < 0) { 119 #ifdef DEBUG 120 printf("fpu_emulate: fault reading opcode\n"); 121 #endif 122 return SIGSEGV; 123 } 124 125 if ((word & 0xf000) != 0xf000) { 126 #ifdef DEBUG 127 printf("fpu_emulate: not coproc. insn.: opcode=0x%x\n", word); 128 #endif 129 return SIGILL; 130 } 131 132 if ((word & 0x0E00) != 0x0200) { 133 #ifdef DEBUG 134 printf("fpu_emulate: bad coproc. id: opcode=0x%x\n", word); 135 #endif 136 return SIGILL; 137 } 138 139 insn.is_opcode = word; 140 optype = (word & 0x01C0); 141 142 word = fusword((void *) (insn.is_pc + 2)); 143 if (word < 0) { 144 #ifdef DEBUG 145 printf("fpu_emulate: fault reading word1\n"); 146 #endif 147 return SIGSEGV; 148 } 149 insn.is_word1 = word; 150 /* all FPU instructions are at least 4-byte long */ 151 insn.is_advance = 4; 152 153 DUMP_INSN(&insn); 154 155 /* 156 * Which family (or type) of opcode is it? 157 * Tests ordered by likelihood (hopefully). 158 * Certainly, type 0 is the most common. 159 */ 160 if (optype == 0x0000) { 161 /* type=0: generic */ 162 if ((word & 0xc000) == 0xc000) { 163 #if DEBUG_FPE 164 printf("fpu_emulate: fmovm FPr\n"); 165 #endif 166 sig = fpu_emul_fmovm(&fe, &insn); 167 } else if ((word & 0xc000) == 0x8000) { 168 #if DEBUG_FPE 169 printf("fpu_emulate: fmovm FPcr\n"); 170 #endif 171 sig = fpu_emul_fmovmcr(&fe, &insn); 172 } else if ((word & 0xe000) == 0x6000) { 173 /* fstore = fmove FPn,mem */ 174 #if DEBUG_FPE 175 printf("fpu_emulate: fmove to mem\n"); 176 #endif 177 sig = fpu_emul_fstore(&fe, &insn); 178 } else if ((word & 0xfc00) == 0x5c00) { 179 /* fmovecr */ 180 #if DEBUG_FPE 181 printf("fpu_emulate: fmovecr\n"); 182 #endif 183 sig = fpu_emul_fmovecr(&fe, &insn); 184 } else if ((word & 0xa07f) == 0x26) { 185 /* fscale */ 186 #if DEBUG_FPE 187 printf("fpu_emulate: fscale\n"); 188 #endif 189 sig = fpu_emul_fscale(&fe, &insn); 190 } else { 191 #if DEBUG_FPE 192 printf("fpu_emulate: other type0\n"); 193 #endif 194 /* all other type0 insns are arithmetic */ 195 sig = fpu_emul_arith(&fe, &insn); 196 } 197 if (sig == 0) { 198 #if DEBUG_FPE 199 printf("fpu_emulate: type 0 returned 0\n"); 200 #endif 201 sig = fpu_upd_excp(&fe); 202 } 203 } else if (optype == 0x0080 || optype == 0x00C0) { 204 /* type=2 or 3: fbcc, short or long disp. */ 205 #if DEBUG_FPE 206 printf("fpu_emulate: fbcc %s\n", 207 (optype & 0x40) ? "long" : "short"); 208 #endif 209 sig = fpu_emul_brcc(&fe, &insn); 210 } else if (optype == 0x0040) { 211 /* type=1: fdbcc, fscc, ftrapcc */ 212 #if DEBUG_FPE 213 printf("fpu_emulate: type1\n"); 214 #endif 215 sig = fpu_emul_type1(&fe, &insn); 216 } else { 217 /* type=4: fsave (privileged) */ 218 /* type=5: frestore (privileged) */ 219 /* type=6: reserved */ 220 /* type=7: reserved */ 221 #ifdef DEBUG 222 printf("fpu_emulate: bad opcode type: opcode=0x%x\n", insn.is_opcode); 223 #endif 224 sig = SIGILL; 225 } 226 227 DUMP_INSN(&insn); 228 229 /* 230 * XXX it is not clear to me, if we should progress the PC always, 231 * for SIGFPE || 0, or only for 0; however, without SIGFPE, we 232 * don't pass the signalling regression tests. -is 233 */ 234 if ((sig == 0) || (sig == SIGFPE)) 235 frame->f_pc += insn.is_advance; 236 #if defined(DDB) && defined(DEBUG) 237 else { 238 printf("fpu_emulate: sig=%d, opcode=%x, word1=%x\n", 239 sig, insn.is_opcode, insn.is_word1); 240 kdb_trap(-1, (db_regs_t *)&frame); 241 } 242 #endif 243 if (frame->f_format == 4) 244 /* XXX Restore PC -- 68{EC,LC}040 only */ 245 frame->f_pc = insn.is_nextpc; 246 247 #if DEBUG_FPE 248 printf("EXITING fpu_emulate: w/FPSR=%08x, FPCR=%08x\n", 249 fe.fe_fpsr, fe.fe_fpcr); 250 #endif 251 252 return (sig); 253 } 254 255 /* update accrued exception bits and see if there's an FP exception */ 256 int 257 fpu_upd_excp(fe) 258 struct fpemu *fe; 259 { 260 u_int fpsr; 261 u_int fpcr; 262 263 fpsr = fe->fe_fpsr; 264 fpcr = fe->fe_fpcr; 265 /* update fpsr accrued exception bits; each insn doesn't have to 266 update this */ 267 if (fpsr & (FPSR_BSUN | FPSR_SNAN | FPSR_OPERR)) { 268 fpsr |= FPSR_AIOP; 269 } 270 if (fpsr & FPSR_OVFL) { 271 fpsr |= FPSR_AOVFL; 272 } 273 if ((fpsr & FPSR_UNFL) && (fpsr & FPSR_INEX2)) { 274 fpsr |= FPSR_AUNFL; 275 } 276 if (fpsr & FPSR_DZ) { 277 fpsr |= FPSR_ADZ; 278 } 279 if (fpsr & (FPSR_INEX1 | FPSR_INEX2 | FPSR_OVFL)) { 280 fpsr |= FPSR_AINEX; 281 } 282 283 fe->fe_fpframe->fpf_fpsr = fe->fe_fpsr = fpsr; 284 285 return (fpsr & fpcr & FPSR_EXCP) ? SIGFPE : 0; 286 } 287 288 /* update fpsr according to fp (= result of an fp op) */ 289 u_int 290 fpu_upd_fpsr(fe, fp) 291 struct fpemu *fe; 292 struct fpn *fp; 293 { 294 u_int fpsr; 295 296 #if DEBUG_FPE 297 printf("fpu_upd_fpsr: previous fpsr=%08x\n", fe->fe_fpsr); 298 #endif 299 /* clear all condition code */ 300 fpsr = fe->fe_fpsr & ~FPSR_CCB; 301 302 #if DEBUG_FPE 303 printf("fpu_upd_fpsr: result is a "); 304 #endif 305 if (fp->fp_sign) { 306 #if DEBUG_FPE 307 printf("negative "); 308 #endif 309 fpsr |= FPSR_NEG; 310 #if DEBUG_FPE 311 } else { 312 printf("positive "); 313 #endif 314 } 315 316 switch (fp->fp_class) { 317 case FPC_SNAN: 318 #if DEBUG_FPE 319 printf("signaling NAN\n"); 320 #endif 321 fpsr |= (FPSR_NAN | FPSR_SNAN); 322 break; 323 case FPC_QNAN: 324 #if DEBUG_FPE 325 printf("quiet NAN\n"); 326 #endif 327 fpsr |= FPSR_NAN; 328 break; 329 case FPC_ZERO: 330 #if DEBUG_FPE 331 printf("Zero\n"); 332 #endif 333 fpsr |= FPSR_ZERO; 334 break; 335 case FPC_INF: 336 #if DEBUG_FPE 337 printf("Inf\n"); 338 #endif 339 fpsr |= FPSR_INF; 340 break; 341 default: 342 #if DEBUG_FPE 343 printf("Number\n"); 344 #endif 345 /* anything else is treated as if it is a number */ 346 break; 347 } 348 349 fe->fe_fpsr = fe->fe_fpframe->fpf_fpsr = fpsr; 350 351 #if DEBUG_FPE 352 printf("fpu_upd_fpsr: new fpsr=%08x\n", fe->fe_fpframe->fpf_fpsr); 353 #endif 354 355 return fpsr; 356 } 357 358 static int 359 fpu_emul_fmovmcr(fe, insn) 360 struct fpemu *fe; 361 struct instruction *insn; 362 { 363 struct frame *frame = fe->fe_frame; 364 struct fpframe *fpf = fe->fe_fpframe; 365 int sig; 366 int reglist; 367 int fpu_to_mem; 368 369 /* move to/from control registers */ 370 reglist = (insn->is_word1 & 0x1c00) >> 10; 371 /* Bit 13 selects direction (FPU to/from Mem) */ 372 fpu_to_mem = insn->is_word1 & 0x2000; 373 374 insn->is_datasize = 4; 375 insn->is_advance = 4; 376 sig = fpu_decode_ea(frame, insn, &insn->is_ea, insn->is_opcode); 377 if (sig) { return sig; } 378 379 if (reglist != 1 && reglist != 2 && reglist != 4 && 380 (insn->is_ea.ea_flags & EA_DIRECT)) { 381 /* attempted to copy more than one FPcr to CPU regs */ 382 #ifdef DEBUG 383 printf("fpu_emul_fmovmcr: tried to copy too many FPcr\n"); 384 #endif 385 return SIGILL; 386 } 387 388 if (reglist & 4) { 389 /* fpcr */ 390 if ((insn->is_ea.ea_flags & EA_DIRECT) && 391 insn->is_ea.ea_regnum >= 8 /* address reg */) { 392 /* attempted to copy FPCR to An */ 393 #ifdef DEBUG 394 printf("fpu_emul_fmovmcr: tried to copy FPCR from/to A%d\n", 395 insn->is_ea.ea_regnum & 7); 396 #endif 397 return SIGILL; 398 } 399 if (fpu_to_mem) { 400 sig = fpu_store_ea(frame, insn, &insn->is_ea, 401 (char *)&fpf->fpf_fpcr); 402 } else { 403 sig = fpu_load_ea(frame, insn, &insn->is_ea, 404 (char *)&fpf->fpf_fpcr); 405 } 406 } 407 if (sig) { return sig; } 408 409 if (reglist & 2) { 410 /* fpsr */ 411 if ((insn->is_ea.ea_flags & EA_DIRECT) && 412 insn->is_ea.ea_regnum >= 8 /* address reg */) { 413 /* attempted to copy FPSR to An */ 414 #ifdef DEBUG 415 printf("fpu_emul_fmovmcr: tried to copy FPSR from/to A%d\n", 416 insn->is_ea.ea_regnum & 7); 417 #endif 418 return SIGILL; 419 } 420 if (fpu_to_mem) { 421 sig = fpu_store_ea(frame, insn, &insn->is_ea, 422 (char *)&fpf->fpf_fpsr); 423 } else { 424 sig = fpu_load_ea(frame, insn, &insn->is_ea, 425 (char *)&fpf->fpf_fpsr); 426 } 427 } 428 if (sig) { return sig; } 429 430 if (reglist & 1) { 431 /* fpiar - can be moved to/from An */ 432 if (fpu_to_mem) { 433 sig = fpu_store_ea(frame, insn, &insn->is_ea, 434 (char *)&fpf->fpf_fpiar); 435 } else { 436 sig = fpu_load_ea(frame, insn, &insn->is_ea, 437 (char *)&fpf->fpf_fpiar); 438 } 439 } 440 return sig; 441 } 442 443 /* 444 * type 0: fmovem 445 * Separated out of fpu_emul_type0 for efficiency. 446 * In this function, we know: 447 * (opcode & 0x01C0) == 0 448 * (word1 & 0x8000) == 0x8000 449 * 450 * No conversion or rounding is done by this instruction, 451 * and the FPSR is not affected. 452 */ 453 static int 454 fpu_emul_fmovm(fe, insn) 455 struct fpemu *fe; 456 struct instruction *insn; 457 { 458 struct frame *frame = fe->fe_frame; 459 struct fpframe *fpf = fe->fe_fpframe; 460 int word1, sig; 461 int reglist, regmask, regnum; 462 int fpu_to_mem, order; 463 int w1_post_incr; 464 int *fpregs; 465 466 insn->is_advance = 4; 467 insn->is_datasize = 12; 468 word1 = insn->is_word1; 469 470 /* Bit 13 selects direction (FPU to/from Mem) */ 471 fpu_to_mem = word1 & 0x2000; 472 473 /* 474 * Bits 12,11 select register list mode: 475 * 0,0: Static reg list, pre-decr. 476 * 0,1: Dynamic reg list, pre-decr. 477 * 1,0: Static reg list, post-incr. 478 * 1,1: Dynamic reg list, post-incr 479 */ 480 w1_post_incr = word1 & 0x1000; 481 if (word1 & 0x0800) { 482 /* dynamic reg list */ 483 reglist = frame->f_regs[(word1 & 0x70) >> 4]; 484 } else { 485 reglist = word1; 486 } 487 reglist &= 0xFF; 488 489 /* Get effective address. (modreg=opcode&077) */ 490 sig = fpu_decode_ea(frame, insn, &insn->is_ea, insn->is_opcode); 491 if (sig) { return sig; } 492 493 /* Get address of soft coprocessor regs. */ 494 fpregs = &fpf->fpf_regs[0]; 495 496 if (insn->is_ea.ea_flags & EA_PREDECR) { 497 regnum = 7; 498 order = -1; 499 } else { 500 regnum = 0; 501 order = 1; 502 } 503 504 regmask = 0x80; 505 while ((0 <= regnum) && (regnum < 8)) { 506 if (regmask & reglist) { 507 if (fpu_to_mem) { 508 sig = fpu_store_ea(frame, insn, &insn->is_ea, 509 (char*)&fpregs[regnum * 3]); 510 #if DEBUG_FPE 511 printf("fpu_emul_fmovm: FP%d (%08x,%08x,%08x) saved\n", 512 regnum, fpregs[regnum * 3], fpregs[regnum * 3 + 1], 513 fpregs[regnum * 3 + 2]); 514 #endif 515 } else { /* mem to fpu */ 516 sig = fpu_load_ea(frame, insn, &insn->is_ea, 517 (char*)&fpregs[regnum * 3]); 518 #if DEBUG_FPE 519 printf("fpu_emul_fmovm: FP%d (%08x,%08x,%08x) loaded\n", 520 regnum, fpregs[regnum * 3], fpregs[regnum * 3 + 1], 521 fpregs[regnum * 3 + 2]); 522 #endif 523 } 524 if (sig) { break; } 525 } 526 regnum += order; 527 regmask >>= 1; 528 } 529 530 return sig; 531 } 532 533 static struct fpn * 534 fpu_cmp(fe) 535 struct fpemu *fe; 536 { 537 struct fpn *x = &fe->fe_f1, *y = &fe->fe_f2; 538 539 /* take care of special cases */ 540 if (x->fp_class < 0 || y->fp_class < 0) { 541 /* if either of two is a SNAN, result is SNAN */ 542 x->fp_class = (y->fp_class < x->fp_class) ? y->fp_class : x->fp_class; 543 } else if (x->fp_class == FPC_INF) { 544 if (y->fp_class == FPC_INF) { 545 /* both infinities */ 546 if (x->fp_sign == y->fp_sign) { 547 x->fp_class = FPC_ZERO; /* return a signed zero */ 548 } else { 549 x->fp_class = FPC_NUM; /* return a faked number w/x's sign */ 550 x->fp_exp = 16383; 551 x->fp_mant[0] = FP_1; 552 } 553 } else { 554 /* y is a number */ 555 x->fp_class = FPC_NUM; /* return a forged number w/x's sign */ 556 x->fp_exp = 16383; 557 x->fp_mant[0] = FP_1; 558 } 559 } else if (y->fp_class == FPC_INF) { 560 /* x is a Num but y is an Inf */ 561 /* return a forged number w/y's sign inverted */ 562 x->fp_class = FPC_NUM; 563 x->fp_sign = !y->fp_sign; 564 x->fp_exp = 16383; 565 x->fp_mant[0] = FP_1; 566 } else { 567 /* x and y are both numbers or zeros, or pair of a number and a zero */ 568 y->fp_sign = !y->fp_sign; 569 x = fpu_add(fe); /* (x - y) */ 570 /* 571 * FCMP does not set Inf bit in CC, so return a forged number 572 * (value doesn't matter) if Inf is the result of fsub. 573 */ 574 if (x->fp_class == FPC_INF) { 575 x->fp_class = FPC_NUM; 576 x->fp_exp = 16383; 577 x->fp_mant[0] = FP_1; 578 } 579 } 580 return x; 581 } 582 583 /* 584 * arithmetic oprations 585 */ 586 static int 587 fpu_emul_arith(fe, insn) 588 struct fpemu *fe; 589 struct instruction *insn; 590 { 591 struct frame *frame = fe->fe_frame; 592 u_int *fpregs = &(fe->fe_fpframe->fpf_regs[0]); 593 struct fpn *res; 594 int word1, sig = 0; 595 int regnum, format; 596 int discard_result = 0; 597 u_int buf[3]; 598 #if DEBUG_FPE 599 int flags; 600 char regname; 601 #endif 602 603 fe->fe_fpsr &= ~FPSR_EXCP; 604 605 DUMP_INSN(insn); 606 607 #if DEBUG_FPE 608 printf("fpu_emul_arith: FPSR = %08x, FPCR = %08x\n", 609 fe->fe_fpsr, fe->fe_fpcr); 610 #endif 611 612 word1 = insn->is_word1; 613 format = (word1 >> 10) & 7; 614 regnum = (word1 >> 7) & 7; 615 616 /* fetch a source operand : may not be used */ 617 #if DEBUG_FPE 618 printf("fpu_emul_arith: dst/src FP%d=%08x,%08x,%08x\n", 619 regnum, fpregs[regnum*3], fpregs[regnum*3+1], 620 fpregs[regnum*3+2]); 621 #endif 622 623 fpu_explode(fe, &fe->fe_f1, FTYPE_EXT, &fpregs[regnum * 3]); 624 625 DUMP_INSN(insn); 626 627 /* get the other operand which is always the source */ 628 if ((word1 & 0x4000) == 0) { 629 #if DEBUG_FPE 630 printf("fpu_emul_arith: FP%d op FP%d => FP%d\n", 631 format, regnum, regnum); 632 printf("fpu_emul_arith: src opr FP%d=%08x,%08x,%08x\n", 633 format, fpregs[format*3], fpregs[format*3+1], 634 fpregs[format*3+2]); 635 #endif 636 fpu_explode(fe, &fe->fe_f2, FTYPE_EXT, &fpregs[format * 3]); 637 } else { 638 /* the operand is in memory */ 639 if (format == FTYPE_DBL) { 640 insn->is_datasize = 8; 641 } else if (format == FTYPE_SNG || format == FTYPE_LNG) { 642 insn->is_datasize = 4; 643 } else if (format == FTYPE_WRD) { 644 insn->is_datasize = 2; 645 } else if (format == FTYPE_BYT) { 646 insn->is_datasize = 1; 647 } else if (format == FTYPE_EXT) { 648 insn->is_datasize = 12; 649 } else { 650 /* invalid or unsupported operand format */ 651 sig = SIGFPE; 652 return sig; 653 } 654 655 /* Get effective address. (modreg=opcode&077) */ 656 sig = fpu_decode_ea(frame, insn, &insn->is_ea, insn->is_opcode); 657 if (sig) { 658 #if DEBUG_FPE 659 printf("fpu_emul_arith: error in fpu_decode_ea\n"); 660 #endif 661 return sig; 662 } 663 664 DUMP_INSN(insn); 665 666 #if DEBUG_FPE 667 printf("fpu_emul_arith: addr mode = "); 668 flags = insn->is_ea.ea_flags; 669 regname = (insn->is_ea.ea_regnum & 8) ? 'a' : 'd'; 670 671 if (flags & EA_DIRECT) { 672 printf("%c%d\n", 673 regname, insn->is_ea.ea_regnum & 7); 674 } else if (flags & EA_PC_REL) { 675 if (flags & EA_OFFSET) { 676 printf("pc@(%d)\n", insn->is_ea.ea_offset); 677 } else if (flags & EA_INDEXED) { 678 printf("pc@(...)\n"); 679 } 680 } else if (flags & EA_PREDECR) { 681 printf("%c%d@-\n", 682 regname, insn->is_ea.ea_regnum & 7); 683 } else if (flags & EA_POSTINCR) { 684 printf("%c%d@+\n", regname, insn->is_ea.ea_regnum & 7); 685 } else if (flags & EA_OFFSET) { 686 printf("%c%d@(%d)\n", regname, insn->is_ea.ea_regnum & 7, 687 insn->is_ea.ea_offset); 688 } else if (flags & EA_INDEXED) { 689 printf("%c%d@(...)\n", regname, insn->is_ea.ea_regnum & 7); 690 } else if (flags & EA_ABS) { 691 printf("0x%08x\n", insn->is_ea.ea_absaddr); 692 } else if (flags & EA_IMMED) { 693 694 printf("#0x%08x,%08x,%08x\n", insn->is_ea.ea_immed[0], 695 insn->is_ea.ea_immed[1], insn->is_ea.ea_immed[2]); 696 } else { 697 printf("%c%d@\n", regname, insn->is_ea.ea_regnum & 7); 698 } 699 #endif /* DEBUG_FPE */ 700 701 fpu_load_ea(frame, insn, &insn->is_ea, (char*)buf); 702 if (format == FTYPE_WRD) { 703 /* sign-extend */ 704 buf[0] &= 0xffff; 705 if (buf[0] & 0x8000) { 706 buf[0] |= 0xffff0000; 707 } 708 format = FTYPE_LNG; 709 } else if (format == FTYPE_BYT) { 710 /* sign-extend */ 711 buf[0] &= 0xff; 712 if (buf[0] & 0x80) { 713 buf[0] |= 0xffffff00; 714 } 715 format = FTYPE_LNG; 716 } 717 #if DEBUG_FPE 718 printf("fpu_emul_arith: src = %08x %08x %08x, siz = %d\n", 719 buf[0], buf[1], buf[2], insn->is_datasize); 720 #endif 721 fpu_explode(fe, &fe->fe_f2, format, buf); 722 } 723 724 DUMP_INSN(insn); 725 726 /* An arithmetic instruction emulate function has a prototype of 727 * struct fpn *fpu_op(struct fpemu *); 728 729 * 1) If the instruction is monadic, then fpu_op() must use 730 * fe->fe_f2 as its operand, and return a pointer to the 731 * result. 732 733 * 2) If the instruction is diadic, then fpu_op() must use 734 * fe->fe_f1 and fe->fe_f2 as its two operands, and return a 735 * pointer to the result. 736 737 */ 738 res = 0; 739 switch (word1 & 0x3f) { 740 case 0x00: /* fmove */ 741 res = &fe->fe_f2; 742 break; 743 744 case 0x01: /* fint */ 745 res = fpu_int(fe); 746 break; 747 748 case 0x02: /* fsinh */ 749 res = fpu_sinh(fe); 750 break; 751 752 case 0x03: /* fintrz */ 753 res = fpu_intrz(fe); 754 break; 755 756 case 0x04: /* fsqrt */ 757 res = fpu_sqrt(fe); 758 break; 759 760 case 0x06: /* flognp1 */ 761 res = fpu_lognp1(fe); 762 break; 763 764 case 0x08: /* fetoxm1 */ 765 res = fpu_etoxm1(fe); 766 break; 767 768 case 0x09: /* ftanh */ 769 res = fpu_tanh(fe); 770 break; 771 772 case 0x0A: /* fatan */ 773 res = fpu_atan(fe); 774 break; 775 776 case 0x0C: /* fasin */ 777 res = fpu_asin(fe); 778 break; 779 780 case 0x0D: /* fatanh */ 781 res = fpu_atanh(fe); 782 break; 783 784 case 0x0E: /* fsin */ 785 res = fpu_sin(fe); 786 break; 787 788 case 0x0F: /* ftan */ 789 res = fpu_tan(fe); 790 break; 791 792 case 0x10: /* fetox */ 793 res = fpu_etox(fe); 794 break; 795 796 case 0x11: /* ftwotox */ 797 res = fpu_twotox(fe); 798 break; 799 800 case 0x12: /* ftentox */ 801 res = fpu_tentox(fe); 802 break; 803 804 case 0x14: /* flogn */ 805 res = fpu_logn(fe); 806 break; 807 808 case 0x15: /* flog10 */ 809 res = fpu_log10(fe); 810 break; 811 812 case 0x16: /* flog2 */ 813 res = fpu_log2(fe); 814 break; 815 816 case 0x18: /* fabs */ 817 fe->fe_f2.fp_sign = 0; 818 res = &fe->fe_f2; 819 break; 820 821 case 0x19: /* fcosh */ 822 res = fpu_cosh(fe); 823 break; 824 825 case 0x1A: /* fneg */ 826 fe->fe_f2.fp_sign = !fe->fe_f2.fp_sign; 827 res = &fe->fe_f2; 828 break; 829 830 case 0x1C: /* facos */ 831 res = fpu_acos(fe); 832 break; 833 834 case 0x1D: /* fcos */ 835 res = fpu_cos(fe); 836 break; 837 838 case 0x1E: /* fgetexp */ 839 res = fpu_getexp(fe); 840 break; 841 842 case 0x1F: /* fgetman */ 843 res = fpu_getman(fe); 844 break; 845 846 case 0x20: /* fdiv */ 847 case 0x24: /* fsgldiv: cheating - better than nothing */ 848 res = fpu_div(fe); 849 break; 850 851 case 0x21: /* fmod */ 852 res = fpu_mod(fe); 853 break; 854 855 case 0x28: /* fsub */ 856 fe->fe_f2.fp_sign = !fe->fe_f2.fp_sign; /* f2 = -f2 */ 857 case 0x22: /* fadd */ 858 res = fpu_add(fe); 859 break; 860 861 case 0x23: /* fmul */ 862 case 0x27: /* fsglmul: cheating - better than nothing */ 863 res = fpu_mul(fe); 864 break; 865 866 case 0x25: /* frem */ 867 res = fpu_rem(fe); 868 break; 869 870 case 0x26: 871 /* fscale is handled by a separate function */ 872 break; 873 874 case 0x30: 875 case 0x31: 876 case 0x32: 877 case 0x33: 878 case 0x34: 879 case 0x35: 880 case 0x36: 881 case 0x37: /* fsincos */ 882 res = fpu_sincos(fe, word1 & 7); 883 break; 884 885 case 0x38: /* fcmp */ 886 res = fpu_cmp(fe); 887 discard_result = 1; 888 break; 889 890 case 0x3A: /* ftst */ 891 res = &fe->fe_f2; 892 discard_result = 1; 893 break; 894 895 default: 896 #ifdef DEBUG 897 printf("fpu_emul_arith: bad opcode=0x%x, word1=0x%x\n", 898 insn->is_opcode, insn->is_word1); 899 #endif 900 sig = SIGILL; 901 } /* switch (word1 & 0x3f) */ 902 903 if (!discard_result && sig == 0) { 904 fpu_implode(fe, res, FTYPE_EXT, &fpregs[regnum * 3]); 905 #if DEBUG_FPE 906 printf("fpu_emul_arith: %08x,%08x,%08x stored in FP%d\n", 907 fpregs[regnum*3], fpregs[regnum*3+1], 908 fpregs[regnum*3+2], regnum); 909 } else if (sig == 0) { 910 static char *class_name[] = { "SNAN", "QNAN", "ZERO", "NUM", "INF" }; 911 printf("fpu_emul_arith: result(%s,%c,%d,%08x,%08x,%08x) discarded\n", 912 class_name[res->fp_class + 2], 913 res->fp_sign ? '-' : '+', res->fp_exp, 914 res->fp_mant[0], res->fp_mant[1], 915 res->fp_mant[2]); 916 } else { 917 printf("fpu_emul_arith: received signal %d\n", sig); 918 #endif 919 } 920 921 /* update fpsr according to the result of operation */ 922 fpu_upd_fpsr(fe, res); 923 924 #if DEBUG_FPE 925 printf("fpu_emul_arith: FPSR = %08x, FPCR = %08x\n", 926 fe->fe_fpsr, fe->fe_fpcr); 927 #endif 928 929 DUMP_INSN(insn); 930 931 return sig; 932 } 933 934 /* test condition code according to the predicate in the opcode. 935 * returns -1 when the predicate evaluates to true, 0 when false. 936 * signal numbers are returned when an error is detected. 937 */ 938 static int 939 test_cc(fe, pred) 940 struct fpemu *fe; 941 int pred; 942 { 943 int result, sig_bsun, invert; 944 int fpsr; 945 946 fpsr = fe->fe_fpsr; 947 invert = 0; 948 fpsr &= ~FPSR_EXCP; /* clear all exceptions */ 949 #if DEBUG_FPE 950 printf("test_cc: fpsr=0x%08x\n", fpsr); 951 #endif 952 pred &= 0x3f; /* lowest 6 bits */ 953 954 #if DEBUG_FPE 955 printf("test_cc: "); 956 #endif 957 958 if (pred >= 0x20) { 959 return SIGILL; 960 } else if (pred & 0x10) { 961 /* IEEE nonaware tests */ 962 sig_bsun = 1; 963 pred &= 0x0f; /* lower 4 bits */ 964 } else { 965 /* IEEE aware tests */ 966 #if DEBUG_FPE 967 printf("IEEE "); 968 #endif 969 sig_bsun = 0; 970 } 971 972 if (pred & 0x08) { 973 #if DEBUG_FPE 974 printf("Not "); 975 #endif 976 /* predicate is "NOT ..." */ 977 pred ^= 0xf; /* invert */ 978 invert = -1; 979 } 980 switch (pred) { 981 case 0: /* (Signaling) False */ 982 #if DEBUG_FPE 983 printf("False"); 984 #endif 985 result = 0; 986 break; 987 case 1: /* (Signaling) Equal */ 988 #if DEBUG_FPE 989 printf("Equal"); 990 #endif 991 result = -((fpsr & FPSR_ZERO) == FPSR_ZERO); 992 break; 993 case 2: /* Greater Than */ 994 #if DEBUG_FPE 995 printf("GT"); 996 #endif 997 result = -((fpsr & (FPSR_NAN|FPSR_ZERO|FPSR_NEG)) == 0); 998 break; 999 case 3: /* Greater or Equal */ 1000 #if DEBUG_FPE 1001 printf("GE"); 1002 #endif 1003 result = -((fpsr & FPSR_ZERO) || 1004 (fpsr & (FPSR_NAN|FPSR_NEG)) == 0); 1005 break; 1006 case 4: /* Less Than */ 1007 #if DEBUG_FPE 1008 printf("LT"); 1009 #endif 1010 result = -((fpsr & (FPSR_NAN|FPSR_ZERO|FPSR_NEG)) == FPSR_NEG); 1011 break; 1012 case 5: /* Less or Equal */ 1013 #if DEBUG_FPE 1014 printf("LE"); 1015 #endif 1016 result = -((fpsr & FPSR_ZERO) || 1017 ((fpsr & (FPSR_NAN|FPSR_NEG)) == FPSR_NEG)); 1018 break; 1019 case 6: /* Greater or Less than */ 1020 #if DEBUG_FPE 1021 printf("GLT"); 1022 #endif 1023 result = -((fpsr & (FPSR_NAN|FPSR_ZERO)) == 0); 1024 break; 1025 case 7: /* Greater, Less or Equal */ 1026 #if DEBUG_FPE 1027 printf("GLE"); 1028 #endif 1029 result = -((fpsr & FPSR_NAN) == 0); 1030 break; 1031 default: 1032 /* invalid predicate */ 1033 return SIGILL; 1034 } 1035 result ^= invert; /* if the predicate is "NOT ...", then 1036 invert the result */ 1037 #if DEBUG_FPE 1038 printf("=> %s (%d)\n", result ? "true" : "false", result); 1039 #endif 1040 /* if it's an IEEE unaware test and NAN is set, BSUN is set */ 1041 if (sig_bsun && (fpsr & FPSR_NAN)) { 1042 fpsr |= FPSR_BSUN; 1043 } 1044 1045 /* put fpsr back */ 1046 fe->fe_fpframe->fpf_fpsr = fe->fe_fpsr = fpsr; 1047 1048 return result; 1049 } 1050 1051 /* 1052 * type 1: fdbcc, fscc, ftrapcc 1053 * In this function, we know: 1054 * (opcode & 0x01C0) == 0x0040 1055 */ 1056 static int 1057 fpu_emul_type1(fe, insn) 1058 struct fpemu *fe; 1059 struct instruction *insn; 1060 { 1061 struct frame *frame = fe->fe_frame; 1062 int advance, sig, branch, displ; 1063 1064 branch = test_cc(fe, insn->is_word1); 1065 fe->fe_fpframe->fpf_fpsr = fe->fe_fpsr; 1066 1067 insn->is_advance = 4; 1068 sig = 0; 1069 1070 switch (insn->is_opcode & 070) { 1071 case 010: /* fdbcc */ 1072 if (branch == -1) { 1073 /* advance */ 1074 insn->is_advance = 6; 1075 } else if (!branch) { 1076 /* decrement Dn and if (Dn != -1) branch */ 1077 u_int16_t count = frame->f_regs[insn->is_opcode & 7]; 1078 1079 if (count-- != 0) { 1080 displ = fusword((void *) (insn->is_pc + insn->is_advance)); 1081 if (displ < 0) { 1082 #ifdef DEBUG 1083 printf("fpu_emul_type1: fault reading displacement\n"); 1084 #endif 1085 return SIGSEGV; 1086 } 1087 /* sign-extend the displacement */ 1088 displ &= 0xffff; 1089 if (displ & 0x8000) { 1090 displ |= 0xffff0000; 1091 } 1092 insn->is_advance += displ; 1093 } else { 1094 insn->is_advance = 6; 1095 } 1096 /* write it back */ 1097 frame->f_regs[insn->is_opcode & 7] &= 0xffff0000; 1098 frame->f_regs[insn->is_opcode & 7] |= (u_int32_t)count; 1099 } else { /* got a signal */ 1100 sig = SIGFPE; 1101 } 1102 break; 1103 1104 case 070: /* ftrapcc or fscc */ 1105 advance = 4; 1106 if ((insn->is_opcode & 07) >= 2) { 1107 switch (insn->is_opcode & 07) { 1108 case 3: /* long opr */ 1109 advance += 2; 1110 case 2: /* word opr */ 1111 advance += 2; 1112 case 4: /* no opr */ 1113 break; 1114 default: 1115 return SIGILL; 1116 break; 1117 } 1118 1119 if (branch == 0) { 1120 /* no trap */ 1121 insn->is_advance = advance; 1122 sig = 0; 1123 } else { 1124 /* trap */ 1125 sig = SIGFPE; 1126 } 1127 break; 1128 } /* if ((insn->is_opcode & 7) < 2), fall through to FScc */ 1129 1130 default: /* fscc */ 1131 insn->is_advance = 4; 1132 insn->is_datasize = 1; /* always byte */ 1133 sig = fpu_decode_ea(frame, insn, &insn->is_ea, insn->is_opcode); 1134 if (sig) { 1135 break; 1136 } 1137 if (branch == -1 || branch == 0) { 1138 /* set result */ 1139 sig = fpu_store_ea(frame, insn, &insn->is_ea, (char *)&branch); 1140 } else { 1141 /* got an exception */ 1142 sig = branch; 1143 } 1144 break; 1145 } 1146 return sig; 1147 } 1148 1149 /* 1150 * Type 2 or 3: fbcc (also fnop) 1151 * In this function, we know: 1152 * (opcode & 0x0180) == 0x0080 1153 */ 1154 static int 1155 fpu_emul_brcc(fe, insn) 1156 struct fpemu *fe; 1157 struct instruction *insn; 1158 { 1159 int displ, word2; 1160 int sig; 1161 1162 /* 1163 * Get branch displacement. 1164 */ 1165 insn->is_advance = 4; 1166 displ = insn->is_word1; 1167 1168 if (insn->is_opcode & 0x40) { 1169 word2 = fusword((void *) (insn->is_pc + insn->is_advance)); 1170 if (word2 < 0) { 1171 #ifdef DEBUG 1172 printf("fpu_emul_brcc: fault reading word2\n"); 1173 #endif 1174 return SIGSEGV; 1175 } 1176 displ <<= 16; 1177 displ |= word2; 1178 insn->is_advance += 2; 1179 } else /* displacement is word sized */ 1180 if (displ & 0x8000) 1181 displ |= 0xFFFF0000; 1182 1183 /* XXX: If CC, insn->is_pc += displ */ 1184 sig = test_cc(fe, insn->is_opcode); 1185 fe->fe_fpframe->fpf_fpsr = fe->fe_fpsr; 1186 1187 if (fe->fe_fpsr & fe->fe_fpcr & FPSR_EXCP) { 1188 return SIGFPE; /* caught an exception */ 1189 } 1190 if (sig == -1) { 1191 /* branch does take place; 2 is the offset to the 1st disp word */ 1192 insn->is_advance = displ + 2; 1193 insn->is_nextpc = insn->is_pc + insn->is_advance; 1194 } else if (sig) { 1195 return SIGILL; /* got a signal */ 1196 } 1197 #if DEBUG_FPE 1198 printf("fpu_emul_brcc: %s insn @ %x (%x+%x) (disp=%x)\n", 1199 (sig == -1) ? "BRANCH to" : "NEXT", 1200 insn->is_pc + insn->is_advance, insn->is_pc, insn->is_advance, 1201 displ); 1202 #endif 1203 return 0; 1204 } 1205
Indexes created Mon Sep 29 21:09:56 GMT 2025