fpu_emulate.h revision 1.10
1 /* $NetBSD: fpu_emulate.h,v 1.10 2003/09/22 14:18:35 cl Exp $ */ 2 3 /* 4 * Copyright (c) 1995 Gordon Ross 5 * Copyright (c) 1995 Ken Nakata 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. The name of the author may not be used to endorse or promote products 17 * derived from this software without specific prior written permission. 18 * 4. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Gordon Ross 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #ifndef _FPU_EMULATE_H_ 35 #define _FPU_EMULATE_H_ 36 37 #include <sys/types.h> 38 #include <sys/signal.h> 39 #include <sys/signalvar.h> 40 #include <sys/siginfo.h> 41 42 /* 43 * Floating point emulator (tailored for SPARC/modified for m68k, but 44 * structurally machine-independent). 45 * 46 * Floating point numbers are carried around internally in an `expanded' 47 * or `unpacked' form consisting of: 48 * - sign 49 * - unbiased exponent 50 * - mantissa (`1.' + 80-bit fraction + guard + round) 51 * - sticky bit 52 * Any implied `1' bit is inserted, giving a 81-bit mantissa that is 53 * always nonzero. Additional low-order `guard' and `round' bits are 54 * scrunched in, making the entire mantissa 83 bits long. This is divided 55 * into three 32-bit words, with `spare' bits left over in the upper part 56 * of the top word (the high bits of fp_mant[0]). An internal `exploded' 57 * number is thus kept within the half-open interval [1.0,2.0) (but see 58 * the `number classes' below). This holds even for denormalized numbers: 59 * when we explode an external denorm, we normalize it, introducing low-order 60 * zero bits, so that the rest of the code always sees normalized values. 61 * 62 * Note that a number of our algorithms use the `spare' bits at the top. 63 * The most demanding algorithm---the one for sqrt---depends on two such 64 * bits, so that it can represent values up to (but not including) 8.0, 65 * and then it needs a carry on top of that, so that we need three `spares'. 66 * 67 * The sticky-word is 32 bits so that we can use `OR' operators to goosh 68 * whole words from the mantissa into it. 69 * 70 * All operations are done in this internal extended precision. According 71 * to Hennesey & Patterson, Appendix A, rounding can be repeated---that is, 72 * it is OK to do a+b in extended precision and then round the result to 73 * single precision---provided single, double, and extended precisions are 74 * `far enough apart' (they always are), but we will try to avoid any such 75 * extra work where possible. 76 */ 77 struct fpn { 78 int fp_class; /* see below */ 79 int fp_sign; /* 0 => positive, 1 => negative */ 80 int fp_exp; /* exponent (unbiased) */ 81 int fp_sticky; /* nonzero bits lost at right end */ 82 u_int fp_mant[3]; /* 83-bit mantissa */ 83 }; 84 85 #define FP_NMANT 83 /* total bits in mantissa (incl g,r) */ 86 #define FP_NG 2 /* number of low-order guard bits */ 87 #define FP_LG ((FP_NMANT - 1) & 31) /* log2(1.0) for fp_mant[0] */ 88 #define FP_QUIETBIT (1 << (FP_LG - 1)) /* Quiet bit in NaNs (0.5) */ 89 #define FP_1 (1 << FP_LG) /* 1.0 in fp_mant[0] */ 90 #define FP_2 (1 << (FP_LG + 1)) /* 2.0 in fp_mant[0] */ 91 92 #define CPYFPN(dst, src) \ 93 if ((dst) != (src)) { \ 94 (dst)->fp_class = (src)->fp_class; \ 95 (dst)->fp_sign = (src)->fp_sign; \ 96 (dst)->fp_exp = (src)->fp_exp; \ 97 (dst)->fp_sticky = (src)->fp_sticky; \ 98 (dst)->fp_mant[0] = (src)->fp_mant[0]; \ 99 (dst)->fp_mant[1] = (src)->fp_mant[1]; \ 100 (dst)->fp_mant[2] = (src)->fp_mant[2]; \ 101 } 102 103 /* 104 * Number classes. Since zero, Inf, and NaN cannot be represented using 105 * the above layout, we distinguish these from other numbers via a class. 106 */ 107 #define FPC_SNAN -2 /* signalling NaN (sign irrelevant) */ 108 #define FPC_QNAN -1 /* quiet NaN (sign irrelevant) */ 109 #define FPC_ZERO 0 /* zero (sign matters) */ 110 #define FPC_NUM 1 /* number (sign matters) */ 111 #define FPC_INF 2 /* infinity (sign matters) */ 112 113 #define ISNAN(fp) ((fp)->fp_class < 0) 114 #define ISZERO(fp) ((fp)->fp_class == 0) 115 #define ISINF(fp) ((fp)->fp_class == FPC_INF) 116 117 /* 118 * ORDER(x,y) `sorts' a pair of `fpn *'s so that the right operand (y) points 119 * to the `more significant' operand for our purposes. Appendix N says that 120 * the result of a computation involving two numbers are: 121 * 122 * If both are SNaN: operand 2, converted to Quiet 123 * If only one is SNaN: the SNaN operand, converted to Quiet 124 * If both are QNaN: operand 2 125 * If only one is QNaN: the QNaN operand 126 * 127 * In addition, in operations with an Inf operand, the result is usually 128 * Inf. The class numbers are carefully arranged so that if 129 * (unsigned)class(op1) > (unsigned)class(op2) 130 * then op1 is the one we want; otherwise op2 is the one we want. 131 */ 132 #define ORDER(x, y) { \ 133 if ((u_int)(x)->fp_class > (u_int)(y)->fp_class) \ 134 SWAP(x, y); \ 135 } 136 #define SWAP(x, y) { \ 137 register struct fpn *swap; \ 138 swap = (x), (x) = (y), (y) = swap; \ 139 } 140 141 /* 142 * Emulator state. 143 */ 144 struct fpemu { 145 struct frame *fe_frame; /* integer regs, etc */ 146 struct fpframe *fe_fpframe; /* FP registers, etc */ 147 u_int fe_fpsr; /* fpsr copy (modified during op) */ 148 u_int fe_fpcr; /* fpcr copy */ 149 struct fpn fe_f1; /* operand 1 */ 150 struct fpn fe_f2; /* operand 2, if required */ 151 struct fpn fe_f3; /* available storage for result */ 152 }; 153 154 /***************************************************************************** 155 * End of definitions derived from Sparc FPE 156 *****************************************************************************/ 157 158 /* 159 * Internal info about a decoded effective address. 160 */ 161 struct insn_ea { 162 int ea_regnum; 163 int ea_ext[3]; /* extension words if any */ 164 int ea_flags; /* flags == 0 means mode 2: An@ */ 165 #define EA_DIRECT 0x001 /* mode [01]: Dn or An */ 166 #define EA_PREDECR 0x002 /* mode 4: An@- */ 167 #define EA_POSTINCR 0x004 /* mode 3: An@+ */ 168 #define EA_OFFSET 0x008 /* mode 5 or (7,2): APC@(d16) */ 169 #define EA_INDEXED 0x010 /* mode 6 or (7,3): APC@(Xn:*:*,d8) etc */ 170 #define EA_ABS 0x020 /* mode (7,[01]): abs */ 171 #define EA_PC_REL 0x040 /* mode (7,[23]): PC@(d16) etc */ 172 #define EA_IMMED 0x080 /* mode (7,4): #immed */ 173 #define EA_MEM_INDIR 0x100 /* mode 6 or (7,3): APC@(Xn:*:*,*)@(*) etc */ 174 #define EA_BASE_SUPPRSS 0x200 /* mode 6 or (7,3): base register suppressed */ 175 #define EA_FRAME_EA 0x400 /* MC68LC040 only: precalculated EA from 176 format 4 stack frame */ 177 int ea_moffs; /* offset used for fmoveMulti */ 178 }; 179 180 #define ea_offset ea_ext[0] /* mode 5: offset word */ 181 #define ea_absaddr ea_ext[0] /* mode (7,[01]): absolute address */ 182 #define ea_immed ea_ext /* mode (7,4): immediate value */ 183 #define ea_basedisp ea_ext[0] /* mode 6: base displacement */ 184 #define ea_outerdisp ea_ext[1] /* mode 6: outer displacement */ 185 #define ea_idxreg ea_ext[2] /* mode 6: index register number */ 186 #define ea_fea ea_ext[0] /* MC68LC040 only: frame EA */ 187 188 struct instruction { 189 u_int is_pc; /* insn's address */ 190 u_int is_nextpc; /* next PC */ 191 int is_advance; /* length of instruction */ 192 int is_datasize; /* size of memory operand */ 193 int is_opcode; /* opcode word */ 194 int is_word1; /* second word */ 195 struct insn_ea is_ea; /* decoded effective address mode */ 196 }; 197 198 /* 199 * FP data types 200 */ 201 #define FTYPE_LNG 0 /* Long Word Integer */ 202 #define FTYPE_SNG 1 /* Single Prec */ 203 #define FTYPE_EXT 2 /* Extended Prec */ 204 #define FTYPE_BCD 3 /* Packed BCD */ 205 #define FTYPE_WRD 4 /* Word Integer */ 206 #define FTYPE_DBL 5 /* Double Prec */ 207 #define FTYPE_BYT 6 /* Byte Integer */ 208 209 /* 210 * MC68881/68882 FPcr bit definitions (should these go to <m68k/reg.h> 211 * or <m68k/fpu.h> or something?) 212 */ 213 214 /* fpsr */ 215 #define FPSR_CCB 0xff000000 216 # define FPSR_NEG 0x08000000 217 # define FPSR_ZERO 0x04000000 218 # define FPSR_INF 0x02000000 219 # define FPSR_NAN 0x01000000 220 #define FPSR_QTT 0x00ff0000 221 # define FPSR_QSG 0x00800000 222 # define FPSR_QUO 0x007f0000 223 #define FPSR_EXCP 0x0000ff00 224 # define FPSR_BSUN 0x00008000 225 # define FPSR_SNAN 0x00004000 226 # define FPSR_OPERR 0x00002000 227 # define FPSR_OVFL 0x00001000 228 # define FPSR_UNFL 0x00000800 229 # define FPSR_DZ 0x00000400 230 # define FPSR_INEX2 0x00000200 231 # define FPSR_INEX1 0x00000100 232 #define FPSR_AEX 0x000000ff 233 # define FPSR_AIOP 0x00000080 234 # define FPSR_AOVFL 0x00000040 235 # define FPSR_AUNFL 0x00000020 236 # define FPSR_ADZ 0x00000010 237 # define FPSR_AINEX 0x00000008 238 239 /* fpcr */ 240 #define FPCR_EXCP FPSR_EXCP 241 # define FPCR_BSUN FPSR_BSUN 242 # define FPCR_SNAN FPSR_SNAN 243 # define FPCR_OPERR FPSR_OPERR 244 # define FPCR_OVFL FPSR_OVFL 245 # define FPCR_UNFL FPSR_UNFL 246 # define FPCR_DZ FPSR_DZ 247 # define FPCR_INEX2 FPSR_INEX2 248 # define FPCR_INEX1 FPSR_INEX1 249 #define FPCR_MODE 0x000000ff 250 # define FPCR_PREC 0x000000c0 251 # define FPCR_EXTD 0x00000000 252 # define FPCR_SNGL 0x00000040 253 # define FPCR_DBL 0x00000080 254 # define FPCR_ROUND 0x00000030 255 # define FPCR_NEAR 0x00000000 256 # define FPCR_ZERO 0x00000010 257 # define FPCR_MINF 0x00000020 258 # define FPCR_PINF 0x00000030 259 260 /* 261 * Other functions. 262 */ 263 264 /* Build a new Quiet NaN (sign=0, frac=all 1's). */ 265 struct fpn *fpu_newnan __P((struct fpemu *fe)); 266 267 /* 268 * Shift a number right some number of bits, taking care of round/sticky. 269 * Note that the result is probably not a well-formed number (it will lack 270 * the normal 1-bit mant[0]&FP_1). 271 */ 272 int fpu_shr __P((struct fpn * fp, int shr)); 273 /* 274 * Round a number according to the round mode in FPCR 275 */ 276 int fpu_round __P((register struct fpemu *fe, register struct fpn *fp)); 277 278 /* type conversion */ 279 void fpu_explode __P((struct fpemu *fe, struct fpn *fp, int t, u_int *src)); 280 void fpu_implode __P((struct fpemu *fe, struct fpn *fp, int t, u_int *dst)); 281 282 /* 283 * non-static emulation functions 284 */ 285 /* type 0 */ 286 int fpu_emul_fmovecr __P((struct fpemu *fe, struct instruction *insn)); 287 int fpu_emul_fstore __P((struct fpemu *fe, struct instruction *insn)); 288 int fpu_emul_fscale __P((struct fpemu *fe, struct instruction *insn)); 289 290 /* 291 * include function declarations of those which are called by fpu_emul_arith() 292 */ 293 #include "fpu_arith_proto.h" 294 295 int fpu_emulate __P((struct frame *frame, struct fpframe *fpf, ksiginfo_t *ksi)); 296 297 /* 298 * "helper" functions 299 */ 300 /* return values from constant rom */ 301 struct fpn *fpu_const __P((struct fpn *fp, u_int offset)); 302 /* update exceptions and FPSR */ 303 int fpu_upd_excp __P((struct fpemu *fe)); 304 u_int fpu_upd_fpsr __P((struct fpemu *fe, struct fpn *fp)); 305 306 /* address mode decoder, and load/store */ 307 int fpu_decode_ea __P((struct frame *frame, struct instruction *insn, 308 struct insn_ea *ea, int modreg)); 309 int fpu_load_ea __P((struct frame *frame, struct instruction *insn, 310 struct insn_ea *ea, char *dst)); 311 int fpu_store_ea __P((struct frame *frame, struct instruction *insn, 312 struct insn_ea *ea, char *src)); 313 314 /* fpu_subr.c */ 315 void fpu_norm __P((register struct fpn *fp)); 316 317 #if !defined(FPE_DEBUG) 318 # define FPE_DEBUG 0 319 #endif 320 321 #endif /* _FPU_EMULATE_H_ */ 322
Indexes created Wed Oct 01 19:09:53 GMT 2025