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fpu_explode.c revision 1.14.12.1
      1  1.14.12.1   skrll /*	$NetBSD: fpu_explode.c,v 1.14.12.1 2015/04/06 15:17:58 skrll Exp $ */
      2        1.1  briggs 
      3        1.1  briggs /*
      4        1.1  briggs  * Copyright (c) 1992, 1993
      5        1.1  briggs  *	The Regents of the University of California.  All rights reserved.
      6        1.1  briggs  *
      7        1.1  briggs  * This software was developed by the Computer Systems Engineering group
      8        1.1  briggs  * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
      9        1.1  briggs  * contributed to Berkeley.
     10        1.1  briggs  *
     11        1.1  briggs  * All advertising materials mentioning features or use of this software
     12        1.1  briggs  * must display the following acknowledgement:
     13        1.1  briggs  *	This product includes software developed by the University of
     14        1.1  briggs  *	California, Lawrence Berkeley Laboratory.
     15        1.1  briggs  *
     16        1.1  briggs  * Redistribution and use in source and binary forms, with or without
     17        1.1  briggs  * modification, are permitted provided that the following conditions
     18        1.1  briggs  * are met:
     19        1.1  briggs  * 1. Redistributions of source code must retain the above copyright
     20        1.1  briggs  *    notice, this list of conditions and the following disclaimer.
     21        1.1  briggs  * 2. Redistributions in binary form must reproduce the above copyright
     22        1.1  briggs  *    notice, this list of conditions and the following disclaimer in the
     23        1.1  briggs  *    documentation and/or other materials provided with the distribution.
     24        1.5     agc  * 3. Neither the name of the University nor the names of its contributors
     25        1.1  briggs  *    may be used to endorse or promote products derived from this software
     26        1.1  briggs  *    without specific prior written permission.
     27        1.1  briggs  *
     28        1.1  briggs  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
     29        1.1  briggs  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     30        1.1  briggs  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     31        1.1  briggs  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
     32        1.1  briggs  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     33        1.1  briggs  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     34        1.1  briggs  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     35        1.1  briggs  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     36        1.1  briggs  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     37        1.1  briggs  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     38        1.1  briggs  * SUCH DAMAGE.
     39        1.1  briggs  *
     40        1.1  briggs  *	@(#)fpu_explode.c	8.1 (Berkeley) 6/11/93
     41        1.1  briggs  */
     42        1.1  briggs 
     43        1.1  briggs /*
     44        1.1  briggs  * FPU subroutines: `explode' the machine's `packed binary' format numbers
     45        1.1  briggs  * into our internal format.
     46        1.1  briggs  */
     47        1.4   lukem 
     48        1.4   lukem #include <sys/cdefs.h>
     49  1.14.12.1   skrll __KERNEL_RCSID(0, "$NetBSD: fpu_explode.c,v 1.14.12.1 2015/04/06 15:17:58 skrll Exp $");
     50        1.1  briggs 
     51        1.1  briggs #include <sys/types.h>
     52        1.2  briggs #include <sys/systm.h>
     53        1.1  briggs 
     54        1.6  kleink #include <machine/ieee.h>
     55        1.1  briggs #include <machine/reg.h>
     56        1.1  briggs 
     57        1.1  briggs #include "fpu_arith.h"
     58        1.1  briggs #include "fpu_emulate.h"
     59        1.1  briggs 
     60        1.1  briggs 
     61        1.1  briggs /* Conversion to internal format -- note asymmetry. */
     62       1.14   isaki static int	fpu_itof(struct fpn *fp, uint32_t i);
     63       1.14   isaki static int	fpu_stof(struct fpn *fp, uint32_t i);
     64       1.14   isaki static int	fpu_dtof(struct fpn *fp, uint32_t i, uint32_t j);
     65       1.14   isaki static int	fpu_xtof(struct fpn *fp, uint32_t i, uint32_t j, uint32_t k);
     66        1.1  briggs 
     67        1.1  briggs /*
     68        1.1  briggs  * N.B.: in all of the following, we assume the FP format is
     69        1.1  briggs  *
     70        1.1  briggs  *	---------------------------
     71        1.1  briggs  *	| s | exponent | fraction |
     72        1.1  briggs  *	---------------------------
     73        1.1  briggs  *
     74        1.1  briggs  * (which represents -1**s * 1.fraction * 2**exponent), so that the
     75        1.1  briggs  * sign bit is way at the top (bit 31), the exponent is next, and
     76        1.1  briggs  * then the remaining bits mark the fraction.  A zero exponent means
     77        1.1  briggs  * zero or denormalized (0.fraction rather than 1.fraction), and the
     78        1.1  briggs  * maximum possible exponent, 2bias+1, signals inf (fraction==0) or NaN.
     79        1.1  briggs  *
     80        1.1  briggs  * Since the sign bit is always the topmost bit---this holds even for
     81        1.1  briggs  * integers---we set that outside all the *tof functions.  Each function
     82        1.1  briggs  * returns the class code for the new number (but note that we use
     83        1.1  briggs  * FPC_QNAN for all NaNs; fpu_explode will fix this if appropriate).
     84        1.1  briggs  */
     85        1.1  briggs 
     86        1.1  briggs /*
     87        1.1  briggs  * int -> fpn.
     88        1.1  briggs  */
     89        1.1  briggs static int
     90       1.14   isaki fpu_itof(struct fpn *fp, uint32_t i)
     91        1.1  briggs {
     92        1.1  briggs 
     93        1.1  briggs 	if (i == 0)
     94        1.1  briggs 		return (FPC_ZERO);
     95        1.1  briggs 	/*
     96        1.1  briggs 	 * The value FP_1 represents 2^FP_LG, so set the exponent
     97        1.1  briggs 	 * there and let normalization fix it up.  Convert negative
     98        1.1  briggs 	 * numbers to sign-and-magnitude.  Note that this relies on
     99        1.1  briggs 	 * fpu_norm()'s handling of `supernormals'; see fpu_subr.c.
    100        1.1  briggs 	 */
    101        1.1  briggs 	fp->fp_exp = FP_LG;
    102        1.1  briggs 	fp->fp_mant[0] = (int)i < 0 ? -i : i;
    103        1.1  briggs 	fp->fp_mant[1] = 0;
    104        1.1  briggs 	fp->fp_mant[2] = 0;
    105        1.1  briggs 	fpu_norm(fp);
    106        1.1  briggs 	return (FPC_NUM);
    107        1.1  briggs }
    108        1.1  briggs 
    109        1.1  briggs #define	mask(nbits) ((1 << (nbits)) - 1)
    110        1.1  briggs 
    111        1.1  briggs /*
    112        1.1  briggs  * All external floating formats convert to internal in the same manner,
    113        1.1  briggs  * as defined here.  Note that only normals get an implied 1.0 inserted.
    114        1.1  briggs  */
    115        1.1  briggs #define	FP_TOF(exp, expbias, allfrac, f0, f1, f2, f3) \
    116        1.1  briggs 	if (exp == 0) { \
    117        1.1  briggs 		if (allfrac == 0) \
    118        1.1  briggs 			return (FPC_ZERO); \
    119        1.1  briggs 		fp->fp_exp = 1 - expbias; \
    120        1.1  briggs 		fp->fp_mant[0] = f0; \
    121        1.1  briggs 		fp->fp_mant[1] = f1; \
    122        1.1  briggs 		fp->fp_mant[2] = f2; \
    123        1.1  briggs 		fpu_norm(fp); \
    124        1.1  briggs 		return (FPC_NUM); \
    125        1.1  briggs 	} \
    126        1.1  briggs 	if (exp == (2 * expbias + 1)) { \
    127        1.1  briggs 		if (allfrac == 0) \
    128        1.1  briggs 			return (FPC_INF); \
    129        1.1  briggs 		fp->fp_mant[0] = f0; \
    130        1.1  briggs 		fp->fp_mant[1] = f1; \
    131        1.1  briggs 		fp->fp_mant[2] = f2; \
    132        1.1  briggs 		return (FPC_QNAN); \
    133        1.1  briggs 	} \
    134        1.1  briggs 	fp->fp_exp = exp - expbias; \
    135        1.1  briggs 	fp->fp_mant[0] = FP_1 | f0; \
    136        1.1  briggs 	fp->fp_mant[1] = f1; \
    137        1.1  briggs 	fp->fp_mant[2] = f2; \
    138        1.1  briggs 	return (FPC_NUM)
    139        1.1  briggs 
    140        1.1  briggs /*
    141        1.1  briggs  * 32-bit single precision -> fpn.
    142        1.1  briggs  * We assume a single occupies at most (64-FP_LG) bits in the internal
    143        1.1  briggs  * format: i.e., needs at most fp_mant[0] and fp_mant[1].
    144        1.1  briggs  */
    145        1.1  briggs static int
    146       1.14   isaki fpu_stof(struct fpn *fp, uint32_t i)
    147        1.1  briggs {
    148       1.12   isaki 	int exp;
    149       1.14   isaki 	uint32_t frac, f0, f1;
    150        1.1  briggs #define SNG_SHIFT (SNG_FRACBITS - FP_LG)
    151        1.1  briggs 
    152        1.1  briggs 	exp = (i >> (32 - 1 - SNG_EXPBITS)) & mask(SNG_EXPBITS);
    153        1.1  briggs 	frac = i & mask(SNG_FRACBITS);
    154        1.1  briggs 	f0 = frac >> SNG_SHIFT;
    155        1.1  briggs 	f1 = frac << (32 - SNG_SHIFT);
    156        1.1  briggs 	FP_TOF(exp, SNG_EXP_BIAS, frac, f0, f1, 0, 0);
    157        1.1  briggs }
    158        1.1  briggs 
    159        1.1  briggs /*
    160        1.1  briggs  * 64-bit double -> fpn.
    161        1.1  briggs  * We assume this uses at most (96-FP_LG) bits.
    162        1.1  briggs  */
    163        1.1  briggs static int
    164       1.14   isaki fpu_dtof(struct fpn *fp, uint32_t i, uint32_t j)
    165        1.1  briggs {
    166       1.12   isaki 	int exp;
    167       1.14   isaki 	uint32_t frac, f0, f1, f2;
    168        1.1  briggs #define DBL_SHIFT (DBL_FRACBITS - 32 - FP_LG)
    169        1.1  briggs 
    170        1.1  briggs 	exp = (i >> (32 - 1 - DBL_EXPBITS)) & mask(DBL_EXPBITS);
    171        1.1  briggs 	frac = i & mask(DBL_FRACBITS - 32);
    172        1.1  briggs 	f0 = frac >> DBL_SHIFT;
    173        1.1  briggs 	f1 = (frac << (32 - DBL_SHIFT)) | (j >> DBL_SHIFT);
    174        1.1  briggs 	f2 = j << (32 - DBL_SHIFT);
    175        1.1  briggs 	frac |= j;
    176        1.1  briggs 	FP_TOF(exp, DBL_EXP_BIAS, frac, f0, f1, f2, 0);
    177        1.1  briggs }
    178        1.1  briggs 
    179        1.1  briggs /*
    180        1.1  briggs  * 96-bit extended -> fpn.
    181        1.1  briggs  */
    182        1.1  briggs static int
    183       1.14   isaki fpu_xtof(struct fpn *fp, uint32_t i, uint32_t j, uint32_t k)
    184        1.1  briggs {
    185       1.12   isaki 	int exp;
    186  1.14.12.1   skrll 	uint32_t f0, f1, f2;
    187        1.1  briggs #define EXT_SHIFT (EXT_FRACBITS - 1 - 32 - FP_LG)
    188        1.1  briggs 
    189        1.1  briggs 	exp = (i >> (32 - 1 - EXT_EXPBITS)) & mask(EXT_EXPBITS);
    190        1.1  briggs 	f0 = j >> EXT_SHIFT;
    191        1.1  briggs 	f1 = (j << (32 - EXT_SHIFT)) | (k >> EXT_SHIFT);
    192        1.1  briggs 	f2 = k << (32 - EXT_SHIFT);
    193        1.1  briggs 
    194        1.1  briggs 	/* m68k extended does not imply denormal by exp==0 */
    195        1.1  briggs 	if (exp == 0) {
    196  1.14.12.1   skrll 		if ((j | k) == 0)
    197        1.1  briggs 			return (FPC_ZERO);
    198        1.1  briggs 		fp->fp_exp = - EXT_EXP_BIAS;
    199        1.1  briggs 		fp->fp_mant[0] = f0;
    200        1.1  briggs 		fp->fp_mant[1] = f1;
    201        1.1  briggs 		fp->fp_mant[2] = f2;
    202        1.1  briggs 		fpu_norm(fp);
    203        1.1  briggs 		return (FPC_NUM);
    204        1.1  briggs 	}
    205        1.1  briggs 	if (exp == (2 * EXT_EXP_BIAS + 1)) {
    206  1.14.12.1   skrll 		/* MSB is an integer part and don't care */
    207  1.14.12.1   skrll 		if ((j & 0x7fffffff) == 0 && k == 0)
    208        1.1  briggs 			return (FPC_INF);
    209        1.1  briggs 		fp->fp_mant[0] = f0;
    210        1.1  briggs 		fp->fp_mant[1] = f1;
    211        1.1  briggs 		fp->fp_mant[2] = f2;
    212        1.1  briggs 		return (FPC_QNAN);
    213        1.1  briggs 	}
    214        1.1  briggs 	fp->fp_exp = exp - EXT_EXP_BIAS;
    215        1.1  briggs 	fp->fp_mant[0] = FP_1 | f0;
    216        1.1  briggs 	fp->fp_mant[1] = f1;
    217        1.1  briggs 	fp->fp_mant[2] = f2;
    218        1.1  briggs 	return (FPC_NUM);
    219        1.1  briggs }
    220        1.1  briggs 
    221        1.1  briggs /*
    222        1.1  briggs  * Explode the contents of a memory operand.
    223        1.1  briggs  */
    224        1.1  briggs void
    225       1.14   isaki fpu_explode(struct fpemu *fe, struct fpn *fp, int type, const uint32_t *space)
    226        1.1  briggs {
    227       1.14   isaki 	uint32_t s;
    228        1.1  briggs 
    229        1.1  briggs 	s = space[0];
    230        1.1  briggs 	fp->fp_sign = s >> 31;
    231        1.1  briggs 	fp->fp_sticky = 0;
    232        1.1  briggs 	switch (type) {
    233        1.1  briggs 
    234        1.1  briggs 	case FTYPE_BYT:
    235        1.1  briggs 		s >>= 8;
    236        1.1  briggs 	case FTYPE_WRD:
    237        1.1  briggs 		s >>= 16;
    238        1.1  briggs 	case FTYPE_LNG:
    239        1.1  briggs 		s = fpu_itof(fp, s);
    240        1.1  briggs 		break;
    241        1.1  briggs 
    242        1.1  briggs 	case FTYPE_SNG:
    243        1.1  briggs 		s = fpu_stof(fp, s);
    244        1.1  briggs 		break;
    245        1.1  briggs 
    246        1.1  briggs 	case FTYPE_DBL:
    247        1.1  briggs 		s = fpu_dtof(fp, s, space[1]);
    248        1.1  briggs 		break;
    249        1.1  briggs 
    250        1.1  briggs 	case FTYPE_EXT:
    251        1.1  briggs 		s = fpu_xtof(fp, s, space[1], space[2]);
    252        1.1  briggs 		break;
    253        1.1  briggs 
    254        1.1  briggs 	default:
    255        1.1  briggs 		panic("fpu_explode");
    256        1.1  briggs 	}
    257        1.1  briggs 	if (s == FPC_QNAN && (fp->fp_mant[0] & FP_QUIETBIT) == 0) {
    258        1.1  briggs 		/*
    259        1.1  briggs 		 * Input is a signalling NaN.  All operations that return
    260        1.1  briggs 		 * an input NaN operand put it through a ``NaN conversion'',
    261        1.1  briggs 		 * which basically just means ``turn on the quiet bit''.
    262        1.1  briggs 		 * We do this here so that all NaNs internally look quiet
    263        1.1  briggs 		 * (we can tell signalling ones by their class).
    264        1.1  briggs 		 */
    265        1.1  briggs 		fp->fp_mant[0] |= FP_QUIETBIT;
    266        1.1  briggs 		fe->fe_fpsr |= FPSR_SNAN;	/* assert SNAN exception */
    267        1.1  briggs 		s = FPC_SNAN;
    268        1.1  briggs 	}
    269        1.1  briggs 	fp->fp_class = s;
    270        1.1  briggs }
    271