fpu_explode.c revision 1.2
1 /* $NetBSD: fpu_explode.c,v 1.2 1996/04/30 11:52:18 briggs Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This software was developed by the Computer Systems Engineering group 8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 9 * contributed to Berkeley. 10 * 11 * All advertising materials mentioning features or use of this software 12 * must display the following acknowledgement: 13 * This product includes software developed by the University of 14 * California, Lawrence Berkeley Laboratory. 15 * 16 * Redistribution and use in source and binary forms, with or without 17 * modification, are permitted provided that the following conditions 18 * are met: 19 * 1. Redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer. 21 * 2. Redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution. 24 * 3. All advertising materials mentioning features or use of this software 25 * must display the following acknowledgement: 26 * This product includes software developed by the University of 27 * California, Berkeley and its contributors. 28 * 4. Neither the name of the University nor the names of its contributors 29 * may be used to endorse or promote products derived from this software 30 * without specific prior written permission. 31 * 32 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 33 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 34 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 35 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 36 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 37 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 38 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 39 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 40 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 41 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 42 * SUCH DAMAGE. 43 * 44 * @(#)fpu_explode.c 8.1 (Berkeley) 6/11/93 45 */ 46 47 /* 48 * FPU subroutines: `explode' the machine's `packed binary' format numbers 49 * into our internal format. 50 */ 51 52 #include <sys/types.h> 53 #include <sys/systm.h> 54 55 #include "ieee.h" 56 #include <machine/reg.h> 57 58 #include "fpu_arith.h" 59 #include "fpu_emulate.h" 60 61 62 /* Conversion to internal format -- note asymmetry. */ 63 static int fpu_itof __P((struct fpn *fp, u_int i)); 64 static int fpu_stof __P((struct fpn *fp, u_int i)); 65 static int fpu_dtof __P((struct fpn *fp, u_int i, u_int j)); 66 static int fpu_xtof __P((struct fpn *fp, u_int i, u_int j, u_int k)); 67 68 /* 69 * N.B.: in all of the following, we assume the FP format is 70 * 71 * --------------------------- 72 * | s | exponent | fraction | 73 * --------------------------- 74 * 75 * (which represents -1**s * 1.fraction * 2**exponent), so that the 76 * sign bit is way at the top (bit 31), the exponent is next, and 77 * then the remaining bits mark the fraction. A zero exponent means 78 * zero or denormalized (0.fraction rather than 1.fraction), and the 79 * maximum possible exponent, 2bias+1, signals inf (fraction==0) or NaN. 80 * 81 * Since the sign bit is always the topmost bit---this holds even for 82 * integers---we set that outside all the *tof functions. Each function 83 * returns the class code for the new number (but note that we use 84 * FPC_QNAN for all NaNs; fpu_explode will fix this if appropriate). 85 */ 86 87 /* 88 * int -> fpn. 89 */ 90 static int 91 fpu_itof(fp, i) 92 register struct fpn *fp; 93 register u_int i; 94 { 95 96 if (i == 0) 97 return (FPC_ZERO); 98 /* 99 * The value FP_1 represents 2^FP_LG, so set the exponent 100 * there and let normalization fix it up. Convert negative 101 * numbers to sign-and-magnitude. Note that this relies on 102 * fpu_norm()'s handling of `supernormals'; see fpu_subr.c. 103 */ 104 fp->fp_exp = FP_LG; 105 fp->fp_mant[0] = (int)i < 0 ? -i : i; 106 fp->fp_mant[1] = 0; 107 fp->fp_mant[2] = 0; 108 fp->fp_mant[3] = 0; 109 fpu_norm(fp); 110 return (FPC_NUM); 111 } 112 113 #define mask(nbits) ((1 << (nbits)) - 1) 114 115 /* 116 * All external floating formats convert to internal in the same manner, 117 * as defined here. Note that only normals get an implied 1.0 inserted. 118 */ 119 #define FP_TOF(exp, expbias, allfrac, f0, f1, f2, f3) \ 120 if (exp == 0) { \ 121 if (allfrac == 0) \ 122 return (FPC_ZERO); \ 123 fp->fp_exp = 1 - expbias; \ 124 fp->fp_mant[0] = f0; \ 125 fp->fp_mant[1] = f1; \ 126 fp->fp_mant[2] = f2; \ 127 fp->fp_mant[3] = f3; \ 128 fpu_norm(fp); \ 129 return (FPC_NUM); \ 130 } \ 131 if (exp == (2 * expbias + 1)) { \ 132 if (allfrac == 0) \ 133 return (FPC_INF); \ 134 fp->fp_mant[0] = f0; \ 135 fp->fp_mant[1] = f1; \ 136 fp->fp_mant[2] = f2; \ 137 fp->fp_mant[3] = f3; \ 138 return (FPC_QNAN); \ 139 } \ 140 fp->fp_exp = exp - expbias; \ 141 fp->fp_mant[0] = FP_1 | f0; \ 142 fp->fp_mant[1] = f1; \ 143 fp->fp_mant[2] = f2; \ 144 fp->fp_mant[3] = f3; \ 145 return (FPC_NUM) 146 147 /* 148 * 32-bit single precision -> fpn. 149 * We assume a single occupies at most (64-FP_LG) bits in the internal 150 * format: i.e., needs at most fp_mant[0] and fp_mant[1]. 151 */ 152 static int 153 fpu_stof(fp, i) 154 register struct fpn *fp; 155 register u_int i; 156 { 157 register int exp; 158 register u_int frac, f0, f1; 159 #define SNG_SHIFT (SNG_FRACBITS - FP_LG) 160 161 exp = (i >> (32 - 1 - SNG_EXPBITS)) & mask(SNG_EXPBITS); 162 frac = i & mask(SNG_FRACBITS); 163 f0 = frac >> SNG_SHIFT; 164 f1 = frac << (32 - SNG_SHIFT); 165 FP_TOF(exp, SNG_EXP_BIAS, frac, f0, f1, 0, 0); 166 } 167 168 /* 169 * 64-bit double -> fpn. 170 * We assume this uses at most (96-FP_LG) bits. 171 */ 172 static int 173 fpu_dtof(fp, i, j) 174 register struct fpn *fp; 175 register u_int i, j; 176 { 177 register int exp; 178 register u_int frac, f0, f1, f2; 179 #define DBL_SHIFT (DBL_FRACBITS - 32 - FP_LG) 180 181 exp = (i >> (32 - 1 - DBL_EXPBITS)) & mask(DBL_EXPBITS); 182 frac = i & mask(DBL_FRACBITS - 32); 183 f0 = frac >> DBL_SHIFT; 184 f1 = (frac << (32 - DBL_SHIFT)) | (j >> DBL_SHIFT); 185 f2 = j << (32 - DBL_SHIFT); 186 frac |= j; 187 FP_TOF(exp, DBL_EXP_BIAS, frac, f0, f1, f2, 0); 188 } 189 190 /* 191 * 96-bit extended -> fpn. 192 */ 193 static int 194 fpu_xtof(fp, i, j, k) 195 register struct fpn *fp; 196 register u_int i, j, k; 197 { 198 register int exp; 199 register u_int frac, f0, f1, f2; 200 #define EXT_SHIFT (EXT_FRACBITS - 1 - 32 - FP_LG) 201 202 exp = (i >> (32 - 1 - EXT_EXPBITS)) & mask(EXT_EXPBITS); 203 f0 = j >> EXT_SHIFT; 204 f1 = (j << (32 - EXT_SHIFT)) | (k >> EXT_SHIFT); 205 f2 = k << (32 - EXT_SHIFT); 206 frac = j | k; 207 208 /* m68k extended does not imply denormal by exp==0 */ 209 if (exp == 0) { 210 if (frac == 0) 211 return (FPC_ZERO); 212 fp->fp_exp = - EXT_EXP_BIAS; 213 fp->fp_mant[0] = f0; 214 fp->fp_mant[1] = f1; 215 fp->fp_mant[2] = f2; 216 fp->fp_mant[3] = 0; 217 fpu_norm(fp); 218 return (FPC_NUM); 219 } 220 if (exp == (2 * EXT_EXP_BIAS + 1)) { 221 if (frac == 0) 222 return (FPC_INF); 223 fp->fp_mant[0] = f0; 224 fp->fp_mant[1] = f1; 225 fp->fp_mant[2] = f2; 226 fp->fp_mant[3] = 0; 227 return (FPC_QNAN); 228 } 229 fp->fp_exp = exp - EXT_EXP_BIAS; 230 fp->fp_mant[0] = FP_1 | f0; 231 fp->fp_mant[1] = f1; 232 fp->fp_mant[2] = f2; 233 fp->fp_mant[3] = 0; 234 return (FPC_NUM); 235 } 236 237 /* 238 * Explode the contents of a memory operand. 239 */ 240 void 241 fpu_explode(fe, fp, type, space) 242 register struct fpemu *fe; 243 register struct fpn *fp; 244 int type; 245 register u_int *space; 246 { 247 register u_int s; 248 249 s = space[0]; 250 fp->fp_sign = s >> 31; 251 fp->fp_sticky = 0; 252 switch (type) { 253 254 case FTYPE_BYT: 255 s >>= 8; 256 case FTYPE_WRD: 257 s >>= 16; 258 case FTYPE_LNG: 259 s = fpu_itof(fp, s); 260 break; 261 262 case FTYPE_SNG: 263 s = fpu_stof(fp, s); 264 break; 265 266 case FTYPE_DBL: 267 s = fpu_dtof(fp, s, space[1]); 268 break; 269 270 case FTYPE_EXT: 271 s = fpu_xtof(fp, s, space[1], space[2]); 272 break; 273 274 default: 275 panic("fpu_explode"); 276 } 277 if (s == FPC_QNAN && (fp->fp_mant[0] & FP_QUIETBIT) == 0) { 278 /* 279 * Input is a signalling NaN. All operations that return 280 * an input NaN operand put it through a ``NaN conversion'', 281 * which basically just means ``turn on the quiet bit''. 282 * We do this here so that all NaNs internally look quiet 283 * (we can tell signalling ones by their class). 284 */ 285 fp->fp_mant[0] |= FP_QUIETBIT; 286 fe->fe_fpsr |= FPSR_SNAN; /* assert SNAN exception */ 287 s = FPC_SNAN; 288 } 289 fp->fp_class = s; 290 } 291
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