fpu_explode.c revision 1.4
1 /* $NetBSD: fpu_explode.c,v 1.4 2003/07/15 02:43:09 lukem Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This software was developed by the Computer Systems Engineering group 8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 9 * contributed to Berkeley. 10 * 11 * All advertising materials mentioning features or use of this software 12 * must display the following acknowledgement: 13 * This product includes software developed by the University of 14 * California, Lawrence Berkeley Laboratory. 15 * 16 * Redistribution and use in source and binary forms, with or without 17 * modification, are permitted provided that the following conditions 18 * are met: 19 * 1. Redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer. 21 * 2. Redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution. 24 * 3. All advertising materials mentioning features or use of this software 25 * must display the following acknowledgement: 26 * This product includes software developed by the University of 27 * California, Berkeley and its contributors. 28 * 4. Neither the name of the University nor the names of its contributors 29 * may be used to endorse or promote products derived from this software 30 * without specific prior written permission. 31 * 32 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 33 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 34 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 35 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 36 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 37 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 38 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 39 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 40 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 41 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 42 * SUCH DAMAGE. 43 * 44 * @(#)fpu_explode.c 8.1 (Berkeley) 6/11/93 45 */ 46 47 /* 48 * FPU subroutines: `explode' the machine's `packed binary' format numbers 49 * into our internal format. 50 */ 51 52 #include <sys/cdefs.h> 53 __KERNEL_RCSID(0, "$NetBSD: fpu_explode.c,v 1.4 2003/07/15 02:43:09 lukem Exp $"); 54 55 #include <sys/types.h> 56 #include <sys/systm.h> 57 58 #include "ieee.h" 59 #include <machine/reg.h> 60 61 #include "fpu_arith.h" 62 #include "fpu_emulate.h" 63 64 65 /* Conversion to internal format -- note asymmetry. */ 66 static int fpu_itof __P((struct fpn *fp, u_int i)); 67 static int fpu_stof __P((struct fpn *fp, u_int i)); 68 static int fpu_dtof __P((struct fpn *fp, u_int i, u_int j)); 69 static int fpu_xtof __P((struct fpn *fp, u_int i, u_int j, u_int k)); 70 71 /* 72 * N.B.: in all of the following, we assume the FP format is 73 * 74 * --------------------------- 75 * | s | exponent | fraction | 76 * --------------------------- 77 * 78 * (which represents -1**s * 1.fraction * 2**exponent), so that the 79 * sign bit is way at the top (bit 31), the exponent is next, and 80 * then the remaining bits mark the fraction. A zero exponent means 81 * zero or denormalized (0.fraction rather than 1.fraction), and the 82 * maximum possible exponent, 2bias+1, signals inf (fraction==0) or NaN. 83 * 84 * Since the sign bit is always the topmost bit---this holds even for 85 * integers---we set that outside all the *tof functions. Each function 86 * returns the class code for the new number (but note that we use 87 * FPC_QNAN for all NaNs; fpu_explode will fix this if appropriate). 88 */ 89 90 /* 91 * int -> fpn. 92 */ 93 static int 94 fpu_itof(fp, i) 95 register struct fpn *fp; 96 register u_int i; 97 { 98 99 if (i == 0) 100 return (FPC_ZERO); 101 /* 102 * The value FP_1 represents 2^FP_LG, so set the exponent 103 * there and let normalization fix it up. Convert negative 104 * numbers to sign-and-magnitude. Note that this relies on 105 * fpu_norm()'s handling of `supernormals'; see fpu_subr.c. 106 */ 107 fp->fp_exp = FP_LG; 108 fp->fp_mant[0] = (int)i < 0 ? -i : i; 109 fp->fp_mant[1] = 0; 110 fp->fp_mant[2] = 0; 111 fpu_norm(fp); 112 return (FPC_NUM); 113 } 114 115 #define mask(nbits) ((1 << (nbits)) - 1) 116 117 /* 118 * All external floating formats convert to internal in the same manner, 119 * as defined here. Note that only normals get an implied 1.0 inserted. 120 */ 121 #define FP_TOF(exp, expbias, allfrac, f0, f1, f2, f3) \ 122 if (exp == 0) { \ 123 if (allfrac == 0) \ 124 return (FPC_ZERO); \ 125 fp->fp_exp = 1 - expbias; \ 126 fp->fp_mant[0] = f0; \ 127 fp->fp_mant[1] = f1; \ 128 fp->fp_mant[2] = f2; \ 129 fpu_norm(fp); \ 130 return (FPC_NUM); \ 131 } \ 132 if (exp == (2 * expbias + 1)) { \ 133 if (allfrac == 0) \ 134 return (FPC_INF); \ 135 fp->fp_mant[0] = f0; \ 136 fp->fp_mant[1] = f1; \ 137 fp->fp_mant[2] = f2; \ 138 return (FPC_QNAN); \ 139 } \ 140 fp->fp_exp = exp - expbias; \ 141 fp->fp_mant[0] = FP_1 | f0; \ 142 fp->fp_mant[1] = f1; \ 143 fp->fp_mant[2] = f2; \ 144 return (FPC_NUM) 145 146 /* 147 * 32-bit single precision -> fpn. 148 * We assume a single occupies at most (64-FP_LG) bits in the internal 149 * format: i.e., needs at most fp_mant[0] and fp_mant[1]. 150 */ 151 static int 152 fpu_stof(fp, i) 153 register struct fpn *fp; 154 register u_int i; 155 { 156 register int exp; 157 register u_int frac, f0, f1; 158 #define SNG_SHIFT (SNG_FRACBITS - FP_LG) 159 160 exp = (i >> (32 - 1 - SNG_EXPBITS)) & mask(SNG_EXPBITS); 161 frac = i & mask(SNG_FRACBITS); 162 f0 = frac >> SNG_SHIFT; 163 f1 = frac << (32 - SNG_SHIFT); 164 FP_TOF(exp, SNG_EXP_BIAS, frac, f0, f1, 0, 0); 165 } 166 167 /* 168 * 64-bit double -> fpn. 169 * We assume this uses at most (96-FP_LG) bits. 170 */ 171 static int 172 fpu_dtof(fp, i, j) 173 register struct fpn *fp; 174 register u_int i, j; 175 { 176 register int exp; 177 register u_int frac, f0, f1, f2; 178 #define DBL_SHIFT (DBL_FRACBITS - 32 - FP_LG) 179 180 exp = (i >> (32 - 1 - DBL_EXPBITS)) & mask(DBL_EXPBITS); 181 frac = i & mask(DBL_FRACBITS - 32); 182 f0 = frac >> DBL_SHIFT; 183 f1 = (frac << (32 - DBL_SHIFT)) | (j >> DBL_SHIFT); 184 f2 = j << (32 - DBL_SHIFT); 185 frac |= j; 186 FP_TOF(exp, DBL_EXP_BIAS, frac, f0, f1, f2, 0); 187 } 188 189 /* 190 * 96-bit extended -> fpn. 191 */ 192 static int 193 fpu_xtof(fp, i, j, k) 194 register struct fpn *fp; 195 register u_int i, j, k; 196 { 197 register int exp; 198 register u_int frac, f0, f1, f2; 199 #define EXT_SHIFT (EXT_FRACBITS - 1 - 32 - FP_LG) 200 201 exp = (i >> (32 - 1 - EXT_EXPBITS)) & mask(EXT_EXPBITS); 202 f0 = j >> EXT_SHIFT; 203 f1 = (j << (32 - EXT_SHIFT)) | (k >> EXT_SHIFT); 204 f2 = k << (32 - EXT_SHIFT); 205 frac = j | k; 206 207 /* m68k extended does not imply denormal by exp==0 */ 208 if (exp == 0) { 209 if (frac == 0) 210 return (FPC_ZERO); 211 fp->fp_exp = - EXT_EXP_BIAS; 212 fp->fp_mant[0] = f0; 213 fp->fp_mant[1] = f1; 214 fp->fp_mant[2] = f2; 215 fpu_norm(fp); 216 return (FPC_NUM); 217 } 218 if (exp == (2 * EXT_EXP_BIAS + 1)) { 219 if (frac == 0) 220 return (FPC_INF); 221 fp->fp_mant[0] = f0; 222 fp->fp_mant[1] = f1; 223 fp->fp_mant[2] = f2; 224 return (FPC_QNAN); 225 } 226 fp->fp_exp = exp - EXT_EXP_BIAS; 227 fp->fp_mant[0] = FP_1 | f0; 228 fp->fp_mant[1] = f1; 229 fp->fp_mant[2] = f2; 230 return (FPC_NUM); 231 } 232 233 /* 234 * Explode the contents of a memory operand. 235 */ 236 void 237 fpu_explode(fe, fp, type, space) 238 register struct fpemu *fe; 239 register struct fpn *fp; 240 int type; 241 register u_int *space; 242 { 243 register u_int s; 244 245 s = space[0]; 246 fp->fp_sign = s >> 31; 247 fp->fp_sticky = 0; 248 switch (type) { 249 250 case FTYPE_BYT: 251 s >>= 8; 252 case FTYPE_WRD: 253 s >>= 16; 254 case FTYPE_LNG: 255 s = fpu_itof(fp, s); 256 break; 257 258 case FTYPE_SNG: 259 s = fpu_stof(fp, s); 260 break; 261 262 case FTYPE_DBL: 263 s = fpu_dtof(fp, s, space[1]); 264 break; 265 266 case FTYPE_EXT: 267 s = fpu_xtof(fp, s, space[1], space[2]); 268 break; 269 270 default: 271 panic("fpu_explode"); 272 } 273 if (s == FPC_QNAN && (fp->fp_mant[0] & FP_QUIETBIT) == 0) { 274 /* 275 * Input is a signalling NaN. All operations that return 276 * an input NaN operand put it through a ``NaN conversion'', 277 * which basically just means ``turn on the quiet bit''. 278 * We do this here so that all NaNs internally look quiet 279 * (we can tell signalling ones by their class). 280 */ 281 fp->fp_mant[0] |= FP_QUIETBIT; 282 fe->fe_fpsr |= FPSR_SNAN; /* assert SNAN exception */ 283 s = FPC_SNAN; 284 } 285 fp->fp_class = s; 286 } 287
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