fpu_fmovecr.c revision 1.3 1 1.3 briggs /* $NetBSD: fpu_fmovecr.c,v 1.3 1996/02/04 02:17:42 briggs Exp $ */
2 1.1 briggs
3 1.1 briggs /*
4 1.1 briggs * Copyright (c) 1995 Ken Nakata
5 1.1 briggs * All rights reserved.
6 1.1 briggs *
7 1.1 briggs * Redistribution and use in source and binary forms, with or without
8 1.1 briggs * modification, are permitted provided that the following conditions
9 1.1 briggs * are met:
10 1.1 briggs * 1. Redistributions of source code must retain the above copyright
11 1.1 briggs * notice, this list of conditions and the following disclaimer.
12 1.1 briggs * 2. Redistributions in binary form must reproduce the above copyright
13 1.1 briggs * notice, this list of conditions and the following disclaimer in the
14 1.1 briggs * documentation and/or other materials provided with the distribution.
15 1.1 briggs * 3. Neither the name of the author nor the names of its contributors
16 1.1 briggs * may be used to endorse or promote products derived from this software
17 1.1 briggs * without specific prior written permission.
18 1.1 briggs *
19 1.1 briggs * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 1.1 briggs * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 1.1 briggs * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 1.1 briggs * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23 1.1 briggs * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 1.1 briggs * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 1.1 briggs * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 1.1 briggs * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 1.1 briggs * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 1.1 briggs * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 1.1 briggs * SUCH DAMAGE.
30 1.1 briggs *
31 1.1 briggs * @(#)fpu_fmovecr.c 10/8/95
32 1.1 briggs */
33 1.1 briggs
34 1.3 briggs #include <sys/param.h>
35 1.1 briggs #include <machine/frame.h>
36 1.1 briggs
37 1.1 briggs #include "fpu_emulate.h"
38 1.1 briggs
39 1.1 briggs static struct fpn constrom[] = {
40 1.1 briggs /* fp_class, fp_sign, fp_exp, fp_sticky, fp_mant[0] ... [3] */
41 1.1 briggs { FPC_NUM, 0, 1, 0, 0x6487e, 0xd5110b46, 0x11a80000, 0x0 },
42 1.1 briggs { FPC_NUM, 0, -2, 0, 0x4d104, 0xd427de7f, 0xbcc00000, 0x0 },
43 1.1 briggs { FPC_NUM, 0, 1, 0, 0x56fc2, 0xa2c515da, 0x54d00000, 0x0 },
44 1.1 briggs { FPC_NUM, 0, 0, 0, 0x5c551, 0xd94ae0bf, 0x85e00000, 0x0 },
45 1.1 briggs { FPC_NUM, 0, -2, 0, 0x6f2de, 0xc549b943, 0x8ca80000, 0x0 },
46 1.1 briggs { FPC_ZERO, 0, 0, 0, 0x0, 0x0, 0x0, 0x0 },
47 1.1 briggs { FPC_NUM, 0, -1, 0, 0x58b90, 0xbfbe8e7b, 0xcd600000, 0x0 },
48 1.1 briggs { FPC_NUM, 0, 1, 0, 0x49aec, 0x6eed5545, 0x60b80000, 0x0 },
49 1.1 briggs { FPC_NUM, 0, 0, 0, 0x40000, 0x0, 0x0, 0x0 },
50 1.1 briggs { FPC_NUM, 0, 3, 0, 0x50000, 0x0, 0x0, 0x0 },
51 1.1 briggs { FPC_NUM, 0, 6, 0, 0x64000, 0x0, 0x0, 0x0 },
52 1.1 briggs { FPC_NUM, 0, 13, 0, 0x4e200, 0x0, 0x0, 0x0 },
53 1.1 briggs { FPC_NUM, 0, 26, 0, 0x5f5e1, 0x0, 0x0, 0x0 },
54 1.1 briggs { FPC_NUM, 0, 53, 0, 0x470de, 0x4df82000, 0x0, 0x0 },
55 1.1 briggs { FPC_NUM, 0, 106, 0, 0x4ee2d, 0x6d415b85, 0xacf00000, 0x0 },
56 1.1 briggs { FPC_NUM, 0, 212, 0, 0x613c0, 0xfa4ffe7d, 0x36a80000, 0x0 },
57 1.1 briggs { FPC_NUM, 0, 425, 0, 0x49dd2, 0x3e4c074c, 0x67000000, 0x0 },
58 1.1 briggs { FPC_NUM, 0, 850, 0, 0x553f7, 0x5fdcefce, 0xf4700000, 0x0 },
59 1.1 briggs { FPC_NUM, 0, 1700, 0, 0x718cd, 0x5753074, 0x8e380000, 0x0 },
60 1.1 briggs { FPC_NUM, 0, 3401, 0, 0x64bb3, 0xac340ba8, 0x60b80000, 0x0 },
61 1.1 briggs { FPC_NUM, 0, 6803, 0, 0x4f459, 0xdaee29ea, 0xef280000, 0x0 },
62 1.1 briggs { FPC_NUM, 0, 13606, 0, 0x62302, 0x90145104, 0xbcd80000, 0x0 },
63 1.1 briggs };
64 1.1 briggs
65 1.1 briggs struct fpn *
66 1.1 briggs fpu_const(fp, offset)
67 1.1 briggs struct fpn *fp;
68 1.1 briggs u_int offset;
69 1.1 briggs {
70 1.1 briggs struct fpn *r;
71 1.1 briggs int i;
72 1.1 briggs
73 1.1 briggs #ifdef DEBUG
74 1.1 briggs if (fp == NULL) {
75 1.1 briggs panic("fpu_const: NULL pointer passed\n");
76 1.1 briggs }
77 1.1 briggs #endif
78 1.1 briggs if (offset == 0) {
79 1.1 briggs r = &constrom[0];
80 1.1 briggs } else if (0xb <= offset && offset <= 0xe) {
81 1.1 briggs r = &constrom[offset - 0xb + 1];
82 1.1 briggs } else if (0x30 <= offset && offset <= 0x3f) {
83 1.1 briggs r = &constrom[offset - 0x30 + 6];
84 1.1 briggs } else {
85 1.1 briggs /* return 0.0 for anything else (incl. valid offset 0xf) */
86 1.1 briggs r = &constrom[5];
87 1.1 briggs }
88 1.1 briggs
89 1.1 briggs CPYFPN(fp, r);
90 1.1 briggs
91 1.1 briggs return fp;
92 1.1 briggs }
93 1.1 briggs
94 1.1 briggs int
95 1.1 briggs fpu_emul_fmovecr(fe, insn)
96 1.1 briggs struct fpemu *fe;
97 1.1 briggs struct instruction *insn;
98 1.1 briggs {
99 1.1 briggs int dstreg, offset, sig;
100 1.1 briggs u_int *fpreg;
101 1.1 briggs
102 1.1 briggs dstreg = (insn->is_word1 >> 7) & 0x7;
103 1.1 briggs offset = insn->is_word1 & 0x7F;
104 1.1 briggs fpreg = &(fe->fe_fpframe->fpf_regs[0]);
105 1.1 briggs
106 1.1 briggs (void)fpu_const(&fe->fe_f3, offset);
107 1.1 briggs (void)fpu_upd_fpsr(fe, &fe->fe_f3);
108 1.1 briggs fpu_implode(fe, &fe->fe_f3, FTYPE_EXT, &fpreg[dstreg * 3]);
109 1.2 briggs if (fpu_debug_level & DL_RESULT) {
110 1.1 briggs printf(" fpu_emul_fmovecr: result %08x,%08x,%08x to FP%d\n",
111 1.1 briggs fpreg[dstreg * 3], fpreg[dstreg * 3 + 1], fpreg[dstreg * 3 + 2],
112 1.1 briggs dstreg);
113 1.1 briggs }
114 1.1 briggs return 0;
115 1.1 briggs }
116