fpu_fscale.c revision 1.17
1 /* $NetBSD: fpu_fscale.c,v 1.17 2025/01/06 07:34:24 isaki Exp $ */ 2 3 /* 4 * Copyright (c) 1995 Ken Nakata 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 4. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Gordon Ross 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * FSCALE - separated from the other type0 arithmetic instructions 35 * for performance reason; maybe unnecessary, but FSCALE assumes 36 * the source operand be an integer. It performs type conversion 37 * only if the source operand is *not* an integer. 38 */ 39 40 #include <sys/cdefs.h> 41 __KERNEL_RCSID(0, "$NetBSD: fpu_fscale.c,v 1.17 2025/01/06 07:34:24 isaki Exp $"); 42 43 #include <sys/types.h> 44 #include <sys/signal.h> 45 #include <sys/systm.h> 46 #include <machine/frame.h> 47 48 #include "fpu_emulate.h" 49 50 int 51 fpu_emul_fscale(struct fpemu *fe, struct instruction *insn) 52 { 53 struct frame *frame; 54 uint32_t *fpregs; 55 int word1, sig; 56 int regnum, format; 57 int modreg; 58 int scale, sign, exp; 59 uint32_t m0, m1; 60 uint32_t buf[3], fpsr; 61 #if DEBUG_FPE 62 int flags; 63 char regname; 64 #endif 65 66 scale = sig = 0; 67 frame = fe->fe_frame; 68 fpregs = &(fe->fe_fpframe->fpf_regs[0]); 69 /* clear all exceptions and conditions */ 70 fpsr = fe->fe_fpsr & ~FPSR_EXCP & ~FPSR_CCB; 71 #if DEBUG_FPE 72 printf("fpu_emul_fscale: FPSR = %08x, FPCR = %08x\n", fpsr, fe->fe_fpcr); 73 #endif 74 75 word1 = insn->is_word1; 76 format = (word1 >> 10) & 7; 77 regnum = (word1 >> 7) & 7; 78 79 fe->fe_fpcr &= FPCR_ROUND; 80 fe->fe_fpcr |= FPCR_ZERO; 81 82 /* get the source operand */ 83 if ((word1 & 0x4000) == 0) { 84 #if DEBUG_FPE 85 printf("fpu_emul_fscale: FP%d op FP%d => FP%d\n", 86 format, regnum, regnum); 87 /* the operand is an FP reg */ 88 printf("fpu_emul_scale: src opr FP%d=%08x%08x%08x\n", 89 format, fpregs[format*3], fpregs[format*3+1], 90 fpregs[format*3+2]); 91 #endif 92 fpu_explode(fe, &fe->fe_f2, FTYPE_EXT, &fpregs[format * 3]); 93 fpu_implode(fe, &fe->fe_f2, FTYPE_LNG, buf); 94 scale = buf[0]; 95 } else { 96 /* the operand is in memory */ 97 if (format == FTYPE_DBL) { 98 insn->is_datasize = 8; 99 } else if (format == FTYPE_SNG || format == FTYPE_LNG) { 100 insn->is_datasize = 4; 101 } else if (format == FTYPE_WRD) { 102 insn->is_datasize = 2; 103 } else if (format == FTYPE_BYT) { 104 insn->is_datasize = 1; 105 } else if (format == FTYPE_EXT) { 106 insn->is_datasize = 12; 107 } else { 108 /* invalid or unsupported operand format */ 109 sig = SIGFPE; 110 return sig; 111 } 112 113 /* Check an illegal mod/reg. */ 114 modreg = insn->is_opcode & 077; 115 if ((modreg >> 3) == 1/*An*/ || modreg >= 075) { 116 return SIGILL; 117 } 118 119 /* Get effective address. (modreg=opcode&077) */ 120 sig = fpu_decode_ea(frame, insn, &insn->is_ea, insn->is_opcode); 121 if (sig) { 122 #if DEBUG_FPE 123 printf("fpu_emul_fscale: error in decode_ea\n"); 124 #endif 125 return sig; 126 } 127 128 if (insn->is_ea.ea_flags == EA_DIRECT && 129 insn->is_datasize > 4) { 130 #if DEBUG_FPE 131 printf("%s: attempted to fetch dbl/ext from reg\n", 132 __func__); 133 #endif 134 return SIGILL; 135 } 136 137 #if DEBUG_FPE 138 printf("fpu_emul_fscale: addr mode = "); 139 flags = insn->is_ea.ea_flags; 140 regname = (insn->is_ea.ea_regnum & 8) ? 'a' : 'd'; 141 142 if (flags & EA_DIRECT) { 143 printf("%c%d\n", regname, insn->is_ea.ea_regnum & 7); 144 } else if (flags & EA_PREDECR) { 145 printf("%c%d@-\n", regname, insn->is_ea.ea_regnum & 7); 146 } else if (flags & EA_POSTINCR) { 147 printf("%c%d@+\n", regname, insn->is_ea.ea_regnum & 7); 148 } else if (flags & EA_OFFSET) { 149 printf("%c%d@(%d)\n", 150 regname, insn->is_ea.ea_regnum & 7, 151 insn->is_ea.ea_offset); 152 } else if (flags & EA_INDEXED) { 153 printf("%c%d@(...)\n", 154 regname, insn->is_ea.ea_regnum & 7); 155 } else if (flags & EA_ABS) { 156 printf("0x%08x\n", insn->is_ea.ea_absaddr); 157 } else if (flags & EA_PC_REL) { 158 printf("pc@(%d)\n", insn->is_ea.ea_offset); 159 } else if (flags & EA_IMMED) { 160 printf("#0x%08x%08x%08x\n", 161 insn->is_ea.ea_immed[0], 162 insn->is_ea.ea_immed[1], 163 insn->is_ea.ea_immed[2]); 164 } else { 165 printf("%c%d@\n", regname, insn->is_ea.ea_regnum & 7); 166 } 167 #endif 168 fpu_load_ea(frame, insn, &insn->is_ea, (char*)buf); 169 170 #if DEBUG_FPE 171 printf("fpu_emul_fscale: src = %08x%08x%08x, siz = %d\n", 172 buf[0], buf[1], buf[2], insn->is_datasize); 173 #endif 174 if (format == FTYPE_LNG) { 175 /* nothing */ 176 scale = buf[0]; 177 } else if (format == FTYPE_WRD) { 178 /* sign-extend */ 179 scale = buf[0] & 0xffff; 180 if (scale & 0x8000) { 181 scale |= 0xffff0000; 182 } 183 } else if (format == FTYPE_BYT) { 184 /* sign-extend */ 185 scale = buf[0] & 0xff; 186 if (scale & 0x80) { 187 scale |= 0xffffff00; 188 } 189 } else if (format == FTYPE_DBL || format == FTYPE_SNG || 190 format == FTYPE_EXT) { 191 fpu_explode(fe, &fe->fe_f2, format, buf); 192 fpu_implode(fe, &fe->fe_f2, FTYPE_LNG, buf); 193 scale = buf[0]; 194 } 195 /* make it look like we've got an FP oprand */ 196 fe->fe_f2.fp_class = (buf[0] == 0) ? FPC_ZERO : FPC_NUM; 197 } 198 199 /* assume there's no exception */ 200 sig = 0; 201 202 /* 203 * it's barbaric but we're going to operate directly on 204 * the dst operand's bit pattern 205 */ 206 sign = fpregs[regnum * 3] & 0x80000000; 207 exp = (fpregs[regnum * 3] & 0x7fff0000) >> 16; 208 m0 = fpregs[regnum * 3 + 1]; 209 m1 = fpregs[regnum * 3 + 2]; 210 211 switch (fe->fe_f2.fp_class) { 212 case FPC_SNAN: 213 fpsr |= FPSR_SNAN; 214 case FPC_QNAN: 215 /* dst = NaN */ 216 exp = 0x7fff; 217 m0 = m1 = 0xffffffff; 218 break; 219 case FPC_ZERO: 220 case FPC_NUM: 221 if ((0 < exp && exp < 0x7fff) || 222 (exp == 0 && (m0 | m1) != 0)) { 223 /* normal or denormal */ 224 exp += scale; 225 if (exp < 0) { 226 /* underflow */ 227 uint32_t grs; /* guard, round and sticky */ 228 229 exp = 0; 230 grs = m1 << (32 + exp); 231 m1 = m0 << (32 + exp) | m1 >> -exp; 232 m0 >>= -exp; 233 if (grs != 0) { 234 fpsr |= FPSR_INEX2; 235 236 switch (fe->fe_fpcr & 0x30) { 237 case FPCR_MINF: 238 if (sign != 0) { 239 if (++m1 == 0 && 240 ++m0 == 0) { 241 m0 = 0x80000000; 242 exp++; 243 } 244 } 245 break; 246 case FPCR_NEAR: 247 if (grs == 0x80000000) { 248 /* tie */ 249 if ((m1 & 1) && 250 ++m1 == 0 && 251 ++m0 == 0) { 252 m0 = 0x80000000; 253 exp++; 254 } 255 } else if (grs & 0x80000000) { 256 if (++m1 == 0 && 257 ++m0 == 0) { 258 m0 = 0x80000000; 259 exp++; 260 } 261 } 262 break; 263 case FPCR_PINF: 264 if (sign == 0) { 265 if (++m1 == 0 && 266 ++m0 == 0) { 267 m0 = 0x80000000; 268 exp++; 269 } 270 } 271 break; 272 case FPCR_ZERO: 273 break; 274 } 275 } 276 if (exp == 0 && (m0 & 0x80000000) == 0) { 277 fpsr |= FPSR_UNFL; 278 if ((m0 | m1) == 0) { 279 fpsr |= FPSR_ZERO; 280 } 281 } 282 } else if (exp >= 0x7fff) { 283 /* overflow --> result = Inf */ 284 /* 285 * but first, try to normalize in case it's an 286 * unnormalized 287 */ 288 while ((m0 & 0x80000000) == 0) { 289 exp--; 290 m0 = (m0 << 1) | (m1 >> 31); 291 m1 = m1 << 1; 292 } 293 /* if it's still too large, then return Inf */ 294 if (exp >= 0x7fff) { 295 exp = 0x7fff; 296 m0 = m1 = 0; 297 fpsr |= FPSR_OVFL | FPSR_INF; 298 } 299 } else if ((m0 & 0x80000000) == 0) { 300 /* 301 * it's a denormal; we try to normalize but 302 * result may and may not be a normal. 303 */ 304 while (exp > 0 && (m0 & 0x80000000) == 0) { 305 exp--; 306 m0 = (m0 << 1) | (m1 >> 31); 307 m1 = m1 << 1; 308 } 309 if ((m0 & 0x80000000) == 0) { 310 fpsr |= FPSR_UNFL; 311 } 312 } /* exp in range and mantissa normalized */ 313 } else if (exp == 0 && m0 == 0 && m1 == 0) { 314 /* dst is Zero */ 315 fpsr |= FPSR_ZERO; 316 } /* else we know exp == 0x7fff */ 317 else if ((m0 | m1) == 0) { 318 fpsr |= FPSR_INF; 319 } else if ((m0 & 0x40000000) == 0) { 320 /* a signaling NaN */ 321 fpsr |= FPSR_NAN | FPSR_SNAN; 322 } else { 323 /* a quiet NaN */ 324 fpsr |= FPSR_NAN; 325 } 326 break; 327 case FPC_INF: 328 /* dst = NaN */ 329 exp = 0x7fff; 330 m0 = m1 = 0xffffffff; 331 fpsr |= FPSR_OPERR | FPSR_NAN; 332 break; 333 default: 334 #ifdef DEBUG 335 panic("fpu_emul_fscale: invalid fp class"); 336 #endif 337 break; 338 } 339 340 /* store the result */ 341 fpregs[regnum * 3] = sign | (exp << 16); 342 fpregs[regnum * 3 + 1] = m0; 343 fpregs[regnum * 3 + 2] = m1; 344 345 if (sign) { 346 fpsr |= FPSR_NEG; 347 } 348 349 /* update fpsr according to the result of operation */ 350 fe->fe_fpframe->fpf_fpsr = fe->fe_fpsr = fpsr; 351 352 #if DEBUG_FPE 353 printf("fpu_emul_fscale: FPSR = %08x, FPCR = %08x\n", 354 fe->fe_fpsr, fe->fe_fpcr); 355 #endif 356 357 return (fpsr & fe->fe_fpcr & FPSR_EXCP) ? SIGFPE : sig; 358 } 359
Indexes created Tue Sep 30 20:09:53 GMT 2025