fpu_fscale.c revision 1.2
1 /* $NetBSD: fpu_fscale.c,v 1.2 1995/11/05 00:35:25 briggs Exp $ */ 2 3 /* 4 * Copyright (c) 1995 Ken Nakata 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 4. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Gordon Ross 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * FSCALE - separated from the other type0 arithmetic instructions 35 * for performance reason; maybe unnecessary, but FSCALE assumes 36 * the source operand be an integer. It performs type conversion 37 * only if the source operand is *not* an integer. 38 */ 39 40 #include <sys/types.h> 41 #include <sys/signal.h> 42 #include <machine/frame.h> 43 44 #include "fpu_emulate.h" 45 46 int 47 fpu_emul_fscale(fe, insn) 48 struct fpemu *fe; 49 struct instruction *insn; 50 { 51 struct frame *frame; 52 u_int *fpregs; 53 int word1, sig; 54 int regnum, format; 55 int scale, sign, exp; 56 u_int m0, m1; 57 u_int buf[3], fpsr; 58 int flags; 59 char regname; 60 61 sig = 0; 62 frame = fe->fe_frame; 63 fpregs = &(fe->fe_fpframe->fpf_regs[0]); 64 /* clear all exceptions and conditions */ 65 fpsr = fe->fe_fpsr & ~FPSR_EXCP & ~FPSR_CCB; 66 if (fpu_debug_level & DL_FSCALE) { 67 printf(" fpu_emul_fscale: FPSR = %08x, FPCR = %08x\n", fpsr, fe->fe_fpcr); 68 } 69 70 word1 = insn->is_word1; 71 format = (word1 >> 10) & 7; 72 regnum = (word1 >> 7) & 7; 73 74 fe->fe_fpcr &= FPCR_ROUND; 75 fe->fe_fpcr |= FPCR_ZERO; 76 77 /* get the source operand */ 78 if ((word1 & 0x4000) == 0) { 79 if (fpu_debug_level & DL_FSCALE) { 80 printf(" fpu_emul_fscale: FP%d op FP%d => FP%d\n", 81 format, regnum, regnum); 82 } 83 /* the operand is an FP reg */ 84 if (fpu_debug_level & DL_FSCALE) { 85 printf(" fpu_emul_scale: src opr FP%d=%08x%08x%08x\n", 86 format, fpregs[format*3], fpregs[format*3+1], 87 fpregs[format*3+2]); 88 } 89 fpu_explode(fe, &fe->fe_f2, FTYPE_EXT, &fpregs[format * 3]); 90 fpu_implode(fe, &fe->fe_f2, FTYPE_LNG, buf); 91 } else { 92 /* the operand is in memory */ 93 if (format == FTYPE_DBL) { 94 insn->is_datasize = 8; 95 } else if (format == FTYPE_SNG || format == FTYPE_LNG) { 96 insn->is_datasize = 4; 97 } else if (format == FTYPE_WRD) { 98 insn->is_datasize = 2; 99 } else if (format == FTYPE_BYT) { 100 insn->is_datasize = 1; 101 } else if (format == FTYPE_EXT) { 102 insn->is_datasize = 12; 103 } else { 104 /* invalid or unsupported operand format */ 105 sig = SIGFPE; 106 return sig; 107 } 108 109 /* Get effective address. (modreg=opcode&077) */ 110 sig = fpu_decode_ea(frame, insn, &insn->is_ea0, insn->is_opcode); 111 if (sig) { 112 if (fpu_debug_level & DL_FSCALE) { 113 printf(" fpu_emul_fscale: error in decode_ea\n"); 114 } 115 return sig; 116 } 117 118 if (fpu_debug_level & DL_FSCALE) { 119 printf(" fpu_emul_fscale: addr mode = "); 120 flags = insn->is_ea0.ea_flags; 121 regname = (insn->is_ea0.ea_regnum & 8) ? 'a' : 'd'; 122 123 if (flags & EA_DIRECT) { 124 printf("%c%d\n", regname, insn->is_ea0.ea_regnum & 7); 125 } else if (insn->is_ea0.ea_flags & EA_PREDECR) { 126 printf("%c%d@-\n", regname, insn->is_ea0.ea_regnum & 7); 127 } else if (insn->is_ea0.ea_flags & EA_POSTINCR) { 128 printf("%c%d@+\n", regname, insn->is_ea0.ea_regnum & 7); 129 } else if (insn->is_ea0.ea_flags & EA_OFFSET) { 130 printf("%c%d@(%d)\n", regname, insn->is_ea0.ea_regnum & 7, 131 insn->is_ea0.ea_offset); 132 } else if (insn->is_ea0.ea_flags & EA_INDEXED) { 133 printf("%c%d@(...)\n", regname, insn->is_ea0.ea_regnum & 7); 134 } else if (insn->is_ea0.ea_flags & EA_ABS) { 135 printf("0x%08x\n", insn->is_ea0.ea_absaddr); 136 } else if (insn->is_ea0.ea_flags & EA_PC_REL) { 137 printf("pc@(%d)\n", insn->is_ea0.ea_offset); 138 } else if (flags & EA_IMMED) { 139 printf("#0x%08x%08x%08x\n", 140 insn->is_ea0.ea_immed[0], insn->is_ea0.ea_immed[1], 141 insn->is_ea0.ea_immed[2]); 142 } else { 143 printf("%c%d@\n", regname, insn->is_ea0.ea_regnum & 7); 144 } 145 } 146 fpu_load_ea(frame, insn, &insn->is_ea0, (char*)buf); 147 148 if (fpu_debug_level & DL_FSCALE) { 149 printf(" fpu_emul_fscale: src = %08x%08x%08x, siz = %d\n", 150 buf[0], buf[1], buf[2], insn->is_datasize); 151 } 152 if (format == FTYPE_LNG) { 153 /* nothing */ 154 } else if (format == FTYPE_WRD) { 155 /* sign-extend */ 156 scale = buf[0] & 0xffff; 157 if (scale & 0x8000) { 158 scale |= 0xffff0000; 159 } 160 } else if (format == FTYPE_BYT) { 161 /* sign-extend */ 162 scale = buf[0] & 0xff; 163 if (scale & 0x80) { 164 scale |= 0xffffff00; 165 } 166 } else if (format == FTYPE_DBL || format == FTYPE_SNG || 167 format == FTYPE_EXT) { 168 fpu_explode(fe, &fe->fe_f2, format, buf); 169 fpu_implode(fe, &fe->fe_f2, FTYPE_LNG, buf); 170 } 171 /* make it look like we've got an FP oprand */ 172 fe->fe_f2.fp_class = (buf[0] == 0) ? FPC_ZERO : FPC_NUM; 173 } 174 175 /* assume there's no exception */ 176 sig = 0; 177 178 /* it's barbaric but we're going to operate directly on 179 * the dst operand's bit pattern */ 180 sign = fpregs[regnum * 3] & 0x80000000; 181 exp = (fpregs[regnum * 3] & 0x7fff0000) >> 16; 182 m0 = fpregs[regnum * 3 + 1]; 183 m1 = fpregs[regnum * 3 + 2]; 184 185 switch (fe->fe_f2.fp_class) { 186 case FPC_SNAN: 187 fpsr |= FPSR_SNAN; 188 case FPC_QNAN: 189 /* dst = NaN */ 190 exp = 0x7fff; 191 m0 = m1 = 0xffffffff; 192 break; 193 case FPC_ZERO: 194 case FPC_NUM: 195 if ((0 < exp && exp < 0x7fff) || 196 (exp == 0 && (m0 | m1) != 0)) { 197 /* normal or denormal */ 198 exp += scale; 199 if (exp < 0) { 200 /* underflow */ 201 u_int grs; /* guard, round and sticky */ 202 203 exp = 0; 204 grs = m1 << (32 + exp); 205 m1 = m0 << (32 + exp) | m1 >> -exp; 206 m0 >>= -exp; 207 if (grs != 0) { 208 fpsr |= FPSR_INEX2; 209 210 switch (fe->fe_fpcr & 0x30) { 211 case FPCR_MINF: 212 if (sign != 0) { 213 if (++m1 == 0 && 214 ++m0 == 0) { 215 m0 = 0x80000000; 216 exp++; 217 } 218 } 219 break; 220 case FPCR_NEAR: 221 if (grs == 0x80000000) { 222 /* tie */ 223 if ((m1 & 1) && 224 ++m1 == 0 && 225 ++m0 == 0) { 226 m0 = 0x80000000; 227 exp++; 228 } 229 } else if (grs & 0x80000000) { 230 if (++m1 == 0 && 231 ++m0 == 0) { 232 m0 = 0x80000000; 233 exp++; 234 } 235 } 236 break; 237 case FPCR_PINF: 238 if (sign == 0) { 239 if (++m1 == 0 && 240 ++m0 == 0) { 241 m0 = 0x80000000; 242 exp++; 243 } 244 } 245 break; 246 case FPCR_ZERO: 247 break; 248 } 249 } 250 if (exp == 0 && (m0 & 0x80000000) == 0) { 251 fpsr |= FPSR_UNFL; 252 if ((m0 | m1) == 0) { 253 fpsr |= FPSR_ZERO; 254 } 255 } 256 } else if (exp >= 0x7fff) { 257 /* overflow --> result = Inf */ 258 /* but first, try to normalize in case it's an unnormalized */ 259 while ((m0 & 0x80000000) == 0) { 260 exp--; 261 m0 = (m0 << 1) | (m1 >> 31); 262 m1 = m1 << 1; 263 } 264 /* if it's still too large, then return Inf */ 265 if (exp >= 0x7fff) { 266 exp = 0x7fff; 267 m0 = m1 = 0; 268 fpsr |= FPSR_OVFL | FPSR_INF; 269 } 270 } else if ((m0 & 0x80000000) == 0) { 271 /* 272 * it's a denormal; we try to normalize but 273 * result may and may not be a normal. 274 */ 275 while (exp > 0 && (m0 & 0x80000000) == 0) { 276 exp--; 277 m0 = (m0 << 1) | (m1 >> 31); 278 m1 = m1 << 1; 279 } 280 if ((m0 & 0x80000000) == 0) { 281 fpsr |= FPSR_UNFL; 282 } 283 } /* exp in range and mantissa normalized */ 284 } else if (exp == 0 && m0 == 0 && m1 == 0) { 285 /* dst is Zero */ 286 fpsr |= FPSR_ZERO; 287 } /* else we know exp == 0x7fff */ 288 else if ((m0 | m1) == 0) { 289 fpsr |= FPSR_INF; 290 } else if ((m0 & 0x40000000) == 0) { 291 /* a signaling NaN */ 292 fpsr |= FPSR_NAN | FPSR_SNAN; 293 } else { 294 /* a quiet NaN */ 295 fpsr |= FPSR_NAN; 296 } 297 break; 298 case FPC_INF: 299 /* dst = NaN */ 300 exp = 0x7fff; 301 m0 = m1 = 0xffffffff; 302 fpsr |= FPSR_OPERR | FPSR_NAN; 303 break; 304 default: 305 #ifdef DEBUG 306 panic(" fpu_emul_fscale: invalid fp class"); 307 #endif 308 break; 309 } 310 311 /* store the result */ 312 fpregs[regnum * 3] = sign | (exp << 16); 313 fpregs[regnum * 3 + 1] = m0; 314 fpregs[regnum * 3 + 2] = m1; 315 316 if (sign) { 317 fpsr |= FPSR_NEG; 318 } 319 320 /* update fpsr according to the result of operation */ 321 fe->fe_fpframe->fpf_fpsr = fe->fe_fpsr = fpsr; 322 323 if (fpu_debug_level & DL_FSCALE) { 324 printf(" fpu_emul_fscale: FPSR = %08x, FPCR = %08x\n", 325 fe->fe_fpsr, fe->fe_fpcr); 326 } 327 328 return (fpsr & fe->fe_fpcr & FPSR_EXCP) ? SIGFPE : sig; 329 } 330
Indexes created Tue Sep 30 11:09:46 GMT 2025