fpu_fscale.c revision 1.4
1 /* $NetBSD: fpu_fscale.c,v 1.4 1996/05/15 07:31:57 leo Exp $ */ 2 3 /* 4 * Copyright (c) 1995 Ken Nakata 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 4. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Gordon Ross 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * FSCALE - separated from the other type0 arithmetic instructions 35 * for performance reason; maybe unnecessary, but FSCALE assumes 36 * the source operand be an integer. It performs type conversion 37 * only if the source operand is *not* an integer. 38 */ 39 40 #include <sys/types.h> 41 #include <sys/signal.h> 42 #include <sys/systm.h> 43 #include <machine/frame.h> 44 45 #include "fpu_emulate.h" 46 47 int 48 fpu_emul_fscale(fe, insn) 49 struct fpemu *fe; 50 struct instruction *insn; 51 { 52 struct frame *frame; 53 u_int *fpregs; 54 int word1, sig; 55 int regnum, format; 56 int scale, sign, exp; 57 u_int m0, m1; 58 u_int buf[3], fpsr; 59 int flags; 60 char regname; 61 62 scale = sig = 0; 63 frame = fe->fe_frame; 64 fpregs = &(fe->fe_fpframe->fpf_regs[0]); 65 /* clear all exceptions and conditions */ 66 fpsr = fe->fe_fpsr & ~FPSR_EXCP & ~FPSR_CCB; 67 if (fpu_debug_level & DL_FSCALE) { 68 printf(" fpu_emul_fscale: FPSR = %08x, FPCR = %08x\n", fpsr, fe->fe_fpcr); 69 } 70 71 word1 = insn->is_word1; 72 format = (word1 >> 10) & 7; 73 regnum = (word1 >> 7) & 7; 74 75 fe->fe_fpcr &= FPCR_ROUND; 76 fe->fe_fpcr |= FPCR_ZERO; 77 78 /* get the source operand */ 79 if ((word1 & 0x4000) == 0) { 80 if (fpu_debug_level & DL_FSCALE) { 81 printf(" fpu_emul_fscale: FP%d op FP%d => FP%d\n", 82 format, regnum, regnum); 83 } 84 /* the operand is an FP reg */ 85 if (fpu_debug_level & DL_FSCALE) { 86 printf(" fpu_emul_scale: src opr FP%d=%08x%08x%08x\n", 87 format, fpregs[format*3], fpregs[format*3+1], 88 fpregs[format*3+2]); 89 } 90 fpu_explode(fe, &fe->fe_f2, FTYPE_EXT, &fpregs[format * 3]); 91 fpu_implode(fe, &fe->fe_f2, FTYPE_LNG, buf); 92 } else { 93 /* the operand is in memory */ 94 if (format == FTYPE_DBL) { 95 insn->is_datasize = 8; 96 } else if (format == FTYPE_SNG || format == FTYPE_LNG) { 97 insn->is_datasize = 4; 98 } else if (format == FTYPE_WRD) { 99 insn->is_datasize = 2; 100 } else if (format == FTYPE_BYT) { 101 insn->is_datasize = 1; 102 } else if (format == FTYPE_EXT) { 103 insn->is_datasize = 12; 104 } else { 105 /* invalid or unsupported operand format */ 106 sig = SIGFPE; 107 return sig; 108 } 109 110 /* Get effective address. (modreg=opcode&077) */ 111 sig = fpu_decode_ea(frame, insn, &insn->is_ea0, insn->is_opcode); 112 if (sig) { 113 if (fpu_debug_level & DL_FSCALE) { 114 printf(" fpu_emul_fscale: error in decode_ea\n"); 115 } 116 return sig; 117 } 118 119 if (fpu_debug_level & DL_FSCALE) { 120 printf(" fpu_emul_fscale: addr mode = "); 121 flags = insn->is_ea0.ea_flags; 122 regname = (insn->is_ea0.ea_regnum & 8) ? 'a' : 'd'; 123 124 if (flags & EA_DIRECT) { 125 printf("%c%d\n", regname, insn->is_ea0.ea_regnum & 7); 126 } else if (insn->is_ea0.ea_flags & EA_PREDECR) { 127 printf("%c%d@-\n", regname, insn->is_ea0.ea_regnum & 7); 128 } else if (insn->is_ea0.ea_flags & EA_POSTINCR) { 129 printf("%c%d@+\n", regname, insn->is_ea0.ea_regnum & 7); 130 } else if (insn->is_ea0.ea_flags & EA_OFFSET) { 131 printf("%c%d@(%d)\n", regname, insn->is_ea0.ea_regnum & 7, 132 insn->is_ea0.ea_offset); 133 } else if (insn->is_ea0.ea_flags & EA_INDEXED) { 134 printf("%c%d@(...)\n", regname, insn->is_ea0.ea_regnum & 7); 135 } else if (insn->is_ea0.ea_flags & EA_ABS) { 136 printf("0x%08x\n", insn->is_ea0.ea_absaddr); 137 } else if (insn->is_ea0.ea_flags & EA_PC_REL) { 138 printf("pc@(%d)\n", insn->is_ea0.ea_offset); 139 } else if (flags & EA_IMMED) { 140 printf("#0x%08x%08x%08x\n", 141 insn->is_ea0.ea_immed[0], insn->is_ea0.ea_immed[1], 142 insn->is_ea0.ea_immed[2]); 143 } else { 144 printf("%c%d@\n", regname, insn->is_ea0.ea_regnum & 7); 145 } 146 } 147 fpu_load_ea(frame, insn, &insn->is_ea0, (char*)buf); 148 149 if (fpu_debug_level & DL_FSCALE) { 150 printf(" fpu_emul_fscale: src = %08x%08x%08x, siz = %d\n", 151 buf[0], buf[1], buf[2], insn->is_datasize); 152 } 153 if (format == FTYPE_LNG) { 154 /* nothing */ 155 } else if (format == FTYPE_WRD) { 156 /* sign-extend */ 157 scale = buf[0] & 0xffff; 158 if (scale & 0x8000) { 159 scale |= 0xffff0000; 160 } 161 } else if (format == FTYPE_BYT) { 162 /* sign-extend */ 163 scale = buf[0] & 0xff; 164 if (scale & 0x80) { 165 scale |= 0xffffff00; 166 } 167 } else if (format == FTYPE_DBL || format == FTYPE_SNG || 168 format == FTYPE_EXT) { 169 fpu_explode(fe, &fe->fe_f2, format, buf); 170 fpu_implode(fe, &fe->fe_f2, FTYPE_LNG, buf); 171 } 172 /* make it look like we've got an FP oprand */ 173 fe->fe_f2.fp_class = (buf[0] == 0) ? FPC_ZERO : FPC_NUM; 174 } 175 176 /* assume there's no exception */ 177 sig = 0; 178 179 /* it's barbaric but we're going to operate directly on 180 * the dst operand's bit pattern */ 181 sign = fpregs[regnum * 3] & 0x80000000; 182 exp = (fpregs[regnum * 3] & 0x7fff0000) >> 16; 183 m0 = fpregs[regnum * 3 + 1]; 184 m1 = fpregs[regnum * 3 + 2]; 185 186 switch (fe->fe_f2.fp_class) { 187 case FPC_SNAN: 188 fpsr |= FPSR_SNAN; 189 case FPC_QNAN: 190 /* dst = NaN */ 191 exp = 0x7fff; 192 m0 = m1 = 0xffffffff; 193 break; 194 case FPC_ZERO: 195 case FPC_NUM: 196 if ((0 < exp && exp < 0x7fff) || 197 (exp == 0 && (m0 | m1) != 0)) { 198 /* normal or denormal */ 199 exp += scale; 200 if (exp < 0) { 201 /* underflow */ 202 u_int grs; /* guard, round and sticky */ 203 204 exp = 0; 205 grs = m1 << (32 + exp); 206 m1 = m0 << (32 + exp) | m1 >> -exp; 207 m0 >>= -exp; 208 if (grs != 0) { 209 fpsr |= FPSR_INEX2; 210 211 switch (fe->fe_fpcr & 0x30) { 212 case FPCR_MINF: 213 if (sign != 0) { 214 if (++m1 == 0 && 215 ++m0 == 0) { 216 m0 = 0x80000000; 217 exp++; 218 } 219 } 220 break; 221 case FPCR_NEAR: 222 if (grs == 0x80000000) { 223 /* tie */ 224 if ((m1 & 1) && 225 ++m1 == 0 && 226 ++m0 == 0) { 227 m0 = 0x80000000; 228 exp++; 229 } 230 } else if (grs & 0x80000000) { 231 if (++m1 == 0 && 232 ++m0 == 0) { 233 m0 = 0x80000000; 234 exp++; 235 } 236 } 237 break; 238 case FPCR_PINF: 239 if (sign == 0) { 240 if (++m1 == 0 && 241 ++m0 == 0) { 242 m0 = 0x80000000; 243 exp++; 244 } 245 } 246 break; 247 case FPCR_ZERO: 248 break; 249 } 250 } 251 if (exp == 0 && (m0 & 0x80000000) == 0) { 252 fpsr |= FPSR_UNFL; 253 if ((m0 | m1) == 0) { 254 fpsr |= FPSR_ZERO; 255 } 256 } 257 } else if (exp >= 0x7fff) { 258 /* overflow --> result = Inf */ 259 /* but first, try to normalize in case it's an unnormalized */ 260 while ((m0 & 0x80000000) == 0) { 261 exp--; 262 m0 = (m0 << 1) | (m1 >> 31); 263 m1 = m1 << 1; 264 } 265 /* if it's still too large, then return Inf */ 266 if (exp >= 0x7fff) { 267 exp = 0x7fff; 268 m0 = m1 = 0; 269 fpsr |= FPSR_OVFL | FPSR_INF; 270 } 271 } else if ((m0 & 0x80000000) == 0) { 272 /* 273 * it's a denormal; we try to normalize but 274 * result may and may not be a normal. 275 */ 276 while (exp > 0 && (m0 & 0x80000000) == 0) { 277 exp--; 278 m0 = (m0 << 1) | (m1 >> 31); 279 m1 = m1 << 1; 280 } 281 if ((m0 & 0x80000000) == 0) { 282 fpsr |= FPSR_UNFL; 283 } 284 } /* exp in range and mantissa normalized */ 285 } else if (exp == 0 && m0 == 0 && m1 == 0) { 286 /* dst is Zero */ 287 fpsr |= FPSR_ZERO; 288 } /* else we know exp == 0x7fff */ 289 else if ((m0 | m1) == 0) { 290 fpsr |= FPSR_INF; 291 } else if ((m0 & 0x40000000) == 0) { 292 /* a signaling NaN */ 293 fpsr |= FPSR_NAN | FPSR_SNAN; 294 } else { 295 /* a quiet NaN */ 296 fpsr |= FPSR_NAN; 297 } 298 break; 299 case FPC_INF: 300 /* dst = NaN */ 301 exp = 0x7fff; 302 m0 = m1 = 0xffffffff; 303 fpsr |= FPSR_OPERR | FPSR_NAN; 304 break; 305 default: 306 #ifdef DEBUG 307 panic(" fpu_emul_fscale: invalid fp class"); 308 #endif 309 break; 310 } 311 312 /* store the result */ 313 fpregs[regnum * 3] = sign | (exp << 16); 314 fpregs[regnum * 3 + 1] = m0; 315 fpregs[regnum * 3 + 2] = m1; 316 317 if (sign) { 318 fpsr |= FPSR_NEG; 319 } 320 321 /* update fpsr according to the result of operation */ 322 fe->fe_fpframe->fpf_fpsr = fe->fe_fpsr = fpsr; 323 324 if (fpu_debug_level & DL_FSCALE) { 325 printf(" fpu_emul_fscale: FPSR = %08x, FPCR = %08x\n", 326 fe->fe_fpsr, fe->fe_fpcr); 327 } 328 329 return (fpsr & fe->fe_fpcr & FPSR_EXCP) ? SIGFPE : sig; 330 } 331
Indexes created Tue Sep 30 11:09:46 GMT 2025