fpu_fstore.c revision 1.16 1 1.16 isaki /* $NetBSD: fpu_fstore.c,v 1.16 2025/01/03 05:54:07 isaki Exp $ */
2 1.1 briggs
3 1.1 briggs /*
4 1.1 briggs * Copyright (c) 1995 Ken Nakata
5 1.1 briggs * All rights reserved.
6 1.1 briggs *
7 1.1 briggs * Redistribution and use in source and binary forms, with or without
8 1.1 briggs * modification, are permitted provided that the following conditions
9 1.1 briggs * are met:
10 1.1 briggs * 1. Redistributions of source code must retain the above copyright
11 1.1 briggs * notice, this list of conditions and the following disclaimer.
12 1.1 briggs * 2. Redistributions in binary form must reproduce the above copyright
13 1.1 briggs * notice, this list of conditions and the following disclaimer in the
14 1.1 briggs * documentation and/or other materials provided with the distribution.
15 1.1 briggs *
16 1.1 briggs * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 1.1 briggs * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 1.1 briggs * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 1.1 briggs * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 1.1 briggs * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 1.1 briggs * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22 1.1 briggs * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23 1.1 briggs * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 1.1 briggs * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 1.1 briggs * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 1.1 briggs */
27 1.8 lukem
28 1.8 lukem #include <sys/cdefs.h>
29 1.16 isaki __KERNEL_RCSID(0, "$NetBSD: fpu_fstore.c,v 1.16 2025/01/03 05:54:07 isaki Exp $");
30 1.1 briggs
31 1.1 briggs #include <sys/types.h>
32 1.1 briggs #include <sys/signal.h>
33 1.3 briggs #include <sys/systm.h>
34 1.1 briggs #include <machine/frame.h>
35 1.1 briggs
36 1.1 briggs #include "fpu_emulate.h"
37 1.1 briggs
38 1.1 briggs /*
39 1.1 briggs * type 0: fmove mem/fpr->fpr
40 1.1 briggs * In this function, we know
41 1.1 briggs * (opcode & 0x01c0) == 0
42 1.1 briggs * (word1 & 0xe000) == 0x6000
43 1.1 briggs */
44 1.1 briggs int
45 1.11 dsl fpu_emul_fstore(struct fpemu *fe, struct instruction *insn)
46 1.1 briggs {
47 1.12 isaki struct frame *frame = fe->fe_frame;
48 1.14 isaki uint32_t *fpregs = fe->fe_fpframe->fpf_regs;
49 1.12 isaki int word1, sig;
50 1.12 isaki int regnum;
51 1.12 isaki int format;
52 1.16 isaki int modreg;
53 1.14 isaki uint32_t buf[3];
54 1.1 briggs
55 1.7 briggs #if DEBUG_FPE
56 1.12 isaki printf(" fpu_emul_fstore: frame at %p fpframe at %p\n",
57 1.13 isaki frame, fe->fe_fpframe);
58 1.7 briggs #endif
59 1.1 briggs
60 1.12 isaki word1 = insn->is_word1;
61 1.12 isaki format = (word1 >> 10) & 7;
62 1.12 isaki regnum = (word1 >> 7) & 7;
63 1.1 briggs
64 1.12 isaki insn->is_advance = 4;
65 1.1 briggs
66 1.12 isaki if (format == FTYPE_DBL) {
67 1.12 isaki insn->is_datasize = 8;
68 1.12 isaki } else if (format == FTYPE_SNG || format == FTYPE_LNG) {
69 1.12 isaki insn->is_datasize = 4;
70 1.12 isaki } else if (format == FTYPE_WRD) {
71 1.12 isaki insn->is_datasize = 2;
72 1.12 isaki format = FTYPE_LNG;
73 1.12 isaki } else if (format == FTYPE_BYT) {
74 1.12 isaki insn->is_datasize = 1;
75 1.12 isaki format = FTYPE_LNG;
76 1.12 isaki } else if (format == FTYPE_EXT) {
77 1.12 isaki insn->is_datasize = 12;
78 1.12 isaki } else {
79 1.12 isaki /* invalid or unsupported operand format */
80 1.7 briggs #if DEBUG_FPE
81 1.12 isaki printf(" fpu_emul_fstore: invalid format %d\n", format);
82 1.7 briggs #endif
83 1.15 isaki return SIGFPE;
84 1.12 isaki }
85 1.7 briggs #if DEBUG_FPE
86 1.12 isaki printf(" fpu_emul_fstore: format %d, size %d\n",
87 1.13 isaki format, insn->is_datasize);
88 1.7 briggs #endif
89 1.6 is
90 1.12 isaki fe->fe_fpsr &= ~FPSR_EXCP;
91 1.1 briggs
92 1.16 isaki /* Check an illegal mod/reg */
93 1.16 isaki modreg = insn->is_opcode & 077;
94 1.16 isaki if ((modreg >> 3) == 1/*An*/ || modreg >= 072/*PCrel and #imm*/) {
95 1.16 isaki #if DEBUG_FPE
96 1.16 isaki printf(" fpu_emul_fstore: illegal modreg=0%o\n", modreg);
97 1.16 isaki #endif
98 1.16 isaki return SIGILL;
99 1.16 isaki }
100 1.16 isaki
101 1.16 isaki /* Get effective address. */
102 1.16 isaki sig = fpu_decode_ea(frame, insn, &insn->is_ea, modreg);
103 1.12 isaki if (sig) {
104 1.7 briggs #if DEBUG_FPE
105 1.12 isaki printf(" fpu_emul_fstore: failed in decode_ea sig=%d\n", sig);
106 1.7 briggs #endif
107 1.12 isaki return sig;
108 1.12 isaki }
109 1.1 briggs
110 1.12 isaki if (insn->is_datasize > 4 && insn->is_ea.ea_flags == EA_DIRECT) {
111 1.12 isaki /* trying to store dbl or ext into a data register */
112 1.1 briggs #ifdef DEBUG
113 1.12 isaki printf(" fpu_fstore: attempted to store dbl/ext to reg\n");
114 1.1 briggs #endif
115 1.12 isaki return SIGILL;
116 1.12 isaki }
117 1.1 briggs
118 1.7 briggs #if DEBUG_FPE
119 1.12 isaki printf(" fpu_emul_fstore: saving FP%d (%08x,%08x,%08x)\n",
120 1.13 isaki regnum, fpregs[regnum * 3], fpregs[regnum * 3 + 1],
121 1.13 isaki fpregs[regnum * 3 + 2]);
122 1.7 briggs #endif
123 1.12 isaki fpu_explode(fe, &fe->fe_f3, FTYPE_EXT, &fpregs[regnum * 3]);
124 1.7 briggs #if DEBUG_FPE
125 1.12 isaki {
126 1.10 tsutsui static const char *class_name[] =
127 1.13 isaki { "SNAN", "QNAN", "ZERO", "NUM", "INF" };
128 1.7 briggs printf(" fpu_emul_fstore: fpn (%s,%c,%d,%08x,%08x,%08x)\n",
129 1.13 isaki class_name[fe->fe_f3.fp_class + 2],
130 1.13 isaki fe->fe_f3.fp_sign ? '-' : '+', fe->fe_f3.fp_exp,
131 1.13 isaki fe->fe_f3.fp_mant[0], fe->fe_f3.fp_mant[1],
132 1.13 isaki fe->fe_f3.fp_mant[2]);
133 1.12 isaki }
134 1.7 briggs #endif
135 1.12 isaki fpu_implode(fe, &fe->fe_f3, format, buf);
136 1.1 briggs
137 1.12 isaki fpu_store_ea(frame, insn, &insn->is_ea, (char *)buf);
138 1.7 briggs #if DEBUG_FPE
139 1.12 isaki printf(" fpu_emul_fstore: %08x,%08x,%08x size %d\n",
140 1.13 isaki buf[0], buf[1], buf[2], insn->is_datasize);
141 1.7 briggs #endif
142 1.1 briggs
143 1.12 isaki return 0;
144 1.1 briggs }
145