fpu_fstore.c revision 1.2 1 1.2 briggs /* $NetBSD: fpu_fstore.c,v 1.2 1995/11/05 00:35:29 briggs Exp $ */
2 1.1 briggs
3 1.1 briggs /*
4 1.1 briggs * Copyright (c) 1995 Ken Nakata
5 1.1 briggs * All rights reserved.
6 1.1 briggs *
7 1.1 briggs * Redistribution and use in source and binary forms, with or without
8 1.1 briggs * modification, are permitted provided that the following conditions
9 1.1 briggs * are met:
10 1.1 briggs * 1. Redistributions of source code must retain the above copyright
11 1.1 briggs * notice, this list of conditions and the following disclaimer.
12 1.1 briggs * 2. Redistributions in binary form must reproduce the above copyright
13 1.1 briggs * notice, this list of conditions and the following disclaimer in the
14 1.1 briggs * documentation and/or other materials provided with the distribution.
15 1.1 briggs *
16 1.1 briggs * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 1.1 briggs * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 1.1 briggs * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 1.1 briggs * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 1.1 briggs * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 1.1 briggs * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22 1.1 briggs * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23 1.1 briggs * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 1.1 briggs * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 1.1 briggs * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 1.1 briggs */
27 1.1 briggs
28 1.1 briggs #include <sys/types.h>
29 1.1 briggs #include <sys/signal.h>
30 1.1 briggs #include <machine/frame.h>
31 1.1 briggs
32 1.1 briggs #include "fpu_emulate.h"
33 1.1 briggs
34 1.1 briggs /*
35 1.1 briggs * type 0: fmove mem/fpr->fpr
36 1.1 briggs * In this function, we know
37 1.1 briggs * (opcode & 0x01c0) == 0
38 1.1 briggs * (word1 & 0xe000) == 0x6000
39 1.1 briggs */
40 1.1 briggs int
41 1.1 briggs fpu_emul_fstore(fe, insn)
42 1.1 briggs struct fpemu *fe;
43 1.1 briggs struct instruction *insn;
44 1.1 briggs {
45 1.1 briggs struct frame *frame = fe->fe_frame;
46 1.1 briggs u_int *fpregs = fe->fe_fpframe->fpf_regs;
47 1.1 briggs int word1, sig;
48 1.1 briggs int regnum;
49 1.1 briggs int format;
50 1.1 briggs u_int buf[3];
51 1.1 briggs u_int flags;
52 1.1 briggs char regname;
53 1.1 briggs
54 1.2 briggs if (fpu_debug_level & DL_FSTORE) {
55 1.1 briggs printf(" fpu_emul_fstore: frame at %08x fpframe at %08x\n",
56 1.1 briggs frame, fe->fe_fpframe);
57 1.1 briggs }
58 1.1 briggs
59 1.1 briggs word1 = insn->is_word1;
60 1.1 briggs format = (word1 >> 10) & 7;
61 1.1 briggs regnum = (word1 >> 7) & 7;
62 1.1 briggs
63 1.1 briggs insn->is_advance = 4;
64 1.1 briggs
65 1.1 briggs if (format == FTYPE_DBL) {
66 1.1 briggs insn->is_datasize = 8;
67 1.1 briggs } else if (format == FTYPE_SNG || format == FTYPE_LNG) {
68 1.1 briggs insn->is_datasize = 4;
69 1.1 briggs } else if (format == FTYPE_WRD) {
70 1.1 briggs insn->is_datasize = 2;
71 1.1 briggs format = FTYPE_LNG;
72 1.1 briggs } else if (format == FTYPE_BYT) {
73 1.1 briggs insn->is_datasize = 1;
74 1.1 briggs format = FTYPE_LNG;
75 1.1 briggs } else if (format == FTYPE_EXT) {
76 1.1 briggs insn->is_datasize = 12;
77 1.1 briggs } else {
78 1.1 briggs /* invalid or unsupported operand format */
79 1.2 briggs if (fpu_debug_level & DL_FSTORE) {
80 1.1 briggs printf(" fpu_emul_fstore: invalid format %d\n", format);
81 1.1 briggs }
82 1.1 briggs sig = SIGFPE;
83 1.1 briggs }
84 1.2 briggs if (fpu_debug_level & DL_FSTORE) {
85 1.1 briggs printf(" fpu_emul_fstore: format %d, size %d\n",
86 1.1 briggs format, insn->is_datasize);
87 1.1 briggs }
88 1.1 briggs
89 1.1 briggs /* Get effective address. (modreg=opcode&077) */
90 1.1 briggs sig = fpu_decode_ea(frame, insn, &insn->is_ea0, insn->is_opcode);
91 1.1 briggs if (sig) {
92 1.2 briggs if (fpu_debug_level & DL_FSTORE) {
93 1.1 briggs printf(" fpu_emul_fstore: failed in decode_ea sig=%d\n", sig);
94 1.1 briggs }
95 1.1 briggs return sig;
96 1.1 briggs }
97 1.1 briggs
98 1.1 briggs if (insn->is_datasize > 4 && insn->is_ea0.ea_flags == EA_DIRECT) {
99 1.1 briggs /* trying to store dbl or ext into a data register */
100 1.1 briggs #ifdef DEBUG
101 1.1 briggs printf(" fpu_fstore: attempted to store dbl/ext to reg\n");
102 1.1 briggs #endif
103 1.1 briggs return SIGILL;
104 1.1 briggs }
105 1.1 briggs
106 1.2 briggs if (fpu_debug_level & DL_OPERANDS)
107 1.1 briggs printf(" fpu_emul_fstore: saving FP%d (%08x,%08x,%08x)\n",
108 1.1 briggs regnum, fpregs[regnum * 3], fpregs[regnum * 3 + 1],
109 1.1 briggs fpregs[regnum * 3 + 2]);
110 1.1 briggs fpu_explode(fe, &fe->fe_f3, FTYPE_EXT, &fpregs[regnum * 3]);
111 1.2 briggs if (fpu_debug_level & DL_VALUES) {
112 1.1 briggs static char *class_name[] = { "SNAN", "QNAN", "ZERO", "NUM", "INF" };
113 1.1 briggs printf(" fpu_emul_fstore: fpn (%s,%c,%d,%08x,%08x,%08x,%08x)\n",
114 1.1 briggs class_name[fe->fe_f3.fp_class + 2],
115 1.1 briggs fe->fe_f3.fp_sign ? '-' : '+', fe->fe_f3.fp_exp,
116 1.1 briggs fe->fe_f3.fp_mant[0], fe->fe_f3.fp_mant[1],
117 1.1 briggs fe->fe_f3.fp_mant[2], fe->fe_f3.fp_mant[3]);
118 1.1 briggs }
119 1.1 briggs fpu_implode(fe, &fe->fe_f3, format, buf);
120 1.1 briggs
121 1.1 briggs fpu_store_ea(frame, insn, &insn->is_ea0, (char *)buf);
122 1.2 briggs if (fpu_debug_level & DL_RESULT)
123 1.1 briggs printf(" fpu_emul_fstore: %08x,%08x,%08x size %d\n",
124 1.1 briggs buf[0], buf[1], buf[2], insn->is_datasize);
125 1.1 briggs
126 1.1 briggs return 0;
127 1.1 briggs }
128