fpu_subr.c revision 1.2
1 /* $NetBSD: fpu_subr.c,v 1.2 1996/04/30 11:52:38 briggs Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This software was developed by the Computer Systems Engineering group 8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 9 * contributed to Berkeley. 10 * 11 * All advertising materials mentioning features or use of this software 12 * must display the following acknowledgement: 13 * This product includes software developed by the University of 14 * California, Lawrence Berkeley Laboratory. 15 * 16 * Redistribution and use in source and binary forms, with or without 17 * modification, are permitted provided that the following conditions 18 * are met: 19 * 1. Redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer. 21 * 2. Redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution. 24 * 3. All advertising materials mentioning features or use of this software 25 * must display the following acknowledgement: 26 * This product includes software developed by the University of 27 * California, Berkeley and its contributors. 28 * 4. Neither the name of the University nor the names of its contributors 29 * may be used to endorse or promote products derived from this software 30 * without specific prior written permission. 31 * 32 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 33 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 34 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 35 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 36 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 37 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 38 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 39 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 40 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 41 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 42 * SUCH DAMAGE. 43 * 44 * @(#)fpu_subr.c 8.1 (Berkeley) 6/11/93 45 */ 46 47 /* 48 * FPU subroutines. 49 */ 50 51 #include <sys/types.h> 52 #include <sys/systm.h> 53 54 #include <machine/reg.h> 55 56 #include "fpu_emulate.h" 57 #include "fpu_arith.h" 58 59 /* 60 * Shift the given number right rsh bits. Any bits that `fall off' will get 61 * shoved into the sticky field; we return the resulting sticky. Note that 62 * shifting NaNs is legal (this will never shift all bits out); a NaN's 63 * sticky field is ignored anyway. 64 */ 65 int 66 fpu_shr(register struct fpn *fp, register int rsh) 67 { 68 register u_int m0, m1, m2, m3, s; 69 register int lsh; 70 71 #ifdef DIAGNOSTIC 72 if (rsh <= 0 || (fp->fp_class != FPC_NUM && !ISNAN(fp))) 73 panic("fpu_rightshift 1"); 74 #endif 75 76 m0 = fp->fp_mant[0]; 77 m1 = fp->fp_mant[1]; 78 m2 = fp->fp_mant[2]; 79 m3 = fp->fp_mant[3]; 80 81 /* If shifting all the bits out, take a shortcut. */ 82 if (rsh >= FP_NMANT) { 83 #ifdef DIAGNOSTIC 84 if ((m0 | m1 | m2 | m3) == 0) 85 panic("fpu_rightshift 2"); 86 #endif 87 fp->fp_mant[0] = 0; 88 fp->fp_mant[1] = 0; 89 fp->fp_mant[2] = 0; 90 fp->fp_mant[3] = 0; 91 #ifdef notdef 92 if ((m0 | m1 | m2 | m3) == 0) 93 fp->fp_class = FPC_ZERO; 94 else 95 #endif 96 fp->fp_sticky = 1; 97 return (1); 98 } 99 100 /* Squish out full words. */ 101 s = fp->fp_sticky; 102 if (rsh >= 32 * 3) { 103 s |= m3 | m2 | m1; 104 m3 = m0, m2 = 0, m1 = 0, m0 = 0; 105 } else if (rsh >= 32 * 2) { 106 s |= m3 | m2; 107 m3 = m1, m2 = m0, m1 = 0, m0 = 0; 108 } else if (rsh >= 32) { 109 s |= m3; 110 m3 = m2, m2 = m1, m1 = m0, m0 = 0; 111 } 112 113 /* Handle any remaining partial word. */ 114 if ((rsh &= 31) != 0) { 115 lsh = 32 - rsh; 116 s |= m3 << lsh; 117 m3 = (m3 >> rsh) | (m2 << lsh); 118 m2 = (m2 >> rsh) | (m1 << lsh); 119 m1 = (m1 >> rsh) | (m0 << lsh); 120 m0 >>= rsh; 121 } 122 fp->fp_mant[0] = m0; 123 fp->fp_mant[1] = m1; 124 fp->fp_mant[2] = m2; 125 fp->fp_mant[3] = m3; 126 fp->fp_sticky = s; 127 return (s); 128 } 129 130 /* 131 * Force a number to be normal, i.e., make its fraction have all zero 132 * bits before FP_1, then FP_1, then all 1 bits. This is used for denorms 133 * and (sometimes) for intermediate results. 134 * 135 * Internally, this may use a `supernormal' -- a number whose fp_mant 136 * is greater than or equal to 2.0 -- so as a side effect you can hand it 137 * a supernormal and it will fix it (provided fp->fp_mant[3] == 0). 138 */ 139 void 140 fpu_norm(register struct fpn *fp) 141 { 142 register u_int m0, m1, m2, m3, top, sup, nrm; 143 register int lsh, rsh, exp; 144 145 exp = fp->fp_exp; 146 m0 = fp->fp_mant[0]; 147 m1 = fp->fp_mant[1]; 148 m2 = fp->fp_mant[2]; 149 m3 = fp->fp_mant[3]; 150 151 /* Handle severe subnormals with 32-bit moves. */ 152 if (m0 == 0) { 153 if (m1) 154 m0 = m1, m1 = m2, m2 = m3, m3 = 0, exp -= 32; 155 else if (m2) 156 m0 = m2, m1 = m3, m2 = 0, m3 = 0, exp -= 2 * 32; 157 else if (m3) 158 m0 = m3, m1 = 0, m2 = 0, m3 = 0, exp -= 3 * 32; 159 else { 160 fp->fp_class = FPC_ZERO; 161 return; 162 } 163 } 164 165 /* Now fix any supernormal or remaining subnormal. */ 166 nrm = FP_1; 167 sup = nrm << 1; 168 if (m0 >= sup) { 169 /* 170 * We have a supernormal number. We need to shift it right. 171 * We may assume m3==0. 172 */ 173 for (rsh = 1, top = m0 >> 1; top >= sup; rsh++) /* XXX slow */ 174 top >>= 1; 175 exp += rsh; 176 lsh = 32 - rsh; 177 m3 = m2 << lsh; 178 m2 = (m2 >> rsh) | (m1 << lsh); 179 m1 = (m1 >> rsh) | (m0 << lsh); 180 m0 = top; 181 } else if (m0 < nrm) { 182 /* 183 * We have a regular denorm (a subnormal number), and need 184 * to shift it left. 185 */ 186 for (lsh = 1, top = m0 << 1; top < nrm; lsh++) /* XXX slow */ 187 top <<= 1; 188 exp -= lsh; 189 rsh = 32 - lsh; 190 m0 = top | (m1 >> rsh); 191 m1 = (m1 << lsh) | (m2 >> rsh); 192 m2 = (m2 << lsh) | (m3 >> rsh); 193 m3 <<= lsh; 194 } 195 196 fp->fp_exp = exp; 197 fp->fp_mant[0] = m0; 198 fp->fp_mant[1] = m1; 199 fp->fp_mant[2] = m2; 200 fp->fp_mant[3] = m3; 201 } 202 203 /* 204 * Concoct a `fresh' Quiet NaN per Appendix N. 205 * As a side effect, we set OPERR for the current exceptions. 206 */ 207 struct fpn * 208 fpu_newnan(register struct fpemu *fe) 209 { 210 register struct fpn *fp; 211 212 fe->fe_fpsr |= FPSR_OPERR; 213 fp = &fe->fe_f3; 214 fp->fp_class = FPC_QNAN; 215 fp->fp_sign = 0; 216 fp->fp_mant[0] = FP_1 - 1; 217 fp->fp_mant[1] = fp->fp_mant[2] = fp->fp_mant[3] = ~0; 218 return (fp); 219 } 220
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