netbsd.sa revision 1.5.4.2 1 1.5.4.2 chs * $NetBSD: netbsd.sa,v 1.5.4.2 2001/10/02 06:34:53 chs Exp $
2 1.5.4.2 chs
3 1.5.4.2 chs * MOTOROLA MICROPROCESSOR & MEMORY TECHNOLOGY GROUP
4 1.5.4.2 chs * M68000 Hi-Performance Microprocessor Division
5 1.5.4.2 chs * M68040 Software Package
6 1.5.4.2 chs *
7 1.5.4.2 chs * M68040 Software Package Copyright (c) 1993, 1994 Motorola Inc.
8 1.5.4.2 chs * All rights reserved.
9 1.5.4.2 chs *
10 1.5.4.2 chs * THE SOFTWARE is provided on an "AS IS" basis and without warranty.
11 1.5.4.2 chs * To the maximum extent permitted by applicable law,
12 1.5.4.2 chs * MOTOROLA DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
13 1.5.4.2 chs * INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A
14 1.5.4.2 chs * PARTICULAR PURPOSE and any warranty against infringement with
15 1.5.4.2 chs * regard to the SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF)
16 1.5.4.2 chs * and any accompanying written materials.
17 1.5.4.2 chs *
18 1.5.4.2 chs * To the maximum extent permitted by applicable law,
19 1.5.4.2 chs * IN NO EVENT SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER
20 1.5.4.2 chs * (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS
21 1.5.4.2 chs * PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR
22 1.5.4.2 chs * OTHER PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE
23 1.5.4.2 chs * SOFTWARE. Motorola assumes no responsibility for the maintenance
24 1.5.4.2 chs * and support of the SOFTWARE.
25 1.5.4.2 chs *
26 1.5.4.2 chs * You are hereby granted a copyright license to use, modify, and
27 1.5.4.2 chs * distribute the SOFTWARE so long as this entire notice is retained
28 1.5.4.2 chs * without alteration in any modified and/or redistributed versions,
29 1.5.4.2 chs * and that such modified versions are clearly identified as such.
30 1.5.4.2 chs * No licenses are granted by implication, estoppel or otherwise
31 1.5.4.2 chs * under any patents or trademarks of Motorola, Inc.
32 1.5.4.2 chs
33 1.5.4.2 chs *
34 1.5.4.2 chs * skeleton.sa 3.2 4/26/91
35 1.5.4.2 chs *
36 1.5.4.2 chs * This file contains code that is system dependent and will
37 1.5.4.2 chs * need to be modified to install the FPSP.
38 1.5.4.2 chs *
39 1.5.4.2 chs * Each entry point for exception 'xxxx' begins with a 'jmp fpsp_xxxx'.
40 1.5.4.2 chs * Put any target system specific handling that must be done immediately
41 1.5.4.2 chs * before the jump instruction. If there no handling necessary, then
42 1.5.4.2 chs * the 'fpsp_xxxx' handler entry point should be placed in the exception
43 1.5.4.2 chs * table so that the 'jmp' can be eliminated. If the FPSP determines that the
44 1.5.4.2 chs * exception is one that must be reported then there will be a
45 1.5.4.2 chs * return from the package by a 'jmp real_xxxx'. At that point
46 1.5.4.2 chs * the machine state will be identical to the state before
47 1.5.4.2 chs * the FPSP was entered. In particular, whatever condition
48 1.5.4.2 chs * that caused the exception will still be pending when the FPSP
49 1.5.4.2 chs * package returns. Thus, there will be system specific code
50 1.5.4.2 chs * to handle the exception.
51 1.5.4.2 chs *
52 1.5.4.2 chs * If the exception was completely handled by the package, then
53 1.5.4.2 chs * the return will be via a 'jmp fpsp_done'. Unless there is
54 1.5.4.2 chs * OS specific work to be done (such as handling a context switch or
55 1.5.4.2 chs * interrupt) the user program can be resumed via 'rte'.
56 1.5.4.2 chs *
57 1.5.4.2 chs * In the following skeleton code, some typical 'real_xxxx' handling
58 1.5.4.2 chs * code is shown. This code may need to be moved to an appropriate
59 1.5.4.2 chs * place in the target system, or rewritten.
60 1.5.4.2 chs *
61 1.5.4.2 chs
62 1.5.4.2 chs SKELETON IDNT 2,1 Motorola 040 Floating Point Software Package
63 1.5.4.2 chs
64 1.5.4.2 chs section 15
65 1.5.4.2 chs *
66 1.5.4.2 chs * The following counters are used for standalone testing
67 1.5.4.2 chs *
68 1.5.4.2 chs
69 1.5.4.2 chs section 8
70 1.5.4.2 chs
71 1.5.4.2 chs include fpsp.h
72 1.5.4.2 chs
73 1.5.4.2 chs *
74 1.5.4.2 chs * XXX Note, this is NOT valid Motorola syntax, but what else can we do?
75 1.5.4.2 chs *
76 1.5.4.2 chs #include <machine/asm.h>
77 1.5.4.2 chs
78 1.5.4.2 chs xref b1238_fix
79 1.5.4.2 chs xref _C_LABEL(mmutype)
80 1.5.4.2 chs
81 1.5.4.2 chs *
82 1.5.4.2 chs * Divide by Zero exception
83 1.5.4.2 chs *
84 1.5.4.2 chs * All dz exceptions are 'real', hence no fpsp_dz entry point.
85 1.5.4.2 chs *
86 1.5.4.2 chs xdef dz
87 1.5.4.2 chs xdef real_dz
88 1.5.4.2 chs dz:
89 1.5.4.2 chs cmp.l #-2,_C_LABEL(mmutype)
90 1.5.4.2 chs bne.l _C_LABEL(fpfault)
91 1.5.4.2 chs real_dz:
92 1.5.4.2 chs link a6,#-LOCAL_SIZE
93 1.5.4.2 chs fsave -(sp)
94 1.5.4.2 chs bclr.b #E1,E_BYTE(a6)
95 1.5.4.2 chs frestore (sp)+
96 1.5.4.2 chs unlk a6
97 1.5.4.2 chs jmp _C_LABEL(fpfault)
98 1.5.4.2 chs
99 1.5.4.2 chs *
100 1.5.4.2 chs * Inexact exception
101 1.5.4.2 chs *
102 1.5.4.2 chs * All inexact exceptions are real, but the 'real' handler
103 1.5.4.2 chs * will probably want to clear the pending exception.
104 1.5.4.2 chs * The provided code will clear the E3 exception (if pending),
105 1.5.4.2 chs * otherwise clear the E1 exception. The frestore is not really
106 1.5.4.2 chs * necessary for E1 exceptions.
107 1.5.4.2 chs *
108 1.5.4.2 chs * Code following the 'inex' label is to handle bug #1232. In this
109 1.5.4.2 chs * bug, if an E1 snan, ovfl, or unfl occurred, and the process was
110 1.5.4.2 chs * swapped out before taking the exception, the exception taken on
111 1.5.4.2 chs * return was inex, rather than the correct exception. The snan, ovfl,
112 1.5.4.2 chs * and unfl exception to be taken must not have been enabled. The
113 1.5.4.2 chs * fix is to check for E1, and the existence of one of snan, ovfl,
114 1.5.4.2 chs * or unfl bits set in the fpsr. If any of these are set, branch
115 1.5.4.2 chs * to the appropriate handler for the exception in the fpsr. Note
116 1.5.4.2 chs * that this fix is only for d43b parts, and is skipped if the
117 1.5.4.2 chs * version number is not $40.
118 1.5.4.2 chs *
119 1.5.4.2 chs *
120 1.5.4.2 chs xdef real_inex
121 1.5.4.2 chs xdef inex
122 1.5.4.2 chs inex:
123 1.5.4.2 chs cmp.l #-2,_C_LABEL(mmutype)
124 1.5.4.2 chs bne.l _C_LABEL(fpfault)
125 1.5.4.2 chs link a6,#-LOCAL_SIZE
126 1.5.4.2 chs fsave -(sp)
127 1.5.4.2 chs cmpi.b #VER_40,(sp) ;test version number
128 1.5.4.2 chs bne.b not_fmt40
129 1.5.4.2 chs fmove.l fpsr,-(sp)
130 1.5.4.2 chs btst.b #E1,E_BYTE(a6) ;test for E1 set
131 1.5.4.2 chs beq.b not_b1232
132 1.5.4.2 chs btst.b #snan_bit,2(sp) ;test for snan
133 1.5.4.2 chs beq inex_ckofl
134 1.5.4.2 chs addq.l #4,sp
135 1.5.4.2 chs frestore (sp)+
136 1.5.4.2 chs unlk a6
137 1.5.4.2 chs bra snan
138 1.5.4.2 chs inex_ckofl:
139 1.5.4.2 chs btst.b #ovfl_bit,2(sp) ;test for ovfl
140 1.5.4.2 chs beq inex_ckufl
141 1.5.4.2 chs addq.l #4,sp
142 1.5.4.2 chs frestore (sp)+
143 1.5.4.2 chs unlk a6
144 1.5.4.2 chs bra ovfl
145 1.5.4.2 chs inex_ckufl:
146 1.5.4.2 chs btst.b #unfl_bit,2(sp) ;test for unfl
147 1.5.4.2 chs beq not_b1232
148 1.5.4.2 chs addq.l #4,sp
149 1.5.4.2 chs frestore (sp)+
150 1.5.4.2 chs unlk a6
151 1.5.4.2 chs bra unfl
152 1.5.4.2 chs
153 1.5.4.2 chs *
154 1.5.4.2 chs * We do not have the bug 1232 case. Clean up the stack and call
155 1.5.4.2 chs * real_inex.
156 1.5.4.2 chs *
157 1.5.4.2 chs not_b1232:
158 1.5.4.2 chs addq.l #4,sp
159 1.5.4.2 chs frestore (sp)+
160 1.5.4.2 chs unlk a6
161 1.5.4.2 chs
162 1.5.4.2 chs real_inex:
163 1.5.4.2 chs link a6,#-LOCAL_SIZE
164 1.5.4.2 chs fsave -(sp)
165 1.5.4.2 chs not_fmt40:
166 1.5.4.2 chs bclr.b #E3,E_BYTE(a6) ;clear and test E3 flag
167 1.5.4.2 chs beq.b inex_cke1
168 1.5.4.2 chs *
169 1.5.4.2 chs * Clear dirty bit on dest resister in the frame before branching
170 1.5.4.2 chs * to b1238_fix.
171 1.5.4.2 chs *
172 1.5.4.2 chs movem.l d0/d1,USER_DA(a6)
173 1.5.4.2 chs bfextu CMDREG1B(a6){6:3},d0 ;get dest reg no
174 1.5.4.2 chs bclr.b d0,FPR_DIRTY_BITS(a6) ;clr dest dirty bit
175 1.5.4.2 chs bsr.l b1238_fix ;test for bug1238 case
176 1.5.4.2 chs movem.l USER_DA(a6),d0/d1
177 1.5.4.2 chs bra.b inex_done
178 1.5.4.2 chs inex_cke1:
179 1.5.4.2 chs bclr.b #E1,E_BYTE(a6)
180 1.5.4.2 chs inex_done:
181 1.5.4.2 chs frestore (sp)+
182 1.5.4.2 chs unlk a6
183 1.5.4.2 chs jmp _C_LABEL(fpfault)
184 1.5.4.2 chs
185 1.5.4.2 chs *
186 1.5.4.2 chs * Overflow exception
187 1.5.4.2 chs *
188 1.5.4.2 chs xref fpsp_ovfl
189 1.5.4.2 chs xdef real_ovfl
190 1.5.4.2 chs xdef ovfl
191 1.5.4.2 chs ovfl:
192 1.5.4.2 chs cmp.l #-2,_C_LABEL(mmutype)
193 1.5.4.2 chs beq.l fpsp_ovfl
194 1.5.4.2 chs jmp _C_LABEL(fpfault)
195 1.5.4.2 chs real_ovfl:
196 1.5.4.2 chs link a6,#-LOCAL_SIZE
197 1.5.4.2 chs fsave -(sp)
198 1.5.4.2 chs bclr.b #E3,E_BYTE(a6) ;clear and test E3 flag
199 1.5.4.2 chs bne.b ovfl_done
200 1.5.4.2 chs bclr.b #E1,E_BYTE(a6)
201 1.5.4.2 chs ovfl_done:
202 1.5.4.2 chs frestore (sp)+
203 1.5.4.2 chs unlk a6
204 1.5.4.2 chs jmp _C_LABEL(fpfault)
205 1.5.4.2 chs
206 1.5.4.2 chs *
207 1.5.4.2 chs * Underflow exception
208 1.5.4.2 chs *
209 1.5.4.2 chs xref fpsp_unfl
210 1.5.4.2 chs xdef real_unfl
211 1.5.4.2 chs xdef unfl
212 1.5.4.2 chs unfl:
213 1.5.4.2 chs cmp.l #-2,_C_LABEL(mmutype)
214 1.5.4.2 chs beq.l fpsp_unfl
215 1.5.4.2 chs jmp _C_LABEL(fpfault)
216 1.5.4.2 chs real_unfl:
217 1.5.4.2 chs link a6,#-LOCAL_SIZE
218 1.5.4.2 chs fsave -(sp)
219 1.5.4.2 chs bclr.b #E3,E_BYTE(a6) ;clear and test E3 flag
220 1.5.4.2 chs bne.b unfl_done
221 1.5.4.2 chs bclr.b #E1,E_BYTE(a6)
222 1.5.4.2 chs unfl_done:
223 1.5.4.2 chs frestore (sp)+
224 1.5.4.2 chs unlk a6
225 1.5.4.2 chs jmp _C_LABEL(fpfault)
226 1.5.4.2 chs
227 1.5.4.2 chs *
228 1.5.4.2 chs * Signalling NAN exception
229 1.5.4.2 chs *
230 1.5.4.2 chs xref fpsp_snan
231 1.5.4.2 chs xdef real_snan
232 1.5.4.2 chs xdef snan
233 1.5.4.2 chs snan:
234 1.5.4.2 chs cmp.l #-2,_C_LABEL(mmutype)
235 1.5.4.2 chs beq.l fpsp_snan
236 1.5.4.2 chs jmp _C_LABEL(fpfault)
237 1.5.4.2 chs real_snan:
238 1.5.4.2 chs link a6,#-LOCAL_SIZE
239 1.5.4.2 chs fsave -(sp)
240 1.5.4.2 chs bclr.b #E1,E_BYTE(a6) ;snan is always an E1 exception
241 1.5.4.2 chs frestore (sp)+
242 1.5.4.2 chs unlk a6
243 1.5.4.2 chs jmp _C_LABEL(fpfault)
244 1.5.4.2 chs
245 1.5.4.2 chs *
246 1.5.4.2 chs * Operand Error exception
247 1.5.4.2 chs *
248 1.5.4.2 chs xref fpsp_operr
249 1.5.4.2 chs xdef real_operr
250 1.5.4.2 chs xdef operr
251 1.5.4.2 chs operr:
252 1.5.4.2 chs cmp.l #-2,_C_LABEL(mmutype)
253 1.5.4.2 chs beq.l fpsp_operr
254 1.5.4.2 chs jmp _C_LABEL(fpfault)
255 1.5.4.2 chs real_operr:
256 1.5.4.2 chs link a6,#-LOCAL_SIZE
257 1.5.4.2 chs fsave -(sp)
258 1.5.4.2 chs bclr.b #E1,E_BYTE(a6) ;operr is always an E1 exception
259 1.5.4.2 chs frestore (sp)+
260 1.5.4.2 chs unlk a6
261 1.5.4.2 chs jmp _C_LABEL(fpfault)
262 1.5.4.2 chs
263 1.5.4.2 chs *
264 1.5.4.2 chs * BSUN exception
265 1.5.4.2 chs *
266 1.5.4.2 chs * This sample handler simply clears the nan bit in the FPSR.
267 1.5.4.2 chs *
268 1.5.4.2 chs xref fpsp_bsun
269 1.5.4.2 chs xdef real_bsun
270 1.5.4.2 chs xdef bsun
271 1.5.4.2 chs bsun:
272 1.5.4.2 chs cmp.l #-2,_C_LABEL(mmutype)
273 1.5.4.2 chs beq.l fpsp_bsun
274 1.5.4.2 chs jmp _C_LABEL(fpfault)
275 1.5.4.2 chs real_bsun:
276 1.5.4.2 chs link a6,#-LOCAL_SIZE
277 1.5.4.2 chs fsave -(sp)
278 1.5.4.2 chs bclr.b #E1,E_BYTE(a6) ;bsun is always an E1 exception
279 1.5.4.2 chs fmove.l FPSR,-(sp)
280 1.5.4.2 chs bclr.b #nan_bit,(sp)
281 1.5.4.2 chs fmove.l (sp)+,FPSR
282 1.5.4.2 chs frestore (sp)+
283 1.5.4.2 chs unlk a6
284 1.5.4.2 chs jmp _C_LABEL(fpfault)
285 1.5.4.2 chs
286 1.5.4.2 chs *
287 1.5.4.2 chs * F-line exception
288 1.5.4.2 chs *
289 1.5.4.2 chs * A 'real' F-line exception is one that the FPSP isn't supposed to
290 1.5.4.2 chs * handle. E.g. an instruction with a co-processor ID that is not 1.
291 1.5.4.2 chs *
292 1.5.4.2 chs *
293 1.5.4.2 chs xref fpsp_fline
294 1.5.4.2 chs xdef real_fline
295 1.5.4.2 chs xdef fline
296 1.5.4.2 chs fline:
297 1.5.4.2 chs cmp.l #-2,_C_LABEL(mmutype)
298 1.5.4.2 chs beq.l fpsp_fline
299 1.5.4.2 chs jmp _C_LABEL(fpfault)
300 1.5.4.2 chs real_fline:
301 1.5.4.2 chs jmp _C_LABEL(fpfault)
302 1.5.4.2 chs
303 1.5.4.2 chs *
304 1.5.4.2 chs * Unsupported data type exception
305 1.5.4.2 chs *
306 1.5.4.2 chs xref fpsp_unsupp
307 1.5.4.2 chs xdef real_unsupp
308 1.5.4.2 chs xdef unsupp
309 1.5.4.2 chs unsupp:
310 1.5.4.2 chs cmp.l #-2,_C_LABEL(mmutype)
311 1.5.4.2 chs beq.l fpsp_unsupp
312 1.5.4.2 chs jmp _C_LABEL(fpfault)
313 1.5.4.2 chs real_unsupp:
314 1.5.4.2 chs link a6,#-LOCAL_SIZE
315 1.5.4.2 chs fsave -(sp)
316 1.5.4.2 chs bclr.b #E1,E_BYTE(a6) ;unsupp is always an E1 exception
317 1.5.4.2 chs frestore (sp)+
318 1.5.4.2 chs unlk a6
319 1.5.4.2 chs jmp _C_LABEL(fpfault)
320 1.5.4.2 chs
321 1.5.4.2 chs *
322 1.5.4.2 chs * Trace exception
323 1.5.4.2 chs *
324 1.5.4.2 chs xdef real_trace
325 1.5.4.2 chs real_trace:
326 1.5.4.2 chs rte
327 1.5.4.2 chs
328 1.5.4.2 chs *
329 1.5.4.2 chs * fpsp_fmt_error --- exit point for frame format error
330 1.5.4.2 chs *
331 1.5.4.2 chs * The fpu stack frame does not match the frames existing
332 1.5.4.2 chs * or planned at the time of this writing. The fpsp is
333 1.5.4.2 chs * unable to handle frame sizes not in the following
334 1.5.4.2 chs * version:size pairs:
335 1.5.4.2 chs *
336 1.5.4.2 chs * {4060, 4160} - busy frame
337 1.5.4.2 chs * {4028, 4130} - unimp frame
338 1.5.4.2 chs * {4000, 4100} - idle frame
339 1.5.4.2 chs *
340 1.5.4.2 chs * This entry point simply holds an f-line illegal value.
341 1.5.4.2 chs * Replace this with a call to your kernel panic code or
342 1.5.4.2 chs * code to handle future revisions of the fpu.
343 1.5.4.2 chs *
344 1.5.4.2 chs xdef fpsp_fmt_error
345 1.5.4.2 chs fpsp_fmt_error:
346 1.5.4.2 chs pea 1f
347 1.5.4.2 chs jsr _C_LABEL(panic)
348 1.5.4.2 chs dc.l $f27f0000 ;f-line illegal
349 1.5.4.2 chs 1:
350 1.5.4.2 chs .asciz "bad floating point stack frame"
351 1.5.4.2 chs .even
352 1.5.4.2 chs
353 1.5.4.2 chs *
354 1.5.4.2 chs * fpsp_done --- FPSP exit point
355 1.5.4.2 chs *
356 1.5.4.2 chs * The exception has been handled by the package and we are ready
357 1.5.4.2 chs * to return to user mode, but there may be OS specific code
358 1.5.4.2 chs * to execute before we do. If there is, do it now.
359 1.5.4.2 chs *
360 1.5.4.2 chs *
361 1.5.4.2 chs xref _ASM_LABEL(rei)
362 1.5.4.2 chs xdef fpsp_done
363 1.5.4.2 chs fpsp_done:
364 1.5.4.2 chs jmp _ASM_LABEL(rei)
365 1.5.4.2 chs
366 1.5.4.2 chs *
367 1.5.4.2 chs * mem_write --- write to user or supervisor address space
368 1.5.4.2 chs *
369 1.5.4.2 chs * Writes to memory while in supervisor mode. copyout accomplishes
370 1.5.4.2 chs * this via a 'moves' instruction. copyout is a UNIX SVR3 (and later) function.
371 1.5.4.2 chs * If you don't have copyout, use the local copy of the function below.
372 1.5.4.2 chs *
373 1.5.4.2 chs * a0 - supervisor source address
374 1.5.4.2 chs * a1 - user destination address
375 1.5.4.2 chs * d0 - number of bytes to write (maximum count is 12)
376 1.5.4.2 chs *
377 1.5.4.2 chs * The supervisor source address is guaranteed to point into the supervisor
378 1.5.4.2 chs * stack. The result is that a UNIX
379 1.5.4.2 chs * process is allowed to sleep as a consequence of a page fault during
380 1.5.4.2 chs * copyout. The probability of a page fault is exceedingly small because
381 1.5.4.2 chs * the 68040 always reads the destination address and thus the page
382 1.5.4.2 chs * faults should have already been handled.
383 1.5.4.2 chs *
384 1.5.4.2 chs * If the EXC_SR shows that the exception was from supervisor space,
385 1.5.4.2 chs * then just do a dumb (and slow) memory move. In a UNIX environment
386 1.5.4.2 chs * there shouldn't be any supervisor mode floating point exceptions.
387 1.5.4.2 chs *
388 1.5.4.2 chs xdef mem_write
389 1.5.4.2 chs mem_write:
390 1.5.4.2 chs btst.b #5,EXC_SR(a6) ;check for supervisor state
391 1.5.4.2 chs beq.b user_write
392 1.5.4.2 chs super_write:
393 1.5.4.2 chs move.b (a0)+,(a1)+
394 1.5.4.2 chs subq.l #1,d0
395 1.5.4.2 chs bne.b super_write
396 1.5.4.2 chs rts
397 1.5.4.2 chs user_write:
398 1.5.4.2 chs move.l d1,-(sp) ;preserve d1 just in case
399 1.5.4.2 chs move.l d0,-(sp)
400 1.5.4.2 chs move.l a1,-(sp)
401 1.5.4.2 chs move.l a0,-(sp)
402 1.5.4.2 chs jsr _C_LABEL(copyout)
403 1.5.4.2 chs add.l #12,sp
404 1.5.4.2 chs move.l (sp)+,d1
405 1.5.4.2 chs rts
406 1.5.4.2 chs
407 1.5.4.2 chs *
408 1.5.4.2 chs * mem_read --- read from user or supervisor address space
409 1.5.4.2 chs *
410 1.5.4.2 chs * Reads from memory while in supervisor mode. copyin accomplishes
411 1.5.4.2 chs * this via a 'moves' instruction. copyin is a UNIX SVR3 (and later) function.
412 1.5.4.2 chs * If you don't have copyin, use the local copy of the function below.
413 1.5.4.2 chs *
414 1.5.4.2 chs * The FPSP calls mem_read to read the original F-line instruction in order
415 1.5.4.2 chs * to extract the data register number when the 'Dn' addressing mode is
416 1.5.4.2 chs * used.
417 1.5.4.2 chs *
418 1.5.4.2 chs *Input:
419 1.5.4.2 chs * a0 - user source address
420 1.5.4.2 chs * a1 - supervisor destination address
421 1.5.4.2 chs * d0 - number of bytes to read (maximum count is 12)
422 1.5.4.2 chs *
423 1.5.4.2 chs * Like mem_write, mem_read always reads with a supervisor
424 1.5.4.2 chs * destination address on the supervisor stack. Also like mem_write,
425 1.5.4.2 chs * the EXC_SR is checked and a simple memory copy is done if reading
426 1.5.4.2 chs * from supervisor space is indicated.
427 1.5.4.2 chs *
428 1.5.4.2 chs xdef mem_read
429 1.5.4.2 chs mem_read:
430 1.5.4.2 chs btst.b #5,EXC_SR(a6) ;check for supervisor state
431 1.5.4.2 chs beq.b user_read
432 1.5.4.2 chs super_read:
433 1.5.4.2 chs move.b (a0)+,(a1)+
434 1.5.4.2 chs subq.l #1,d0
435 1.5.4.2 chs bne.b super_read
436 1.5.4.2 chs rts
437 1.5.4.2 chs user_read:
438 1.5.4.2 chs move.l d1,-(sp) ;preserve d1 just in case
439 1.5.4.2 chs move.l d0,-(sp)
440 1.5.4.2 chs move.l a1,-(sp)
441 1.5.4.2 chs move.l a0,-(sp)
442 1.5.4.2 chs jsr _C_LABEL(copyin)
443 1.5.4.2 chs add.l #12,sp
444 1.5.4.2 chs move.l (sp)+,d1
445 1.5.4.2 chs rts
446 1.5.4.2 chs
447 1.5.4.2 chs end
448