x_ovfl.sa revision 1.3.4.2
1 1.3.4.2 wiz * $NetBSD: x_ovfl.sa,v 1.3.4.2 2001/09/16 16:34:33 wiz Exp $ 2 1.3.4.2 wiz 3 1.3.4.2 wiz * MOTOROLA MICROPROCESSOR & MEMORY TECHNOLOGY GROUP 4 1.3.4.2 wiz * M68000 Hi-Performance Microprocessor Division 5 1.3.4.2 wiz * M68040 Software Package 6 1.3.4.2 wiz * 7 1.3.4.2 wiz * M68040 Software Package Copyright (c) 1993, 1994 Motorola Inc. 8 1.3.4.2 wiz * All rights reserved. 9 1.3.4.2 wiz * 10 1.3.4.2 wiz * THE SOFTWARE is provided on an "AS IS" basis and without warranty. 11 1.3.4.2 wiz * To the maximum extent permitted by applicable law, 12 1.3.4.2 wiz * MOTOROLA DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, 13 1.3.4.2 wiz * INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A 14 1.3.4.2 wiz * PARTICULAR PURPOSE and any warranty against infringement with 15 1.3.4.2 wiz * regard to the SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF) 16 1.3.4.2 wiz * and any accompanying written materials. 17 1.3.4.2 wiz * 18 1.3.4.2 wiz * To the maximum extent permitted by applicable law, 19 1.3.4.2 wiz * IN NO EVENT SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER 20 1.3.4.2 wiz * (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS 21 1.3.4.2 wiz * PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR 22 1.3.4.2 wiz * OTHER PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE 23 1.3.4.2 wiz * SOFTWARE. Motorola assumes no responsibility for the maintenance 24 1.3.4.2 wiz * and support of the SOFTWARE. 25 1.3.4.2 wiz * 26 1.3.4.2 wiz * You are hereby granted a copyright license to use, modify, and 27 1.3.4.2 wiz * distribute the SOFTWARE so long as this entire notice is retained 28 1.3.4.2 wiz * without alteration in any modified and/or redistributed versions, 29 1.3.4.2 wiz * and that such modified versions are clearly identified as such. 30 1.3.4.2 wiz * No licenses are granted by implication, estoppel or otherwise 31 1.3.4.2 wiz * under any patents or trademarks of Motorola, Inc. 32 1.3.4.2 wiz 33 1.3.4.2 wiz * 34 1.3.4.2 wiz * x_ovfl.sa 3.5 7/1/91 35 1.3.4.2 wiz * 36 1.3.4.2 wiz * fpsp_ovfl --- FPSP handler for overflow exception 37 1.3.4.2 wiz * 38 1.3.4.2 wiz * Overflow occurs when a floating-point intermediate result is 39 1.3.4.2 wiz * too large to be represented in a floating-point data register, 40 1.3.4.2 wiz * or when storing to memory, the contents of a floating-point 41 1.3.4.2 wiz * data register are too large to be represented in the 42 1.3.4.2 wiz * destination format. 43 1.3.4.2 wiz * 44 1.3.4.2 wiz * Trap disabled results 45 1.3.4.2 wiz * 46 1.3.4.2 wiz * If the instruction is move_out, then garbage is stored in the 47 1.3.4.2 wiz * destination. If the instruction is not move_out, then the 48 1.3.4.2 wiz * destination is not affected. For 68881 compatibility, the 49 1.3.4.2 wiz * following values should be stored at the destination, based 50 1.3.4.2 wiz * on the current rounding mode: 51 1.3.4.2 wiz * 52 1.3.4.2 wiz * RN Infinity with the sign of the intermediate result. 53 1.3.4.2 wiz * RZ Largest magnitude number, with the sign of the 54 1.3.4.2 wiz * intermediate result. 55 1.3.4.2 wiz * RM For pos overflow, the largest pos number. For neg overflow, 56 1.3.4.2 wiz * -infinity 57 1.3.4.2 wiz * RP For pos overflow, +infinity. For neg overflow, the largest 58 1.3.4.2 wiz * neg number 59 1.3.4.2 wiz * 60 1.3.4.2 wiz * Trap enabled results 61 1.3.4.2 wiz * All trap disabled code applies. In addition the exceptional 62 1.3.4.2 wiz * operand needs to be made available to the users exception handler 63 1.3.4.2 wiz * with a bias of $6000 subtracted from the exponent. 64 1.3.4.2 wiz * 65 1.3.4.2 wiz 66 1.3.4.2 wiz X_OVFL IDNT 2,1 Motorola 040 Floating Point Software Package 67 1.3.4.2 wiz 68 1.3.4.2 wiz section 8 69 1.3.4.2 wiz 70 1.3.4.2 wiz include fpsp.h 71 1.3.4.2 wiz 72 1.3.4.2 wiz xref ovf_r_x2 73 1.3.4.2 wiz xref ovf_r_x3 74 1.3.4.2 wiz xref store 75 1.3.4.2 wiz xref real_ovfl 76 1.3.4.2 wiz xref real_inex 77 1.3.4.2 wiz xref fpsp_done 78 1.3.4.2 wiz xref g_opcls 79 1.3.4.2 wiz xref b1238_fix 80 1.3.4.2 wiz 81 1.3.4.2 wiz xdef fpsp_ovfl 82 1.3.4.2 wiz fpsp_ovfl: 83 1.3.4.2 wiz link a6,#-LOCAL_SIZE 84 1.3.4.2 wiz fsave -(a7) 85 1.3.4.2 wiz movem.l d0-d1/a0-a1,USER_DA(a6) 86 1.3.4.2 wiz fmovem.x fp0-fp3,USER_FP0(a6) 87 1.3.4.2 wiz fmovem.l fpcr/fpsr/fpiar,USER_FPCR(a6) 88 1.3.4.2 wiz 89 1.3.4.2 wiz * 90 1.3.4.2 wiz * The 040 doesn't set the AINEX bit in the FPSR, the following 91 1.3.4.2 wiz * line temporarily rectifies this error. 92 1.3.4.2 wiz * 93 1.3.4.2 wiz bset.b #ainex_bit,FPSR_AEXCEPT(a6) 94 1.3.4.2 wiz * 95 1.3.4.2 wiz bsr.l ovf_adj ;denormalize, round & store interm op 96 1.3.4.2 wiz * 97 1.3.4.2 wiz * if overflow traps not enabled check for inexact exception 98 1.3.4.2 wiz * 99 1.3.4.2 wiz btst.b #ovfl_bit,FPCR_ENABLE(a6) 100 1.3.4.2 wiz beq.b ck_inex 101 1.3.4.2 wiz * 102 1.3.4.2 wiz btst.b #E3,E_BYTE(a6) 103 1.3.4.2 wiz beq.b no_e3_1 104 1.3.4.2 wiz bfextu CMDREG3B(a6){6:3},d0 ;get dest reg no 105 1.3.4.2 wiz bclr.b d0,FPR_DIRTY_BITS(a6) ;clr dest dirty bit 106 1.3.4.2 wiz bsr.l b1238_fix 107 1.3.4.2 wiz move.l USER_FPSR(a6),FPSR_SHADOW(a6) 108 1.3.4.2 wiz or.l #sx_mask,E_BYTE(a6) 109 1.3.4.2 wiz no_e3_1: 110 1.3.4.2 wiz movem.l USER_DA(a6),d0-d1/a0-a1 111 1.3.4.2 wiz fmovem.x USER_FP0(a6),fp0-fp3 112 1.3.4.2 wiz fmovem.l USER_FPCR(a6),fpcr/fpsr/fpiar 113 1.3.4.2 wiz frestore (a7)+ 114 1.3.4.2 wiz unlk a6 115 1.3.4.2 wiz bra.l real_ovfl 116 1.3.4.2 wiz * 117 1.3.4.2 wiz * It is possible to have either inex2 or inex1 exceptions with the 118 1.3.4.2 wiz * ovfl. If the inex enable bit is set in the FPCR, and either 119 1.3.4.2 wiz * inex2 or inex1 occurred, we must clean up and branch to the 120 1.3.4.2 wiz * real inex handler. 121 1.3.4.2 wiz * 122 1.3.4.2 wiz ck_inex: 123 1.3.4.2 wiz * move.b FPCR_ENABLE(a6),d0 124 1.3.4.2 wiz * and.b FPSR_EXCEPT(a6),d0 125 1.3.4.2 wiz * andi.b #$3,d0 126 1.3.4.2 wiz btst.b #inex2_bit,FPCR_ENABLE(a6) 127 1.3.4.2 wiz beq.b ovfl_exit 128 1.3.4.2 wiz * 129 1.3.4.2 wiz * Inexact enabled and reported, and we must take an inexact exception. 130 1.3.4.2 wiz * 131 1.3.4.2 wiz take_inex: 132 1.3.4.2 wiz btst.b #E3,E_BYTE(a6) 133 1.3.4.2 wiz beq.b no_e3_2 134 1.3.4.2 wiz bfextu CMDREG3B(a6){6:3},d0 ;get dest reg no 135 1.3.4.2 wiz bclr.b d0,FPR_DIRTY_BITS(a6) ;clr dest dirty bit 136 1.3.4.2 wiz bsr.l b1238_fix 137 1.3.4.2 wiz move.l USER_FPSR(a6),FPSR_SHADOW(a6) 138 1.3.4.2 wiz or.l #sx_mask,E_BYTE(a6) 139 1.3.4.2 wiz no_e3_2: 140 1.3.4.2 wiz move.b #INEX_VEC,EXC_VEC+1(a6) 141 1.3.4.2 wiz movem.l USER_DA(a6),d0-d1/a0-a1 142 1.3.4.2 wiz fmovem.x USER_FP0(a6),fp0-fp3 143 1.3.4.2 wiz fmovem.l USER_FPCR(a6),fpcr/fpsr/fpiar 144 1.3.4.2 wiz frestore (a7)+ 145 1.3.4.2 wiz unlk a6 146 1.3.4.2 wiz bra.l real_inex 147 1.3.4.2 wiz 148 1.3.4.2 wiz ovfl_exit: 149 1.3.4.2 wiz bclr.b #E3,E_BYTE(a6) ;test and clear E3 bit 150 1.3.4.2 wiz beq.b e1_set 151 1.3.4.2 wiz * 152 1.3.4.2 wiz * Clear dirty bit on dest resister in the frame before branching 153 1.3.4.2 wiz * to b1238_fix. 154 1.3.4.2 wiz * 155 1.3.4.2 wiz bfextu CMDREG3B(a6){6:3},d0 ;get dest reg no 156 1.3.4.2 wiz bclr.b d0,FPR_DIRTY_BITS(a6) ;clr dest dirty bit 157 1.3.4.2 wiz bsr.l b1238_fix ;test for bug1238 case 158 1.3.4.2 wiz 159 1.3.4.2 wiz move.l USER_FPSR(a6),FPSR_SHADOW(a6) 160 1.3.4.2 wiz or.l #sx_mask,E_BYTE(a6) 161 1.3.4.2 wiz movem.l USER_DA(a6),d0-d1/a0-a1 162 1.3.4.2 wiz fmovem.x USER_FP0(a6),fp0-fp3 163 1.3.4.2 wiz fmovem.l USER_FPCR(a6),fpcr/fpsr/fpiar 164 1.3.4.2 wiz frestore (a7)+ 165 1.3.4.2 wiz unlk a6 166 1.3.4.2 wiz bra.l fpsp_done 167 1.3.4.2 wiz e1_set: 168 1.3.4.2 wiz movem.l USER_DA(a6),d0-d1/a0-a1 169 1.3.4.2 wiz fmovem.x USER_FP0(a6),fp0-fp3 170 1.3.4.2 wiz fmovem.l USER_FPCR(a6),fpcr/fpsr/fpiar 171 1.3.4.2 wiz unlk a6 172 1.3.4.2 wiz bra.l fpsp_done 173 1.3.4.2 wiz 174 1.3.4.2 wiz * 175 1.3.4.2 wiz * ovf_adj 176 1.3.4.2 wiz * 177 1.3.4.2 wiz ovf_adj: 178 1.3.4.2 wiz * 179 1.3.4.2 wiz * Have a0 point to the correct operand. 180 1.3.4.2 wiz * 181 1.3.4.2 wiz btst.b #E3,E_BYTE(a6) ;test E3 bit 182 1.3.4.2 wiz beq.b ovf_e1 183 1.3.4.2 wiz 184 1.3.4.2 wiz lea WBTEMP(a6),a0 185 1.3.4.2 wiz bra.b ovf_com 186 1.3.4.2 wiz ovf_e1: 187 1.3.4.2 wiz lea ETEMP(a6),a0 188 1.3.4.2 wiz 189 1.3.4.2 wiz ovf_com: 190 1.3.4.2 wiz bclr.b #sign_bit,LOCAL_EX(a0) 191 1.3.4.2 wiz sne LOCAL_SGN(a0) 192 1.3.4.2 wiz 193 1.3.4.2 wiz bsr.l g_opcls ;returns opclass in d0 194 1.3.4.2 wiz cmpi.w #3,d0 ;check for opclass3 195 1.3.4.2 wiz bne.b not_opc011 196 1.3.4.2 wiz 197 1.3.4.2 wiz * 198 1.3.4.2 wiz * FPSR_CC is saved and restored because ovf_r_x3 affects it. The 199 1.3.4.2 wiz * CCs are defined to be 'not affected' for the opclass3 instruction. 200 1.3.4.2 wiz * 201 1.3.4.2 wiz move.b FPSR_CC(a6),L_SCR1(a6) 202 1.3.4.2 wiz bsr.l ovf_r_x3 ;returns a0 pointing to result 203 1.3.4.2 wiz move.b L_SCR1(a6),FPSR_CC(a6) 204 1.3.4.2 wiz bra.l store ;stores to memory or register 205 1.3.4.2 wiz 206 1.3.4.2 wiz not_opc011: 207 1.3.4.2 wiz bsr.l ovf_r_x2 ;returns a0 pointing to result 208 1.3.4.2 wiz bra.l store ;stores to memory or register 209 1.3.4.2 wiz 210 1.3.4.2 wiz end 211
Indexes created Thu Oct 30 16:09:53 GMT 2025