x_ovfl.sa revision 1.1
1 * MOTOROLA MICROPROCESSOR & MEMORY TECHNOLOGY GROUP 2 * M68000 Hi-Performance Microprocessor Division 3 * M68040 Software Package 4 * 5 * M68040 Software Package Copyright (c) 1993, 1994 Motorola Inc. 6 * All rights reserved. 7 * 8 * THE SOFTWARE is provided on an "AS IS" basis and without warranty. 9 * To the maximum extent permitted by applicable law, 10 * MOTOROLA DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, 11 * INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A 12 * PARTICULAR PURPOSE and any warranty against infringement with 13 * regard to the SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF) 14 * and any accompanying written materials. 15 * 16 * To the maximum extent permitted by applicable law, 17 * IN NO EVENT SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER 18 * (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS 19 * PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR 20 * OTHER PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE 21 * SOFTWARE. Motorola assumes no responsibility for the maintenance 22 * and support of the SOFTWARE. 23 * 24 * You are hereby granted a copyright license to use, modify, and 25 * distribute the SOFTWARE so long as this entire notice is retained 26 * without alteration in any modified and/or redistributed versions, 27 * and that such modified versions are clearly identified as such. 28 * No licenses are granted by implication, estoppel or otherwise 29 * under any patents or trademarks of Motorola, Inc. 30 31 * 32 * x_ovfl.sa 3.5 7/1/91 33 * 34 * fpsp_ovfl --- FPSP handler for overflow exception 35 * 36 * Overflow occurs when a floating-point intermediate result is 37 * too large to be represented in a floating-point data register, 38 * or when storing to memory, the contents of a floating-point 39 * data register are too large to be represented in the 40 * destination format. 41 * 42 * Trap disabled results 43 * 44 * If the instruction is move_out, then garbage is stored in the 45 * destination. If the instruction is not move_out, then the 46 * destination is not affected. For 68881 compatibility, the 47 * following values should be stored at the destination, based 48 * on the current rounding mode: 49 * 50 * RN Infinity with the sign of the intermediate result. 51 * RZ Largest magnitude number, with the sign of the 52 * intermediate result. 53 * RM For pos overflow, the largest pos number. For neg overflow, 54 * -infinity 55 * RP For pos overflow, +infinity. For neg overflow, the largest 56 * neg number 57 * 58 * Trap enabled results 59 * All trap disabled code applies. In addition the exceptional 60 * operand needs to be made available to the users exception handler 61 * with a bias of $6000 subtracted from the exponent. 62 * 63 64 X_OVFL IDNT 2,1 Motorola 040 Floating Point Software Package 65 66 section 8 67 68 include fpsp.h 69 70 xref ovf_r_x2 71 xref ovf_r_x3 72 xref store 73 xref real_ovfl 74 xref real_inex 75 xref fpsp_done 76 xref g_opcls 77 xref b1238_fix 78 79 xdef fpsp_ovfl 80 fpsp_ovfl: 81 link a6,#-LOCAL_SIZE 82 fsave -(a7) 83 movem.l d0-d1/a0-a1,USER_DA(a6) 84 fmovem.x fp0-fp3,USER_FP0(a6) 85 fmovem.l fpcr/fpsr/fpiar,USER_FPCR(a6) 86 87 * 88 * The 040 doesn't set the AINEX bit in the FPSR, the following 89 * line temporarily rectifies this error. 90 * 91 bset.b #ainex_bit,FPSR_AEXCEPT(a6) 92 * 93 bsr.l ovf_adj ;denormalize, round & store interm op 94 * 95 * if overflow traps not enabled check for inexact exception 96 * 97 btst.b #ovfl_bit,FPCR_ENABLE(a6) 98 beq.b ck_inex 99 * 100 btst.b #E3,E_BYTE(a6) 101 beq.b no_e3_1 102 bfextu CMDREG3B(a6){6:3},d0 ;get dest reg no 103 bclr.b d0,FPR_DIRTY_BITS(a6) ;clr dest dirty bit 104 bsr.l b1238_fix 105 move.l USER_FPSR(a6),FPSR_SHADOW(a6) 106 or.l #sx_mask,E_BYTE(a6) 107 no_e3_1: 108 movem.l USER_DA(a6),d0-d1/a0-a1 109 fmovem.x USER_FP0(a6),fp0-fp3 110 fmovem.l USER_FPCR(a6),fpcr/fpsr/fpiar 111 frestore (a7)+ 112 unlk a6 113 bra.l real_ovfl 114 * 115 * It is possible to have either inex2 or inex1 exceptions with the 116 * ovfl. If the inex enable bit is set in the FPCR, and either 117 * inex2 or inex1 occured, we must clean up and branch to the 118 * real inex handler. 119 * 120 ck_inex: 121 * move.b FPCR_ENABLE(a6),d0 122 * and.b FPSR_EXCEPT(a6),d0 123 * andi.b #$3,d0 124 btst.b #inex2_bit,FPCR_ENABLE(a6) 125 beq.b ovfl_exit 126 * 127 * Inexact enabled and reported, and we must take an inexact exception. 128 * 129 take_inex: 130 btst.b #E3,E_BYTE(a6) 131 beq.b no_e3_2 132 bfextu CMDREG3B(a6){6:3},d0 ;get dest reg no 133 bclr.b d0,FPR_DIRTY_BITS(a6) ;clr dest dirty bit 134 bsr.l b1238_fix 135 move.l USER_FPSR(a6),FPSR_SHADOW(a6) 136 or.l #sx_mask,E_BYTE(a6) 137 no_e3_2: 138 move.b #INEX_VEC,EXC_VEC+1(a6) 139 movem.l USER_DA(a6),d0-d1/a0-a1 140 fmovem.x USER_FP0(a6),fp0-fp3 141 fmovem.l USER_FPCR(a6),fpcr/fpsr/fpiar 142 frestore (a7)+ 143 unlk a6 144 bra.l real_inex 145 146 ovfl_exit: 147 bclr.b #E3,E_BYTE(a6) ;test and clear E3 bit 148 beq.b e1_set 149 * 150 * Clear dirty bit on dest resister in the frame before branching 151 * to b1238_fix. 152 * 153 bfextu CMDREG3B(a6){6:3},d0 ;get dest reg no 154 bclr.b d0,FPR_DIRTY_BITS(a6) ;clr dest dirty bit 155 bsr.l b1238_fix ;test for bug1238 case 156 157 move.l USER_FPSR(a6),FPSR_SHADOW(a6) 158 or.l #sx_mask,E_BYTE(a6) 159 movem.l USER_DA(a6),d0-d1/a0-a1 160 fmovem.x USER_FP0(a6),fp0-fp3 161 fmovem.l USER_FPCR(a6),fpcr/fpsr/fpiar 162 frestore (a7)+ 163 unlk a6 164 bra.l fpsp_done 165 e1_set: 166 movem.l USER_DA(a6),d0-d1/a0-a1 167 fmovem.x USER_FP0(a6),fp0-fp3 168 fmovem.l USER_FPCR(a6),fpcr/fpsr/fpiar 169 unlk a6 170 bra.l fpsp_done 171 172 * 173 * ovf_adj 174 * 175 ovf_adj: 176 * 177 * Have a0 point to the correct operand. 178 * 179 btst.b #E3,E_BYTE(a6) ;test E3 bit 180 beq.b ovf_e1 181 182 lea WBTEMP(a6),a0 183 bra.b ovf_com 184 ovf_e1: 185 lea ETEMP(a6),a0 186 187 ovf_com: 188 bclr.b #sign_bit,LOCAL_EX(a0) 189 sne LOCAL_SGN(a0) 190 191 bsr.l g_opcls ;returns opclass in d0 192 cmpi.w #3,d0 ;check for opclass3 193 bne.b not_opc011 194 195 * 196 * FPSR_CC is saved and restored because ovf_r_x3 affects it. The 197 * CCs are defined to be 'not affected' for the opclass3 instruction. 198 * 199 move.b FPSR_CC(a6),L_SCR1(a6) 200 bsr.l ovf_r_x3 ;returns a0 pointing to result 201 move.b L_SCR1(a6),FPSR_CC(a6) 202 bra.l store ;stores to memory or register 203 204 not_opc011: 205 bsr.l ovf_r_x2 ;returns a0 pointing to result 206 bra.l store ;stores to memory or register 207 208 end 209
Indexes created Wed Oct 29 18:09:52 GMT 2025