cacheops_20.h revision 1.7 1 /* $NetBSD: cacheops_20.h,v 1.7 2005/12/24 20:07:15 perry Exp $ */
2
3 /*-
4 * Copyright (c) 1997 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Leo Weppelman
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 * must display the following acknowledgement:
20 * This product includes software developed by the NetBSD
21 * Foundation, Inc. and its contributors.
22 * 4. Neither the name of The NetBSD Foundation nor the names of its
23 * contributors may be used to endorse or promote products derived
24 * from this software without specific prior written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36 * POSSIBILITY OF SUCH DAMAGE.
37 */
38
39 /*
40 * Invalidate entire TLB.
41 */
42 static inline void __attribute__((__unused__))
43 TBIA_20(void)
44 {
45 __asm volatile (" pflusha");
46 }
47
48 /*
49 * Invalidate any TLB entry for given VA (TB Invalidate Single)
50 */
51 static inline void __attribute__((__unused__))
52 TBIS_20(vaddr_t va)
53 {
54
55 __asm volatile (" pflushs #0,#0,%0@" : : "a" (va) );
56 }
57
58 /*
59 * Invalidate supervisor side of TLB
60 */
61 static inline void __attribute__((__unused__))
62 TBIAS_20(void)
63 {
64 __asm volatile (" pflushs #4,#4");
65 }
66
67 /*
68 * Invalidate user side of TLB
69 */
70 static inline void __attribute__((__unused__))
71 TBIAU_20(void)
72 {
73 __asm volatile (" pflushs #0,#4;");
74 }
75
76 /*
77 * Invalidate instruction cache
78 */
79 static inline void __attribute__((__unused__))
80 ICIA_20(void)
81 {
82 __asm volatile (" movc %0,%%cacr;" : : "d" (IC_CLEAR));
83 }
84
85 static inline void __attribute__((__unused__))
86 ICPA_20(void)
87 {
88 __asm volatile (" movc %0,%%cacr;" : : "d" (IC_CLEAR));
89 }
90
91 /*
92 * Invalidate data cache.
93 * NOTE: we do not flush 68030/20 on-chip cache as there are no aliasing
94 * problems with DC_WA. The only cases we have to worry about are context
95 * switch and TLB changes, both of which are handled "in-line" in resume
96 * and TBI*.
97 */
98 #define DCIA_20()
99 #define DCIS_20()
100 #define DCIU_20()
101 #define DCIAS_20(va)
102 #define DCFA_20()
103 #define DCPA_20()
104
105 static inline void __attribute__((__unused__))
106 PCIA_20(void)
107 {
108 __asm volatile (" movc %0,%%cacr;" : : "d" (DC_CLEAR));
109 }
110