cpu.h revision 1.14 1 1.14 rmind /* $NetBSD: cpu.h,v 1.14 2011/02/08 20:20:16 rmind Exp $ */
2 1.1 thorpej
3 1.1 thorpej /*
4 1.14 rmind * Copyright (c) 1988 University of Utah.
5 1.1 thorpej * Copyright (c) 1982, 1990, 1993
6 1.1 thorpej * The Regents of the University of California. All rights reserved.
7 1.10 agc *
8 1.10 agc * This code is derived from software contributed to Berkeley by
9 1.10 agc * the Systems Programming Group of the University of Utah Computer
10 1.10 agc * Science Department.
11 1.10 agc *
12 1.10 agc * Redistribution and use in source and binary forms, with or without
13 1.10 agc * modification, are permitted provided that the following conditions
14 1.10 agc * are met:
15 1.10 agc * 1. Redistributions of source code must retain the above copyright
16 1.10 agc * notice, this list of conditions and the following disclaimer.
17 1.10 agc * 2. Redistributions in binary form must reproduce the above copyright
18 1.10 agc * notice, this list of conditions and the following disclaimer in the
19 1.10 agc * documentation and/or other materials provided with the distribution.
20 1.10 agc * 3. Neither the name of the University nor the names of its contributors
21 1.10 agc * may be used to endorse or promote products derived from this software
22 1.10 agc * without specific prior written permission.
23 1.10 agc *
24 1.10 agc * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
25 1.10 agc * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 1.10 agc * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 1.10 agc * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
28 1.10 agc * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 1.10 agc * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
30 1.10 agc * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31 1.10 agc * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32 1.10 agc * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33 1.10 agc * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 1.10 agc * SUCH DAMAGE.
35 1.10 agc *
36 1.10 agc * from: Utah $Hdr: cpu.h 1.16 91/03/25$
37 1.10 agc *
38 1.10 agc * @(#)cpu.h 8.4 (Berkeley) 1/5/94
39 1.10 agc */
40 1.1 thorpej
41 1.1 thorpej #ifndef _M68K_CPU_H_
42 1.1 thorpej #define _M68K_CPU_H_
43 1.1 thorpej
44 1.1 thorpej /*
45 1.1 thorpej * Exported definitions common to Motorola m68k-based ports.
46 1.1 thorpej *
47 1.1 thorpej * Note that are some port-specific definitions here, such as
48 1.1 thorpej * HP and Sun MMU types. These facilitate adding very small
49 1.1 thorpej * amounts of port-specific code to what would otherwise be
50 1.1 thorpej * identical. The is especially true in the case of the HP
51 1.1 thorpej * and other m68k pmaps.
52 1.1 thorpej *
53 1.1 thorpej * Individual ports are expected to define the following CPP symbols
54 1.1 thorpej * in <machine/cpu.h> to enable conditional code:
55 1.1 thorpej *
56 1.1 thorpej * M68K_MMU_MOTOROLA Machine has a Motorola MMU (incl.
57 1.1 thorpej * 68851, 68030, 68040, 68060)
58 1.1 thorpej *
59 1.1 thorpej * M68K_MMU_HP Machine has an HP MMU.
60 1.1 thorpej *
61 1.1 thorpej * Note also that while m68k-generic code conditionalizes on the
62 1.8 wiz * M68K_MMU_HP CPP symbol, none of the HP MMU definitions are in this
63 1.1 thorpej * file (since none are used in otherwise sharable code).
64 1.1 thorpej */
65 1.1 thorpej
66 1.1 thorpej /*
67 1.5 gwr * XXX The remaining contents of this file should be split out
68 1.5 gwr * XXX into separate files (like m68k.h) and then this file
69 1.5 gwr * XXX should go away. Furthermore, most of the stuff defined
70 1.5 gwr * XXX here does NOT belong in <machine/cpu.h>, and the ports
71 1.5 gwr * XXX using this file should remove <m68k/cpu.h> from there.
72 1.1 thorpej */
73 1.1 thorpej
74 1.5 gwr #include <m68k/m68k.h>
75 1.5 gwr
76 1.5 gwr /* XXX - Move this stuff into <m68k/mmu030.h> maybe? */
77 1.1 thorpej
78 1.1 thorpej /*
79 1.1 thorpej * 68851 and 68030 MMU
80 1.1 thorpej */
81 1.1 thorpej #define PMMU_LVLMASK 0x0007
82 1.1 thorpej #define PMMU_INV 0x0400
83 1.1 thorpej #define PMMU_WP 0x0800
84 1.1 thorpej #define PMMU_ALV 0x1000
85 1.1 thorpej #define PMMU_SO 0x2000
86 1.1 thorpej #define PMMU_LV 0x4000
87 1.1 thorpej #define PMMU_BE 0x8000
88 1.1 thorpej #define PMMU_FAULT (PMMU_WP|PMMU_INV)
89 1.1 thorpej
90 1.5 gwr /* XXX - Move this stuff into <m68k/mmu040.h> maybe? */
91 1.5 gwr
92 1.1 thorpej /*
93 1.1 thorpej * 68040 MMU
94 1.1 thorpej */
95 1.1 thorpej #define MMU40_RES 0x001
96 1.1 thorpej #define MMU40_TTR 0x002
97 1.1 thorpej #define MMU40_WP 0x004
98 1.1 thorpej #define MMU40_MOD 0x010
99 1.1 thorpej #define MMU40_CMMASK 0x060
100 1.1 thorpej #define MMU40_SUP 0x080
101 1.1 thorpej #define MMU40_U0 0x100
102 1.1 thorpej #define MMU40_U1 0x200
103 1.1 thorpej #define MMU40_GLB 0x400
104 1.1 thorpej #define MMU40_BE 0x800
105 1.1 thorpej
106 1.5 gwr /* XXX - Move this stuff into <m68k/fcode.h> maybe? */
107 1.5 gwr
108 1.1 thorpej /* 680X0 function codes */
109 1.1 thorpej #define FC_USERD 1 /* user data space */
110 1.1 thorpej #define FC_USERP 2 /* user program space */
111 1.1 thorpej #define FC_PURGE 3 /* HPMMU: clear TLB entries */
112 1.1 thorpej #define FC_SUPERD 5 /* supervisor data space */
113 1.1 thorpej #define FC_SUPERP 6 /* supervisor program space */
114 1.1 thorpej #define FC_CPU 7 /* CPU space */
115 1.1 thorpej
116 1.5 gwr /* XXX - Move this stuff into <m68k/cacr.h> maybe? */
117 1.5 gwr
118 1.1 thorpej /* fields in the 68020 cache control register */
119 1.1 thorpej #define IC_ENABLE 0x0001 /* enable instruction cache */
120 1.1 thorpej #define IC_FREEZE 0x0002 /* freeze instruction cache */
121 1.1 thorpej #define IC_CE 0x0004 /* clear instruction cache entry */
122 1.1 thorpej #define IC_CLR 0x0008 /* clear entire instruction cache */
123 1.1 thorpej
124 1.1 thorpej /* additional fields in the 68030 cache control register */
125 1.1 thorpej #define IC_BE 0x0010 /* instruction burst enable */
126 1.1 thorpej #define DC_ENABLE 0x0100 /* data cache enable */
127 1.1 thorpej #define DC_FREEZE 0x0200 /* data cache freeze */
128 1.1 thorpej #define DC_CE 0x0400 /* clear data cache entry */
129 1.1 thorpej #define DC_CLR 0x0800 /* clear entire data cache */
130 1.1 thorpej #define DC_BE 0x1000 /* data burst enable */
131 1.1 thorpej #define DC_WA 0x2000 /* write allocate */
132 1.1 thorpej
133 1.1 thorpej /* fields in the 68040 cache control register */
134 1.1 thorpej #define IC40_ENABLE 0x00008000 /* instruction cache enable bit */
135 1.1 thorpej #define DC40_ENABLE 0x80000000 /* data cache enable bit */
136 1.1 thorpej
137 1.1 thorpej /* additional fields in the 68060 cache control register */
138 1.1 thorpej #define DC60_NAD 0x40000000 /* no allocate mode, data cache */
139 1.1 thorpej #define DC60_ESB 0x20000000 /* enable store buffer */
140 1.1 thorpej #define DC60_DPI 0x10000000 /* disable CPUSH invalidation */
141 1.1 thorpej #define DC60_FOC 0x08000000 /* four kB data cache mode (else 8) */
142 1.1 thorpej
143 1.1 thorpej #define IC60_EBC 0x00800000 /* enable branch cache */
144 1.1 thorpej #define IC60_CABC 0x00400000 /* clear all branch cache entries */
145 1.1 thorpej #define IC60_CUBC 0x00200000 /* clear user branch cache entries */
146 1.1 thorpej
147 1.1 thorpej #define IC60_NAI 0x00004000 /* no allocate mode, instr. cache */
148 1.1 thorpej #define IC60_FIC 0x00002000 /* four kB instr. cache (else 8) */
149 1.1 thorpej
150 1.1 thorpej #define CACHE_ON (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE)
151 1.1 thorpej #define CACHE_OFF (DC_CLR|IC_CLR)
152 1.1 thorpej #define CACHE_CLR (CACHE_ON)
153 1.1 thorpej #define IC_CLEAR (DC_WA|DC_BE|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE)
154 1.1 thorpej #define DC_CLEAR (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_ENABLE)
155 1.1 thorpej
156 1.1 thorpej #define CACHE40_ON (IC40_ENABLE|DC40_ENABLE)
157 1.1 thorpej #define CACHE40_OFF (0x00000000)
158 1.1 thorpej
159 1.1 thorpej #define CACHE60_ON (CACHE40_ON|IC60_CABC|IC60_EBC|DC60_ESB)
160 1.1 thorpej #define CACHE60_OFF (CACHE40_OFF|IC60_CABC)
161 1.6 scw
162 1.13 he #if defined(_KERNEL) || defined(_KMEMUSER)
163 1.12 matt #include <sys/cpu_data.h>
164 1.12 matt
165 1.12 matt struct cpu_info {
166 1.12 matt struct cpu_data ci_data; /* MI per-cpu data */
167 1.12 matt cpuid_t ci_cpuid;
168 1.12 matt int ci_mtx_count;
169 1.12 matt int ci_mtx_oldspl;
170 1.12 matt volatile int ci_want_resched;
171 1.12 matt volatile int ci_idepth;
172 1.12 matt };
173 1.12 matt #endif /* _KERNEL || _KMEMUSER */
174 1.12 matt
175 1.6 scw #ifdef _KERNEL
176 1.12 matt extern struct cpu_info cpu_info_store;
177 1.12 matt
178 1.12 matt struct proc;
179 1.12 matt void cpu_proc_fork(struct proc *, struct proc *);
180 1.12 matt
181 1.12 matt #define curcpu() (&cpu_info_store)
182 1.12 matt
183 1.6 scw /*
184 1.12 matt * definitions of cpu-dependent requirements
185 1.12 matt * referenced in generic code
186 1.6 scw */
187 1.12 matt #define cpu_number() 0
188 1.9 thorpej
189 1.9 thorpej #define LWP_PC(l) (((struct trapframe *)((l)->l_md.md_regs))->tf_pc)
190 1.6 scw #endif /* _KERNEL */
191 1.1 thorpej
192 1.1 thorpej #endif /* _M68K_CPU_H_ */
193