cpu.h revision 1.14
1 /* $NetBSD: cpu.h,v 1.14 2011/02/08 20:20:16 rmind Exp $ */ 2 3 /* 4 * Copyright (c) 1988 University of Utah. 5 * Copyright (c) 1982, 1990, 1993 6 * The Regents of the University of California. All rights reserved. 7 * 8 * This code is derived from software contributed to Berkeley by 9 * the Systems Programming Group of the University of Utah Computer 10 * Science Department. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * from: Utah $Hdr: cpu.h 1.16 91/03/25$ 37 * 38 * @(#)cpu.h 8.4 (Berkeley) 1/5/94 39 */ 40 41 #ifndef _M68K_CPU_H_ 42 #define _M68K_CPU_H_ 43 44 /* 45 * Exported definitions common to Motorola m68k-based ports. 46 * 47 * Note that are some port-specific definitions here, such as 48 * HP and Sun MMU types. These facilitate adding very small 49 * amounts of port-specific code to what would otherwise be 50 * identical. The is especially true in the case of the HP 51 * and other m68k pmaps. 52 * 53 * Individual ports are expected to define the following CPP symbols 54 * in <machine/cpu.h> to enable conditional code: 55 * 56 * M68K_MMU_MOTOROLA Machine has a Motorola MMU (incl. 57 * 68851, 68030, 68040, 68060) 58 * 59 * M68K_MMU_HP Machine has an HP MMU. 60 * 61 * Note also that while m68k-generic code conditionalizes on the 62 * M68K_MMU_HP CPP symbol, none of the HP MMU definitions are in this 63 * file (since none are used in otherwise sharable code). 64 */ 65 66 /* 67 * XXX The remaining contents of this file should be split out 68 * XXX into separate files (like m68k.h) and then this file 69 * XXX should go away. Furthermore, most of the stuff defined 70 * XXX here does NOT belong in <machine/cpu.h>, and the ports 71 * XXX using this file should remove <m68k/cpu.h> from there. 72 */ 73 74 #include <m68k/m68k.h> 75 76 /* XXX - Move this stuff into <m68k/mmu030.h> maybe? */ 77 78 /* 79 * 68851 and 68030 MMU 80 */ 81 #define PMMU_LVLMASK 0x0007 82 #define PMMU_INV 0x0400 83 #define PMMU_WP 0x0800 84 #define PMMU_ALV 0x1000 85 #define PMMU_SO 0x2000 86 #define PMMU_LV 0x4000 87 #define PMMU_BE 0x8000 88 #define PMMU_FAULT (PMMU_WP|PMMU_INV) 89 90 /* XXX - Move this stuff into <m68k/mmu040.h> maybe? */ 91 92 /* 93 * 68040 MMU 94 */ 95 #define MMU40_RES 0x001 96 #define MMU40_TTR 0x002 97 #define MMU40_WP 0x004 98 #define MMU40_MOD 0x010 99 #define MMU40_CMMASK 0x060 100 #define MMU40_SUP 0x080 101 #define MMU40_U0 0x100 102 #define MMU40_U1 0x200 103 #define MMU40_GLB 0x400 104 #define MMU40_BE 0x800 105 106 /* XXX - Move this stuff into <m68k/fcode.h> maybe? */ 107 108 /* 680X0 function codes */ 109 #define FC_USERD 1 /* user data space */ 110 #define FC_USERP 2 /* user program space */ 111 #define FC_PURGE 3 /* HPMMU: clear TLB entries */ 112 #define FC_SUPERD 5 /* supervisor data space */ 113 #define FC_SUPERP 6 /* supervisor program space */ 114 #define FC_CPU 7 /* CPU space */ 115 116 /* XXX - Move this stuff into <m68k/cacr.h> maybe? */ 117 118 /* fields in the 68020 cache control register */ 119 #define IC_ENABLE 0x0001 /* enable instruction cache */ 120 #define IC_FREEZE 0x0002 /* freeze instruction cache */ 121 #define IC_CE 0x0004 /* clear instruction cache entry */ 122 #define IC_CLR 0x0008 /* clear entire instruction cache */ 123 124 /* additional fields in the 68030 cache control register */ 125 #define IC_BE 0x0010 /* instruction burst enable */ 126 #define DC_ENABLE 0x0100 /* data cache enable */ 127 #define DC_FREEZE 0x0200 /* data cache freeze */ 128 #define DC_CE 0x0400 /* clear data cache entry */ 129 #define DC_CLR 0x0800 /* clear entire data cache */ 130 #define DC_BE 0x1000 /* data burst enable */ 131 #define DC_WA 0x2000 /* write allocate */ 132 133 /* fields in the 68040 cache control register */ 134 #define IC40_ENABLE 0x00008000 /* instruction cache enable bit */ 135 #define DC40_ENABLE 0x80000000 /* data cache enable bit */ 136 137 /* additional fields in the 68060 cache control register */ 138 #define DC60_NAD 0x40000000 /* no allocate mode, data cache */ 139 #define DC60_ESB 0x20000000 /* enable store buffer */ 140 #define DC60_DPI 0x10000000 /* disable CPUSH invalidation */ 141 #define DC60_FOC 0x08000000 /* four kB data cache mode (else 8) */ 142 143 #define IC60_EBC 0x00800000 /* enable branch cache */ 144 #define IC60_CABC 0x00400000 /* clear all branch cache entries */ 145 #define IC60_CUBC 0x00200000 /* clear user branch cache entries */ 146 147 #define IC60_NAI 0x00004000 /* no allocate mode, instr. cache */ 148 #define IC60_FIC 0x00002000 /* four kB instr. cache (else 8) */ 149 150 #define CACHE_ON (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE) 151 #define CACHE_OFF (DC_CLR|IC_CLR) 152 #define CACHE_CLR (CACHE_ON) 153 #define IC_CLEAR (DC_WA|DC_BE|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE) 154 #define DC_CLEAR (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_ENABLE) 155 156 #define CACHE40_ON (IC40_ENABLE|DC40_ENABLE) 157 #define CACHE40_OFF (0x00000000) 158 159 #define CACHE60_ON (CACHE40_ON|IC60_CABC|IC60_EBC|DC60_ESB) 160 #define CACHE60_OFF (CACHE40_OFF|IC60_CABC) 161 162 #if defined(_KERNEL) || defined(_KMEMUSER) 163 #include <sys/cpu_data.h> 164 165 struct cpu_info { 166 struct cpu_data ci_data; /* MI per-cpu data */ 167 cpuid_t ci_cpuid; 168 int ci_mtx_count; 169 int ci_mtx_oldspl; 170 volatile int ci_want_resched; 171 volatile int ci_idepth; 172 }; 173 #endif /* _KERNEL || _KMEMUSER */ 174 175 #ifdef _KERNEL 176 extern struct cpu_info cpu_info_store; 177 178 struct proc; 179 void cpu_proc_fork(struct proc *, struct proc *); 180 181 #define curcpu() (&cpu_info_store) 182 183 /* 184 * definitions of cpu-dependent requirements 185 * referenced in generic code 186 */ 187 #define cpu_number() 0 188 189 #define LWP_PC(l) (((struct trapframe *)((l)->l_md.md_regs))->tf_pc) 190 #endif /* _KERNEL */ 191 192 #endif /* _M68K_CPU_H_ */ 193
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