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cpu.h revision 1.20 
      1 /*	$NetBSD: cpu.h,v 1.20 2024/01/18 14:39:06 thorpej Exp $	*/
      2 
      3 /*
      4  * Copyright (c) 1988 University of Utah.
      5  * Copyright (c) 1982, 1990, 1993
      6  *	The Regents of the University of California.  All rights reserved.
      7  *
      8  * This code is derived from software contributed to Berkeley by
      9  * the Systems Programming Group of the University of Utah Computer
     10  * Science Department.
     11  *
     12  * Redistribution and use in source and binary forms, with or without
     13  * modification, are permitted provided that the following conditions
     14  * are met:
     15  * 1. Redistributions of source code must retain the above copyright
     16  *    notice, this list of conditions and the following disclaimer.
     17  * 2. Redistributions in binary form must reproduce the above copyright
     18  *    notice, this list of conditions and the following disclaimer in the
     19  *    documentation and/or other materials provided with the distribution.
     20  * 3. Neither the name of the University nor the names of its contributors
     21  *    may be used to endorse or promote products derived from this software
     22  *    without specific prior written permission.
     23  *
     24  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
     25  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     26  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     27  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
     28  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     29  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     30  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     31  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     32  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     33  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     34  * SUCH DAMAGE.
     35  *
     36  * from: Utah $Hdr: cpu.h 1.16 91/03/25$
     37  *
     38  *	@(#)cpu.h	8.4 (Berkeley) 1/5/94
     39  */
     40 
     41 #ifndef _M68K_CPU_H_
     42 #define	_M68K_CPU_H_
     43 
     44 #if defined(_KERNEL_OPT)
     45 #include "opt_m68k_arch.h"	/* XXX Should not do this here. */
     46 #endif
     47 
     48 /*
     49  * Exported definitions common to Motorola m68k-based ports.
     50  *
     51  * Note that are some port-specific definitions here, such as
     52  * HP and Sun MMU types.  These facilitate adding very small
     53  * amounts of port-specific code to what would otherwise be
     54  * identical.  The is especially true in the case of the HP
     55  * and other m68k pmaps.
     56  *
     57  * Individual ports are expected to define the following CPP symbols
     58  * in <machine/cpu.h> to enable conditional code:
     59  *
     60  *	M68K_MMU_MOTOROLA	Machine has a Motorola MMU (incl.
     61  *				68851, 68030, 68040, 68060)
     62  *
     63  *	M68K_MMU_HP		Machine has an HP MMU.
     64  *
     65  * Note also that while m68k-generic code conditionalizes on the
     66  * M68K_MMU_HP CPP symbol, none of the HP MMU definitions are in this
     67  * file (since none are used in otherwise sharable code).
     68  */
     69 
     70 /*
     71  * XXX  The remaining contents of this file should be split out
     72  * XXX  into separate files (like m68k.h) and then this file
     73  * XXX  should go away.  Furthermore, most of the stuff defined
     74  * XXX  here does NOT belong in <machine/cpu.h>, and the ports
     75  * XXX  using this file should remove <m68k/cpu.h> from there.
     76  */
     77 
     78 #include <m68k/m68k.h>
     79 
     80 /* XXX - Move this stuff into <m68k/cacr.h> maybe? */
     81 
     82 /* fields in the 68020 cache control register */
     83 #define	IC_ENABLE	0x0001	/* enable instruction cache */
     84 #define	IC_FREEZE	0x0002	/* freeze instruction cache */
     85 #define	IC_CE		0x0004	/* clear instruction cache entry */
     86 #define	IC_CLR		0x0008	/* clear entire instruction cache */
     87 
     88 /* additional fields in the 68030 cache control register */
     89 #define	IC_BE		0x0010	/* instruction burst enable */
     90 #define	DC_ENABLE	0x0100	/* data cache enable */
     91 #define	DC_FREEZE	0x0200	/* data cache freeze */
     92 #define	DC_CE		0x0400	/* clear data cache entry */
     93 #define	DC_CLR		0x0800	/* clear entire data cache */
     94 #define	DC_BE		0x1000	/* data burst enable */
     95 #define	DC_WA		0x2000	/* write allocate */
     96 
     97 /* fields in the 68040 cache control register */
     98 #define	IC40_ENABLE	0x00008000	/* instruction cache enable bit */
     99 #define	DC40_ENABLE	0x80000000	/* data cache enable bit */
    100 
    101 /* additional fields in the 68060 cache control register */
    102 #define	DC60_NAD	0x40000000	/* no allocate mode, data cache */
    103 #define	DC60_ESB	0x20000000	/* enable store buffer */
    104 #define	DC60_DPI	0x10000000	/* disable CPUSH invalidation */
    105 #define	DC60_FOC	0x08000000	/* four kB data cache mode (else 8) */
    106 
    107 #define	IC60_EBC	0x00800000	/* enable branch cache */
    108 #define IC60_CABC	0x00400000	/* clear all branch cache entries */
    109 #define	IC60_CUBC	0x00200000	/* clear user branch cache entries */
    110 
    111 #define	IC60_NAI	0x00004000	/* no allocate mode, instr. cache */
    112 #define	IC60_FIC	0x00002000	/* four kB instr. cache (else 8) */
    113 
    114 #define	CACHE_ON	(DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE)
    115 #define	CACHE_OFF	(DC_CLR|IC_CLR)
    116 #define	CACHE_CLR	(CACHE_ON)
    117 #define	IC_CLEAR	(DC_WA|DC_BE|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE)
    118 #define	DC_CLEAR	(DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_ENABLE)
    119 
    120 #define	CACHE40_ON	(IC40_ENABLE|DC40_ENABLE)
    121 #define	CACHE40_OFF	(0x00000000)
    122 
    123 #define	CACHE60_ON	(CACHE40_ON|IC60_CABC|IC60_EBC|DC60_ESB)
    124 #define	CACHE60_OFF	(CACHE40_OFF|IC60_CABC)
    125 
    126 #define CACHELINE_SIZE	16
    127 #define CACHELINE_MASK	(CACHELINE_SIZE - 1)
    128 
    129 /* CTL_MACHDEP definitions. (Common to all m68k ports.) */
    130 #define	CPU_CONSDEV		1	/* dev_t: console terminal device */
    131 #define	CPU_ROOT_DEVICE		2	/* string: root device name */
    132 #define	CPU_BOOTED_KERNEL	3	/* string: booted kernel name */
    133 
    134 #if defined(_KERNEL) || defined(_KMEMUSER)
    135 #include <sys/cpu_data.h>
    136 
    137 struct cpu_info {
    138 	struct cpu_data ci_data;	/* MI per-cpu data */
    139 	cpuid_t	ci_cpuid;
    140 	int	ci_mtx_count;
    141 	int	ci_mtx_oldspl;
    142 	volatile int	ci_want_resched;
    143 	volatile int	ci_idepth;
    144 	struct lwp *ci_onproc;		/* current user LWP / kthread */
    145 };
    146 #endif /* _KERNEL || _KMEMUSER */
    147 
    148 #ifdef _KERNEL
    149 extern struct cpu_info cpu_info_store;
    150 
    151 struct	proc;
    152 void	cpu_proc_fork(struct proc *, struct proc *);
    153 
    154 #define	curcpu()	(&cpu_info_store)
    155 
    156 /*
    157  * definitions of cpu-dependent requirements
    158  * referenced in generic code
    159  */
    160 #define cpu_number()			0
    161 
    162 #define LWP_PC(l)	(((struct trapframe *)((l)->l_md.md_regs))->tf_pc)
    163 #endif /* _KERNEL */
    164 
    165 #endif /* _M68K_CPU_H_ */
    166