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db_machdep.h revision 1.7 
      1 /*
      2  * Mach Operating System
      3  * Copyright (c) 1992 Carnegie Mellon University
      4  * All Rights Reserved.
      5  *
      6  * Permission to use, copy, modify and distribute this software and its
      7  * documentation is hereby granted, provided that both the copyright
      8  * notice and this permission notice appear in all copies of the
      9  * software, derivative works or modified versions, and any portions
     10  * thereof, and that both notices appear in supporting documentation.
     11  *
     12  * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
     13  * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
     14  * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
     15  *
     16  * Carnegie Mellon requests users of this software to return to
     17  *
     18  *  Software Distribution Coordinator  or  Software.Distribution (at) CS.CMU.EDU
     19  *  School of Computer Science
     20  *  Carnegie Mellon University
     21  *  Pittsburgh PA 15213-3890
     22  *
     23  * any improvements or extensions that they make and grant Carnegie Mellon
     24  * the rights to redistribute these changes.
     25  */
     26 
     27 /*
     28  * Machine-dependent defines for new kernel debugger.
     29  */
     30 #ifndef	_M68K_DB_MACHDEP_H_
     31 #define	_M68K_DB_MACHDEP_H_
     32 
     33 #include <vm/queue.h>
     34 #include <vm/vm_prot.h>
     35 #include <vm/vm_param.h>
     36 #include <vm/vm_inherit.h>
     37 #include <vm/lock.h>
     38 #include <machine/psl.h>
     39 #include <machine/trap.h>
     40 
     41 typedef	vm_offset_t	db_addr_t;	/* address - unsigned */
     42 typedef	int		db_expr_t;	/* expression - signed */
     43 struct mc68020_saved_state {
     44 	int		d0;		/* data registers */
     45 	int		d1;
     46 	int		d2;
     47 	int		d3;
     48 	int		d4;
     49 	int		d5;
     50 	int		d6;
     51 	int		d7;
     52 	int		a0;		/* address registers */
     53 	int		a1;
     54 	int		a2;
     55 	int		a3;
     56 	int		a4;
     57 	int		a5;
     58 	int		a6;
     59 	int		sp;		/* stack pointer */
     60 	short		empty;
     61 	unsigned short	sr;		/* status register */
     62 	unsigned int	pc;		/* program counter - UNALIGNED!!! */
     63 	unsigned int	stkfmt	: 4;	/* rte stack frame format */
     64 	unsigned int	vector	: 12;	/* vector number */
     65 };
     66 typedef struct mc68020_saved_state db_regs_t;
     67 db_regs_t	ddb_regs;		/* register state */
     68 #define DDB_REGS	(&ddb_regs)
     69 
     70 #define	PC_REGS(regs)	((db_addr_t)(regs)->pc)
     71 
     72 #define	BKPT_INST	0x4e4f		/* breakpoint instruction */
     73 #define	BKPT_SIZE	(2)		/* size of breakpoint inst */
     74 #define	BKPT_SET(inst)	(BKPT_INST)
     75 
     76 #define	FIXUP_PC_AFTER_BREAK	ddb_regs.pc -= 2;
     77 
     78 #define SR_T1 0x8000
     79 #define	db_clear_single_step(regs)	((regs)->sr &= ~SR_T1)
     80 #define	db_set_single_step(regs)	((regs)->sr |=  SR_T1)
     81 
     82 #define	IS_BREAKPOINT_TRAP(type, code)	((type) == T_BREAKPOINT)
     83 #ifdef T_WATCHPOINT
     84 #define	IS_WATCHPOINT_TRAP(type, code)	((type) == T_WATCHPOINT)
     85 #else
     86 #define	IS_WATCHPOINT_TRAP(type, code)	0
     87 #endif
     88 
     89 #define	M_RTS		0xffff0000
     90 #define I_RTS		0x4e750000
     91 #define M_JSR		0xffc00000
     92 #define I_JSR		0x4e800000
     93 #define M_BSR		0xff000000
     94 #define I_BSR		0x61000000
     95 #define	M_RTE		0xffff0000
     96 #define	I_RTE		0x4e730000
     97 
     98 #define	inst_trap_return(ins)	(((ins)&M_RTE) == I_RTE)
     99 #define	inst_return(ins)	(((ins)&M_RTS) == I_RTS)
    100 #define	inst_call(ins)		(((ins)&M_JSR) == I_JSR || \
    101 				 ((ins)&M_BSR) == I_BSR)
    102 #define inst_load(ins)		0
    103 #define inst_store(ins)		0
    104 
    105 #endif	/* _M68K_DB_MACHDEP_H_ */
    106