1 /* 2 * Mach Operating System 3 * Copyright (c) 1992 Carnegie Mellon University 4 * All Rights Reserved. 5 * 6 * Permission to use, copy, modify and distribute this software and its 7 * documentation is hereby granted, provided that both the copyright 8 * notice and this permission notice appear in all copies of the 9 * software, derivative works or modified versions, and any portions 10 * thereof, and that both notices appear in supporting documentation. 11 * 12 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 13 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR 14 * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 15 * 16 * Carnegie Mellon requests users of this software to return to 17 * 18 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 19 * School of Computer Science 20 * Carnegie Mellon University 21 * Pittsburgh PA 15213-3890 22 * 23 * any improvements or extensions that they make and grant Carnegie Mellon 24 * the rights to redistribute these changes. 25 */ 26 27 /* 28 * Machine-dependent defines for new kernel debugger. 29 */ 30 #ifndef _M68K_DB_MACHDEP_H_ 31 #define _M68K_DB_MACHDEP_H_ 32 33 #include <vm/queue.h> 34 #include <vm/vm_prot.h> 35 #include <vm/vm_param.h> 36 #include <vm/vm_inherit.h> 37 #include <vm/lock.h> 38 #include <machine/psl.h> 39 #include <machine/trap.h> 40 41 #define BYTE_MSF 42 43 typedef vm_offset_t db_addr_t; /* address - unsigned */ 44 typedef int db_expr_t; /* expression - signed */ 45 struct mc68020_saved_state { 46 int d0; /* data registers */ 47 int d1; 48 int d2; 49 int d3; 50 int d4; 51 int d5; 52 int d6; 53 int d7; 54 int a0; /* address registers */ 55 int a1; 56 int a2; 57 int a3; 58 int a4; 59 int a5; 60 int a6; 61 int sp; /* stack pointer */ 62 short empty; 63 unsigned short sr; /* status register */ 64 unsigned int pc; /* program counter - UNALIGNED!!! */ 65 unsigned int stkfmt : 4; /* rte stack frame format */ 66 unsigned int vector : 12; /* vector number */ 67 }; 68 typedef struct mc68020_saved_state db_regs_t; 69 db_regs_t ddb_regs; /* register state */ 70 #define DDB_REGS (&ddb_regs) 71 72 #define PC_REGS(regs) ((db_addr_t)(regs)->pc) 73 74 #define BKPT_INST 0x4e4f /* breakpoint instruction */ 75 #define BKPT_SIZE (2) /* size of breakpoint inst */ 76 #define BKPT_SET(inst) (BKPT_INST) 77 78 #define FIXUP_PC_AFTER_BREAK ddb_regs.pc -= 2; 79 80 #define SR_T1 0x8000 81 #define db_clear_single_step(regs) ((regs)->sr &= ~SR_T1) 82 #define db_set_single_step(regs) ((regs)->sr |= SR_T1) 83 84 #define IS_BREAKPOINT_TRAP(type, code) ((type) == T_BREAKPOINT) 85 #ifdef T_WATCHPOINT 86 #define IS_WATCHPOINT_TRAP(type, code) ((type) == T_WATCHPOINT) 87 #else 88 #define IS_WATCHPOINT_TRAP(type, code) 0 89 #endif 90 91 #define M_RTS 0xffff0000 92 #define I_RTS 0x4e750000 93 #define M_JSR 0xffc00000 94 #define I_JSR 0x4e800000 95 #define M_BSR 0xff000000 96 #define I_BSR 0x61000000 97 #define M_RTE 0xffff0000 98 #define I_RTE 0x4e730000 99 100 #define inst_trap_return(ins) (((ins)&M_RTE) == I_RTE) 101 #define inst_return(ins) (((ins)&M_RTS) == I_RTS) 102 #define inst_call(ins) (((ins)&M_JSR) == I_JSR || \ 103 ((ins)&M_BSR) == I_BSR) 104 #define inst_load(ins) 0 105 #define inst_store(ins) 0 106 107 #endif /* _M68K_DB_MACHDEP_H_ */ 108