pte_coldfire.h revision 1.2.8.2
1 1.2.8.2 tls /* $NetBSD: pte_coldfire.h,v 1.2.8.2 2014/08/20 00:03:10 tls Exp $ */ 2 1.2.8.2 tls /*- 3 1.2.8.2 tls * Copyright (c) 2013 The NetBSD Foundation, Inc. 4 1.2.8.2 tls * All rights reserved. 5 1.2.8.2 tls * 6 1.2.8.2 tls * This code is derived from software contributed to The NetBSD Foundation 7 1.2.8.2 tls * by Matt Thomas of 3am Software Foundry. 8 1.2.8.2 tls * 9 1.2.8.2 tls * Redistribution and use in source and binary forms, with or without 10 1.2.8.2 tls * modification, are permitted provided that the following conditions 11 1.2.8.2 tls * are met: 12 1.2.8.2 tls * 1. Redistributions of source code must retain the above copyright 13 1.2.8.2 tls * notice, this list of conditions and the following disclaimer. 14 1.2.8.2 tls * 2. Redistributions in binary form must reproduce the above copyright 15 1.2.8.2 tls * notice, this list of conditions and the following disclaimer in the 16 1.2.8.2 tls * documentation and/or other materials provided with the distribution. 17 1.2.8.2 tls * 18 1.2.8.2 tls * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 19 1.2.8.2 tls * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 20 1.2.8.2 tls * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 21 1.2.8.2 tls * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 22 1.2.8.2 tls * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 1.2.8.2 tls * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 1.2.8.2 tls * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 1.2.8.2 tls * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 1.2.8.2 tls * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 1.2.8.2 tls * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 1.2.8.2 tls * POSSIBILITY OF SUCH DAMAGE. 29 1.2.8.2 tls */ 30 1.2.8.2 tls 31 1.2.8.2 tls #ifndef _M68K_PTE_COLDFIRE_H_ 32 1.2.8.2 tls #define _M68K_PTE_COLDFIRE_H_ 33 1.2.8.2 tls 34 1.2.8.2 tls #ifdef __ASSEMBLY__ 35 1.2.8.2 tls #error use assym.h instead 36 1.2.8.2 tls #endif 37 1.2.8.2 tls 38 1.2.8.2 tls #ifndef __BSD_PT_ENTRY_T 39 1.2.8.2 tls #define __BSD_PT_ENTRY_T __uint32_t 40 1.2.8.2 tls typedef __BSD_PT_ENTRY_T pt_entry_t; 41 1.2.8.2 tls #endif 42 1.2.8.2 tls 43 1.2.8.2 tls #define MMUTR_VA __BITS(31,10) // Virtual Address 44 1.2.8.2 tls #define MMUTR_ID __BITS(9,2) // ASID 45 1.2.8.2 tls #define MMUTR_SG __BIT(1) // Shared Global 46 1.2.8.2 tls #define MMUTR_V __BIT(0) // Valid 47 1.2.8.2 tls 48 1.2.8.2 tls #define MMUDR_PA __BITS(31,10) // Physical Address 49 1.2.8.2 tls #define MMUDR_SZ __BITS(9,8) // Entry Size 50 1.2.8.2 tls #define MMUDR_SZ_1MB 0 51 1.2.8.2 tls #define MMUDR_SZ_4KB 1 52 1.2.8.2 tls #define MMUDR_SZ_8KB 2 53 1.2.8.2 tls #define MMUDR_SZ_16MB 3 54 1.2.8.2 tls #define MMUDR_CM __BITS(7,6) // Cache Mode 55 1.2.8.2 tls #define MMUDR_CM_WT 0 // Write-Through 56 1.2.8.2 tls #define MMUDR_CM_WB 1 // Write-Back (Copy-Back) 57 1.2.8.2 tls #define MMUDR_CM_NC 2 // Non-cacheable 58 1.2.8.2 tls #define MMUDR_CM_NCP 2 // Non-cacheable Precise 59 1.2.8.2 tls #define MMUDR_CM_NCI 3 // Non-cacheable Imprecise 60 1.2.8.2 tls #define MMUDR_SP __BIT(5) // Supervisor Protect 61 1.2.8.2 tls #define MMUDR_R __BIT(4) // Read Access 62 1.2.8.2 tls #define MMUDR_W __BIT(3) // Write Access 63 1.2.8.2 tls #define MMUDR_X __BIT(2) // Execute Access 64 1.2.8.2 tls #define MMUDR_LK __BIT(1) // Lock Entry 65 1.2.8.2 tls #define MMUDR_MBZ0 __BIT(0) // Must be zero 66 1.2.8.2 tls 67 1.2.8.2 tls /* 68 1.2.8.2 tls * The PTE basically the contents of MMUDR[31:2] | MMUAR[0]. 69 1.2.8.2 tls * We overload the meaning of MMUDR_LK for indicating wired. 70 1.2.8.2 tls * It will be cleared before writing to the TLB. 71 1.2.8.2 tls */ 72 1.2.8.2 tls 73 1.2.8.2 tls #ifdef _KERNEL 74 1.2.8.2 tls 75 1.2.8.2 tls static inline bool 76 1.2.8.2 tls pte_cached_p(pt_entry_t pt_entry) 77 1.2.8.2 tls { 78 1.2.8.2 tls return (pt_entry & MMUDR_CM_NC) != MMUDR_CM_NC; 79 1.2.8.2 tls } 80 1.2.8.2 tls 81 1.2.8.2 tls static inline bool 82 1.2.8.2 tls pte_modified_p(pt_entry_t pt_entry) 83 1.2.8.2 tls { 84 1.2.8.2 tls return (pt_entry & MMUDR_W) == MMUDR_W; 85 1.2.8.2 tls } 86 1.2.8.2 tls 87 1.2.8.2 tls static inline bool 88 1.2.8.2 tls pte_valid_p(pt_entry_t pt_entry) 89 1.2.8.2 tls { 90 1.2.8.2 tls return (pt_entry & MMUAR_V) == MMUAR_V; 91 1.2.8.2 tls } 92 1.2.8.2 tls 93 1.2.8.2 tls static inline bool 94 1.2.8.2 tls pte_exec_p(pt_entry_t pt_entry) 95 1.2.8.2 tls { 96 1.2.8.2 tls return (pt_entry & MMUDR_X) == MMUDR_X; 97 1.2.8.2 tls } 98 1.2.8.2 tls 99 1.2.8.2 tls static inline bool 100 1.2.8.2 tls pte_deferred_exec_p(pt_entry_t pt_entry) 101 1.2.8.2 tls { 102 1.2.8.2 tls return !pte_exec_p(pt_entry); 103 1.2.8.2 tls } 104 1.2.8.2 tls 105 1.2.8.2 tls static inline bool 106 1.2.8.2 tls pte_wired_p(pt_entry_t pt_entry) 107 1.2.8.2 tls { 108 1.2.8.2 tls return (pt_entry & MMUDR_LK) == MMUDR_LK; 109 1.2.8.2 tls } 110 1.2.8.2 tls 111 1.2.8.2 tls static inline pt_entry_t 112 1.2.8.2 tls pte_nv_entry(bool kernel) 113 1.2.8.2 tls { 114 1.2.8.2 tls return 0; 115 1.2.8.2 tls } 116 1.2.8.2 tls 117 1.2.8.2 tls static inline paddr_t 118 1.2.8.2 tls pte_to_paddr(pt_entry_t pt_entry) 119 1.2.8.2 tls { 120 1.2.8.2 tls return (paddr_t)(pt_entry & MMUDR_PA); 121 1.2.8.2 tls } 122 1.2.8.2 tls 123 1.2.8.2 tls static inline pt_entry_t 124 1.2.8.2 tls pte_ionocached_bits(void) 125 1.2.8.2 tls { 126 1.2.8.2 tls return MMUDR_CM_NCP; 127 1.2.8.2 tls } 128 1.2.8.2 tls 129 1.2.8.2 tls static inline pt_entry_t 130 1.2.8.2 tls pte_iocached_bits(void) 131 1.2.8.2 tls { 132 1.2.8.2 tls return MMUDR_CM_NCP; 133 1.2.8.2 tls } 134 1.2.8.2 tls 135 1.2.8.2 tls static inline pt_entry_t 136 1.2.8.2 tls pte_nocached_bits(void) 137 1.2.8.2 tls { 138 1.2.8.2 tls return MMUDR_CM_NCP; 139 1.2.8.2 tls } 140 1.2.8.2 tls 141 1.2.8.2 tls static inline pt_entry_t 142 1.2.8.2 tls pte_cached_bits(void) 143 1.2.8.2 tls { 144 1.2.8.2 tls return MMUDR_CM_WB; 145 1.2.8.2 tls } 146 1.2.8.2 tls 147 1.2.8.2 tls static inline pt_entry_t 148 1.2.8.2 tls pte_cached_change(pt_entry_t pt_entry, bool cached) 149 1.2.8.2 tls { 150 1.2.8.2 tls return (pt_entry & ~MMUDR_CM) | (cached ? MMUDR_CM_WB : MMUDR_CM_NCP); 151 1.2.8.2 tls } 152 1.2.8.2 tls 153 1.2.8.2 tls static inline pt_entry_t 154 1.2.8.2 tls pte_wire_entry(pt_entry_t pt_entry) 155 1.2.8.2 tls { 156 1.2.8.2 tls return pt_entry | MMUDR_LK; 157 1.2.8.2 tls } 158 1.2.8.2 tls 159 1.2.8.2 tls static inline pt_entry_t 160 1.2.8.2 tls pte_unwire_entry(pt_entry_t pt_entry) 161 1.2.8.2 tls { 162 1.2.8.2 tls return pt_entry & ~MMUDR_LK; 163 1.2.8.2 tls } 164 1.2.8.2 tls 165 1.2.8.2 tls static inline pt_entry_t 166 1.2.8.2 tls pte_prot_nowrite(pt_entry_t pt_entry) 167 1.2.8.2 tls { 168 1.2.8.2 tls return pt_entry & ~MMUDR_W; 169 1.2.8.2 tls } 170 1.2.8.2 tls 171 1.2.8.2 tls static inline pt_entry_t 172 1.2.8.2 tls pte_prot_downgrade(pt_entry_t pt_entry, vm_prot_t newprot) 173 1.2.8.2 tls { 174 1.2.8.2 tls pt_entry &= ~MMUDR_W; 175 1.2.8.2 tls if ((newprot & VM_PROT_EXECUTE) == 0) 176 1.2.8.2 tls pt_entry &= ~MMUDR_X; 177 1.2.8.2 tls return pt_entry; 178 1.2.8.2 tls } 179 1.2.8.2 tls 180 1.2.8.2 tls static inline pt_entry_t 181 1.2.8.2 tls pte_prot_bits(struct vm_page_md *mdpg, vm_prot_t prot) 182 1.2.8.2 tls { 183 1.2.8.2 tls KASSERT(prot & VM_PROT_READ); 184 1.2.8.2 tls pt_entry_t pt_entry = MMUDR_R; 185 1.2.8.2 tls if (prot & VM_PROT_EXECUTE) { 186 1.2.8.2 tls /* Only allow exec for managed pages */ 187 1.2.8.2 tls if (mdpg != NULL && VM_PAGEMD_EXECPAGE_P(mdpg)) 188 1.2.8.2 tls pt_entry |= MMUDR_X; 189 1.2.8.2 tls } 190 1.2.8.2 tls if (prot & VM_PROT_WRITE) { 191 1.2.8.2 tls if (mdpg == NULL || VM_PAGEMD_MODIFIED_P(mdpg)) 192 1.2.8.2 tls pt_entry |= MMUDR_W; 193 1.2.8.2 tls } 194 1.2.8.2 tls return pt_entry; 195 1.2.8.2 tls } 196 1.2.8.2 tls 197 1.2.8.2 tls static inline pt_entry_t 198 1.2.8.2 tls pte_flag_bits(struct vm_page_md *mdpg, int flags) 199 1.2.8.2 tls { 200 1.2.8.2 tls if (__predict_false(flags & PMAP_NOCACHE)) { 201 1.2.8.2 tls if (__predict_true(mdpg != NULL)) { 202 1.2.8.2 tls return pte_nocached_bits(); 203 1.2.8.2 tls } else { 204 1.2.8.2 tls return pte_ionocached_bits(); 205 1.2.8.2 tls } 206 1.2.8.2 tls } else { 207 1.2.8.2 tls if (__predict_false(mdpg != NULL)) { 208 1.2.8.2 tls return pte_cached_bits(); 209 1.2.8.2 tls } else { 210 1.2.8.2 tls return pte_iocached_bits(); 211 1.2.8.2 tls } 212 1.2.8.2 tls } 213 1.2.8.2 tls } 214 1.2.8.2 tls 215 1.2.8.2 tls static inline pt_entry_t 216 1.2.8.2 tls pte_make_enter(paddr_t pa, struct vm_page_md *mdpg, vm_prot_t prot, 217 1.2.8.2 tls int flags, bool kernel) 218 1.2.8.2 tls { 219 1.2.8.2 tls pt_entry_t pt_entry = (pt_entry_t) pa & MMUDR_PA; 220 1.2.8.2 tls 221 1.2.8.2 tls pt_entry |= pte_flag_bits(mdpg, flags); 222 1.2.8.2 tls pt_entry |= pte_prot_bits(mdpg, prot); 223 1.2.8.2 tls 224 1.2.8.2 tls return pt_entry; 225 1.2.8.2 tls } 226 1.2.8.2 tls 227 1.2.8.2 tls static inline pt_entry_t 228 1.2.8.2 tls pte_make_kenter_pa(paddr_t pa, struct vm_page_md *mdpg, vm_prot_t prot, 229 1.2.8.2 tls int flags) 230 1.2.8.2 tls { 231 1.2.8.2 tls pt_entry_t pt_entry = (pt_entry_t) pa & MMUDR_PA; 232 1.2.8.2 tls 233 1.2.8.2 tls pt_entry |= MMUDR_LK; 234 1.2.8.2 tls pt_entry |= pte_flag_bits(mdpg, flags); 235 1.2.8.2 tls pt_entry |= pte_prot_bits(NULL, prot); /* pretend unmanaged */ 236 1.2.8.2 tls 237 1.2.8.2 tls return pt_entry; 238 1.2.8.2 tls } 239 1.2.8.2 tls #endif /* _KERNEL_ */ 240 1.2.8.2 tls 241 1.2.8.2 tls #endif /* _M68K_PTE_COLDFIRE_H_ */ 242
Indexes created Sun Oct 26 21:10:03 GMT 2025