pte_motorola.h revision 1.1 1 1.1 chs /* $NetBSD: pte_motorola.h,v 1.1 2002/10/14 05:18:45 chs Exp $ */
2 1.1 chs
3 1.1 chs /*
4 1.1 chs * Copyright (c) 1988 University of Utah.
5 1.1 chs * Copyright (c) 1982, 1986, 1990, 1993
6 1.1 chs * The Regents of the University of California. All rights reserved.
7 1.1 chs *
8 1.1 chs * This code is derived from software contributed to Berkeley by
9 1.1 chs * the Systems Programming Group of the University of Utah Computer
10 1.1 chs * Science Department.
11 1.1 chs *
12 1.1 chs * Redistribution and use in source and binary forms, with or without
13 1.1 chs * modification, are permitted provided that the following conditions
14 1.1 chs * are met:
15 1.1 chs * 1. Redistributions of source code must retain the above copyright
16 1.1 chs * notice, this list of conditions and the following disclaimer.
17 1.1 chs * 2. Redistributions in binary form must reproduce the above copyright
18 1.1 chs * notice, this list of conditions and the following disclaimer in the
19 1.1 chs * documentation and/or other materials provided with the distribution.
20 1.1 chs * 3. All advertising materials mentioning features or use of this software
21 1.1 chs * must display the following acknowledgement:
22 1.1 chs * This product includes software developed by the University of
23 1.1 chs * California, Berkeley and its contributors.
24 1.1 chs * 4. Neither the name of the University nor the names of its contributors
25 1.1 chs * may be used to endorse or promote products derived from this software
26 1.1 chs * without specific prior written permission.
27 1.1 chs *
28 1.1 chs * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
29 1.1 chs * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
30 1.1 chs * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
31 1.1 chs * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
32 1.1 chs * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 1.1 chs * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 1.1 chs * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 1.1 chs * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
36 1.1 chs * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
37 1.1 chs * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
38 1.1 chs * SUCH DAMAGE.
39 1.1 chs *
40 1.1 chs * from: Utah $Hdr: pte.h 1.13 92/01/20$
41 1.1 chs *
42 1.1 chs * @(#)pte.h 8.1 (Berkeley) 6/10/93
43 1.1 chs */
44 1.1 chs
45 1.1 chs #ifndef _MACHINE_PTE_H_
46 1.1 chs #define _MACHINE_PTE_H_
47 1.1 chs
48 1.1 chs /*
49 1.1 chs * m68k motorola MMU segment/page table entries
50 1.1 chs */
51 1.1 chs
52 1.1 chs typedef int st_entry_t; /* segment table entry */
53 1.1 chs typedef int pt_entry_t; /* page table entry */
54 1.1 chs
55 1.1 chs #define PT_ENTRY_NULL NULL
56 1.1 chs #define ST_ENTRY_NULL NULL
57 1.1 chs
58 1.1 chs #if defined(amiga) || defined(atari)
59 1.1 chs #define PG_SHIFT 13
60 1.1 chs #else
61 1.1 chs #define PG_SHIFT 12
62 1.1 chs #endif
63 1.1 chs
64 1.1 chs #define SG_V 0x00000002 /* segment is valid */
65 1.1 chs #define SG_NV 0x00000000
66 1.1 chs #define SG_PROT 0x00000004 /* access protection mask */
67 1.1 chs #define SG_RO 0x00000004
68 1.1 chs #define SG_RW 0x00000000
69 1.1 chs #define SG_U 0x00000008 /* modified bit (68040) */
70 1.1 chs #define SG_FRAME ((~0) << PG_SHIFT)
71 1.1 chs #define SG_ISHIFT ((PG_SHIFT << 1) - 2) /* 24 or 22 */
72 1.1 chs #define SG_IMASK ((~0) << SG_ISHIFT)
73 1.1 chs #define SG_PSHIFT PG_SHIFT
74 1.1 chs #define SG_PMASK (((~0) << SG_PSHIFT) & ~SG_IMASK)
75 1.1 chs
76 1.1 chs /* 68040 additions */
77 1.1 chs #define SG4_MASK1 0xfe000000
78 1.1 chs #define SG4_SHIFT1 25
79 1.1 chs #define SG4_MASK2 0x01fc0000
80 1.1 chs #define SG4_SHIFT2 18
81 1.1 chs #define SG4_MASK3 (((~0) << PG_SHIFT) & ~(SG4_MASK1 | SG4_MASK2))
82 1.1 chs #define SG4_SHIFT3 PG_SHIFT
83 1.1 chs #define SG4_ADDR1 0xfffffe00
84 1.1 chs #define SG4_ADDR2 ((~0) << (20 - PG_SHIFT))
85 1.1 chs #define SG4_LEV1SIZE 128
86 1.1 chs #define SG4_LEV2SIZE 128
87 1.1 chs #define SG4_LEV3SIZE (1 << (SG4_SHIFT2 - PG_SHIFT)) /* 64 or 32 */
88 1.1 chs
89 1.1 chs #define PG_V 0x00000001
90 1.1 chs #define PG_NV 0x00000000
91 1.1 chs #define PG_PROT 0x00000004
92 1.1 chs #define PG_U 0x00000008
93 1.1 chs #define PG_M 0x00000010
94 1.1 chs #define PG_W 0x00000100
95 1.1 chs #define PG_RO 0x00000004
96 1.1 chs #define PG_RW 0x00000000
97 1.1 chs #define PG_FRAME ((~0) << PG_SHIFT)
98 1.1 chs #define PG_CI 0x00000040
99 1.1 chs #define PG_PFNUM(x) (((x) & PG_FRAME) >> PG_SHIFT)
100 1.1 chs
101 1.1 chs /* 68040 additions */
102 1.1 chs #define PG_CMASK 0x00000060 /* cache mode mask */
103 1.1 chs #define PG_CWT 0x00000000 /* writethrough caching */
104 1.1 chs #define PG_CCB 0x00000020 /* copyback caching */
105 1.1 chs #define PG_CIS 0x00000040 /* cache inhibited serialized */
106 1.1 chs #define PG_CIN 0x00000060 /* cache inhibited nonserialized */
107 1.1 chs #define PG_SO 0x00000080 /* supervisor only */
108 1.1 chs
109 1.1 chs #define M68K_STSIZE (MAXUL2SIZE * SG4_LEV2SIZE * sizeof(st_entry_t))
110 1.1 chs /* user process segment table size */
111 1.1 chs #define M68K_MAX_PTSIZE 0x400000 /* max size of UPT */
112 1.1 chs #define M68K_MAX_KPTSIZE 0x100000 /* max memory to allocate to KPT */
113 1.1 chs #define M68K_PTBASE 0x10000000 /* UPT map base address */
114 1.1 chs #define M68K_PTMAXSIZE 0x70000000 /* UPT map maximum size */
115 1.1 chs
116 1.1 chs /*
117 1.1 chs * Kernel virtual address to page table entry and to physical address.
118 1.1 chs */
119 1.1 chs
120 1.1 chs #ifdef cesfic
121 1.1 chs #define kvtopte(va) \
122 1.1 chs (&Sysmap[((unsigned)(va)) >> PGSHIFT])
123 1.1 chs #else
124 1.1 chs #define kvtopte(va) \
125 1.1 chs (&Sysmap[((unsigned)(va) - VM_MIN_KERNEL_ADDRESS) >> PGSHIFT])
126 1.1 chs #endif
127 1.1 chs
128 1.1 chs #endif /* !_MACHINE_PTE_H_ */
129