Home | History | Annotate | Line # | Download | only in include
      1  1.6   andvar /*	$NetBSD: vectors.h,v 1.6 2024/02/01 22:00:29 andvar Exp $	*/
      2  1.1  thorpej 
      3  1.1  thorpej /*-
      4  1.1  thorpej  * Copyright (c) 2024 The NetBSD Foundation, Inc.
      5  1.1  thorpej  * All rights reserved.
      6  1.1  thorpej  *
      7  1.1  thorpej  * This code is derived from software contributed to The NetBSD Foundation
      8  1.1  thorpej  * by Jason R. Thorpe.
      9  1.1  thorpej  *
     10  1.1  thorpej  * Redistribution and use in source and binary forms, with or without
     11  1.1  thorpej  * modification, are permitted provided that the following conditions
     12  1.1  thorpej  * are met:
     13  1.1  thorpej  * 1. Redistributions of source code must retain the above copyright
     14  1.1  thorpej  *    notice, this list of conditions and the following disclaimer.
     15  1.1  thorpej  * 2. Redistributions in binary form must reproduce the above copyright
     16  1.1  thorpej  *    notice, this list of conditions and the following disclaimer in the
     17  1.1  thorpej  *    documentation and/or other materials provided with the distribution.
     18  1.1  thorpej  *
     19  1.1  thorpej  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     20  1.1  thorpej  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     21  1.1  thorpej  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     22  1.1  thorpej  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     23  1.1  thorpej  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     24  1.1  thorpej  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     25  1.1  thorpej  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     26  1.1  thorpej  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     27  1.1  thorpej  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     28  1.1  thorpej  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     29  1.1  thorpej  * POSSIBILITY OF SUCH DAMAGE.
     30  1.1  thorpej  */
     31  1.1  thorpej 
     32  1.1  thorpej #ifndef _M68K_VECTORS_H_
     33  1.1  thorpej #define	_M68K_VECTORS_H_
     34  1.1  thorpej 
     35  1.1  thorpej /*
     36  1.1  thorpej  * Vector numbers (*4 for byte offset into table).
     37  1.1  thorpej  *
     38  1.1  thorpej  * VECI_RIISP and VECI_RIPC are fetched using Supervisor Program
     39  1.1  thorpej  * space.  The rest, Supervisor Data space.
     40  1.1  thorpej  *
     41  1.1  thorpej  * VECI_PMMU_ILLOP and VECI_PMMU_ACCESS are defined for the 68020, but
     42  1.1  thorpej  * not used on the 68030.
     43  1.1  thorpej  *
     44  1.1  thorpej  * VECI_CPV and VECI_PMMU_CONF are defined for the 68020 and 68030, but
     45  1.1  thorpej  * not used on the 68040 or 68060.
     46  1.1  thorpej  *
     47  1.1  thorpej  * VECI_UNIMP_FP_DATA, VECI_UNIMP_EA and VECI_UNIMP_II are defined for
     48  1.1  thorpej  * the 68060 and reserved on all other processors.
     49  1.1  thorpej  */
     50  1.1  thorpej #define	VECI_RIISP		0	/* Reset Initial Interrupt SP */
     51  1.1  thorpej #define	VECI_RIPC		1	/* Reset Initial PC */
     52  1.1  thorpej #define	VECI_BUSERR		2	/* Bus Error */
     53  1.1  thorpej #define	VECI_ADDRERR		3	/* Address Error */
     54  1.1  thorpej #define	VECI_ILLINST		4	/* Illegal Instruction */
     55  1.1  thorpej #define	VECI_ZERODIV		5	/* Zero Divide */
     56  1.1  thorpej #define	VECI_CHK		6	/* CHK, CHK2 instruction */
     57  1.1  thorpej #define	VECI_TRAPcc		7	/* cpTRAPcc, TRAPcc, TRAPV */
     58  1.1  thorpej #define	VECI_PRIV		8	/* Privilege Violation */
     59  1.1  thorpej #define	VECI_TRACE		9	/* Trace */
     60  1.1  thorpej #define	VECI_LINE1010		10	/* Line 1010 Emulator */
     61  1.1  thorpej #define	VECI_LINE1111		11	/* Line 1111 Emulator */
     62  1.1  thorpej #define	VECI_rsvd12		12	/* unassigned, reserved */
     63  1.6   andvar #define	VECI_CPV		13	/* Coprocessor Protocol Violation */
     64  1.1  thorpej #define	VECI_FORMATERR		14	/* Format Error */
     65  1.1  thorpej #define	VECI_UNINT_INTR		15	/* Uninitialized Interrupt */
     66  1.1  thorpej #define	VECI_rsvd16		16	/* unassigned, reserved */
     67  1.1  thorpej #define	VECI_rsvd17		17	/* unassigned, reserved */
     68  1.1  thorpej #define	VECI_rsvd18		18	/* unassigned, reserved */
     69  1.1  thorpej #define	VECI_rsvd19		19	/* unassigned, reserved */
     70  1.1  thorpej #define	VECI_rsvd20		20	/* unassigned, reserved */
     71  1.1  thorpej #define	VECI_rsvd21		21	/* unassigned, reserved */
     72  1.1  thorpej #define	VECI_rsvd22		22	/* unassigned, reserved */
     73  1.1  thorpej #define	VECI_rsvd23		23	/* unassigned, reserved */
     74  1.2  thorpej #define	VECI_INTRAV0		24	/* Spurious Interrupt */
     75  1.2  thorpej #define	VECI_SPURIOUS_INTR	VECI_INTRAV0
     76  1.1  thorpej #define	VECI_INTRAV1		25	/* Level 1 Interrupt Autovector */
     77  1.1  thorpej #define	VECI_INTRAV2		26	/* Level 2 Interrupt Autovector */
     78  1.1  thorpej #define	VECI_INTRAV3		27	/* Level 3 Interrupt Autovector */
     79  1.1  thorpej #define	VECI_INTRAV4		28	/* Level 4 Interrupt Autovector */
     80  1.1  thorpej #define	VECI_INTRAV5		29	/* Level 5 Interrupt Autovector */
     81  1.1  thorpej #define	VECI_INTRAV6		30	/* Level 6 Interrupt Autovector */
     82  1.1  thorpej #define	VECI_INTRAV7		31	/* Level 7 Interrupt Autovector */
     83  1.1  thorpej #define	VECI_TRAP0		32	/* Trap #0 instruction */
     84  1.1  thorpej #define	VECI_TRAP1		33	/* Trap #1 instruction */
     85  1.1  thorpej #define	VECI_TRAP2		34	/* Trap #2 instruction */
     86  1.1  thorpej #define	VECI_TRAP3		35	/* Trap #3 instruction */
     87  1.1  thorpej #define	VECI_TRAP4		36	/* Trap #4 instruction */
     88  1.1  thorpej #define	VECI_TRAP5		37	/* Trap #5 instruction */
     89  1.1  thorpej #define	VECI_TRAP6		38	/* Trap #6 instruction */
     90  1.1  thorpej #define	VECI_TRAP7		39	/* Trap #7 instruction */
     91  1.1  thorpej #define	VECI_TRAP8		40	/* Trap #8 instruction */
     92  1.1  thorpej #define	VECI_TRAP9		41	/* Trap #9 instruction */
     93  1.1  thorpej #define	VECI_TRAP10		42	/* Trap #10 instruction */
     94  1.1  thorpej #define	VECI_TRAP11		43	/* Trap #11 instruction */
     95  1.1  thorpej #define	VECI_TRAP12		44	/* Trap #12 instruction */
     96  1.1  thorpej #define	VECI_TRAP13		45	/* Trap #13 instruction */
     97  1.1  thorpej #define	VECI_TRAP14		46	/* Trap #14 instruction */
     98  1.1  thorpej #define	VECI_TRAP15		47	/* Trap #15 instruction */
     99  1.1  thorpej #define	VECI_FP_BSUN		48	/* FPCP Branch or Set on Unordered */
    100  1.1  thorpej #define	VECI_FP_INEX		49	/* FPCP Inexact Result */
    101  1.1  thorpej #define	VECI_FP_DZ		50	/* FPCP Divide by Zero */
    102  1.1  thorpej #define	VECI_FP_UNFL		51	/* FPCP Underflow */
    103  1.1  thorpej #define	VECI_FP_OPERR		52	/* FPCP Operand Error */
    104  1.1  thorpej #define	VECI_FP_OVFL		53	/* FPCP Overflow */
    105  1.1  thorpej #define	VECI_FP_SNAN		54	/* FPCP Signalling NaN */
    106  1.1  thorpej #define	VECI_UNIMP_FP_DATA	55	/* FP Unimplemented Data Type */
    107  1.1  thorpej #define	VECI_PMMU_CONF		56	/* PMMU Configuration */
    108  1.1  thorpej #define	VECI_PMMU_ILLOP		57	/* PMMU Illegal Operation */
    109  1.1  thorpej #define	VECI_PMMU_ACCESS	58	/* PMMU Access Level Violation */
    110  1.1  thorpej #define	VECI_rsvd59		59	/* unassigned, reserved */
    111  1.1  thorpej #define	VECI_UNIMP_EA		60	/* Unimplemented Effective Address */
    112  1.6   andvar #define	VECI_UNIMP_II		61	/* Unimplemented Integer Instruction */
    113  1.1  thorpej #define	VECI_rsvd62		62	/* unassigned, reserved */
    114  1.1  thorpej #define	VECI_rsvd63		63	/* unassigned, reserved */
    115  1.1  thorpej #define	VECI_USRVEC_START	64	/* User defined vectors (192) */
    116  1.1  thorpej 
    117  1.1  thorpej #define	NVECTORS		256
    118  1.4  thorpej #define	NAUTOVECTORS		8
    119  1.4  thorpej #define	NUSERVECTORS		(NVECTORS - VECI_USRVEC_START)
    120  1.1  thorpej 
    121  1.1  thorpej #define	VECI_INTRAV(ipl)	((ipl) + VECI_SPURIOUS_INTR)
    122  1.1  thorpej #define	VECI_TRAP(x)		((x) + VECI_TRAP0)
    123  1.1  thorpej 
    124  1.2  thorpej #define	VECI_TO_VECO(x)		((x) << 2)
    125  1.5  thorpej #define	VECO_TO_VECI(x)		((uint8_t)((unsigned int)(x) >> 2))
    126  1.1  thorpej 
    127  1.1  thorpej #ifdef _KERNEL
    128  1.1  thorpej 
    129  1.1  thorpej extern void *vectab[NVECTORS];
    130  1.3  thorpej extern void **saved_vbr;
    131  1.1  thorpej 
    132  1.1  thorpej void	vec_init(void);
    133  1.1  thorpej void	vec_reset(void);
    134  1.2  thorpej void	*vec_get_entry(int);
    135  1.2  thorpej void	vec_set_entry(int, void *);
    136  1.1  thorpej 
    137  1.1  thorpej #endif /* _KERNEL */
    138  1.1  thorpej 
    139  1.1  thorpej #endif /* _M68K_VECTORS_H_ */
    140