sys_machdep.c revision 1.1
11.1Schs/*	$NetBSD: sys_machdep.c,v 1.1 2002/11/03 02:29:40 chs Exp $	*/
21.1Schs
31.1Schs/*
41.1Schs * Copyright (c) 1982, 1986, 1993
51.1Schs *	The Regents of the University of California.  All rights reserved.
61.1Schs *
71.1Schs * Redistribution and use in source and binary forms, with or without
81.1Schs * modification, are permitted provided that the following conditions
91.1Schs * are met:
101.1Schs * 1. Redistributions of source code must retain the above copyright
111.1Schs *    notice, this list of conditions and the following disclaimer.
121.1Schs * 2. Redistributions in binary form must reproduce the above copyright
131.1Schs *    notice, this list of conditions and the following disclaimer in the
141.1Schs *    documentation and/or other materials provided with the distribution.
151.1Schs * 3. All advertising materials mentioning features or use of this software
161.1Schs *    must display the following acknowledgement:
171.1Schs *	This product includes software developed by the University of
181.1Schs *	California, Berkeley and its contributors.
191.1Schs * 4. Neither the name of the University nor the names of its contributors
201.1Schs *    may be used to endorse or promote products derived from this software
211.1Schs *    without specific prior written permission.
221.1Schs *
231.1Schs * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
241.1Schs * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
251.1Schs * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
261.1Schs * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
271.1Schs * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
281.1Schs * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
291.1Schs * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
301.1Schs * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
311.1Schs * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
321.1Schs * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
331.1Schs * SUCH DAMAGE.
341.1Schs *
351.1Schs *	@(#)sys_machdep.c	8.2 (Berkeley) 1/13/94
361.1Schs */
371.1Schs
381.1Schs#include <sys/cdefs.h>
391.1Schs__KERNEL_RCSID(0, "$NetBSD");
401.1Schs
411.1Schs#include "opt_compat_hpux.h"
421.1Schs
431.1Schs#include <sys/param.h>
441.1Schs#include <sys/proc.h>
451.1Schs#include <sys/mount.h>
461.1Schs
471.1Schs#include <uvm/uvm_extern.h>
481.1Schs
491.1Schs#include <sys/syscallargs.h>
501.1Schs
511.1Schs#include <machine/cpu.h>
521.1Schs#include <m68k/cacheops.h>
531.1Schs
541.1Schs/* XXX should be in an include file somewhere */
551.1Schs#define CC_PURGE	1
561.1Schs#define CC_FLUSH	2
571.1Schs#define CC_IPURGE	4
581.1Schs#define CC_EXTPURGE	0x80000000
591.1Schs/* XXX end should be */
601.1Schs
611.1Schs/*
621.1Schs * Note that what we do here on 040/060 for BSD is different than for HP-UX.
631.1Schs *
641.1Schs * In 'pux they either act on a line (len == 16), a page (len == NBPG)
651.1Schs * or the whole cache (len == anything else).
661.1Schs *
671.1Schs * In BSD we attempt to be more optimal when acting on "odd" sizes.
681.1Schs * For lengths up to 1024 we do all affected lines, up to 2*NBPG we
691.1Schs * do pages, above that we do the entire cache.
701.1Schs */
711.1Schs/*ARGSUSED1*/
721.1Schsint
731.1Schscachectl1(req, addr, len, p)
741.1Schs	unsigned long req;
751.1Schs	vaddr_t	addr;
761.1Schs	size_t len;
771.1Schs	struct proc *p;
781.1Schs{
791.1Schs	int error = 0;
801.1Schs
811.1Schs#if defined(M68040) || defined(M68060)
821.1Schs	if (mmutype == MMU_68040) {
831.1Schs		int inc = 0;
841.1Schs		boolean_t doall = FALSE;
851.1Schs		paddr_t pa = 0;
861.1Schs		vaddr_t end = 0;
871.1Schs#ifdef COMPAT_HPUX
881.1Schs		extern struct emul emul_hpux;
891.1Schs
901.1Schs		if ((p->p_emul == &emul_hpux) &&
911.1Schs		    len != 16 && len != NBPG)
921.1Schs			doall = 1;
931.1Schs#endif
941.1Schs
951.1Schs		if (addr == 0 ||
961.1Schs#if defined(M68060)
971.1Schs		    (cputype == CPU_68040 && req & CC_IPURGE) ||
981.1Schs#else
991.1Schs		    (req & CC_IPURGE) ||
1001.1Schs#endif
1011.1Schs		    ((req & ~CC_EXTPURGE) != CC_PURGE && len > 2 * NBPG))
1021.1Schs			doall = 1;
1031.1Schs
1041.1Schs		if (!doall) {
1051.1Schs			end = addr + len;
1061.1Schs			if (len <= 1024) {
1071.1Schs				addr = addr & ~0xf;
1081.1Schs				inc = 16;
1091.1Schs			} else {
1101.1Schs				addr = addr & ~PGOFSET;
1111.1Schs				inc = NBPG;
1121.1Schs			}
1131.1Schs		}
1141.1Schs		do {
1151.1Schs			/*
1161.1Schs			 * Convert to physical address if needed.
1171.1Schs			 * If translation fails, we perform operation on
1181.1Schs			 * entire cache.
1191.1Schs			 */
1201.1Schs			if (!doall &&
1211.1Schs			    (pa == 0 || m68k_page_offset(addr) == 0)) {
1221.1Schs				if (pmap_extract(p->p_vmspace->vm_map.pmap,
1231.1Schs				    addr, &pa) == FALSE)
1241.1Schs					doall = 1;
1251.1Schs			}
1261.1Schs			switch (req) {
1271.1Schs			case CC_EXTPURGE|CC_IPURGE:
1281.1Schs			case CC_IPURGE:
1291.1Schs				if (doall) {
1301.1Schs					DCFA();
1311.1Schs					ICPA();
1321.1Schs				} else if (inc == 16) {
1331.1Schs					DCFL(pa);
1341.1Schs					ICPL(pa);
1351.1Schs				} else if (inc == NBPG) {
1361.1Schs					DCFP(pa);
1371.1Schs					ICPP(pa);
1381.1Schs				}
1391.1Schs				break;
1401.1Schs
1411.1Schs			case CC_EXTPURGE|CC_PURGE:
1421.1Schs			case CC_PURGE:
1431.1Schs				if (doall)
1441.1Schs					DCFA();	/* note: flush not purge */
1451.1Schs				else if (inc == 16)
1461.1Schs					DCPL(pa);
1471.1Schs				else if (inc == NBPG)
1481.1Schs					DCPP(pa);
1491.1Schs				break;
1501.1Schs
1511.1Schs			case CC_EXTPURGE|CC_FLUSH:
1521.1Schs			case CC_FLUSH:
1531.1Schs				if (doall)
1541.1Schs					DCFA();
1551.1Schs				else if (inc == 16)
1561.1Schs					DCFL(pa);
1571.1Schs				else if (inc == NBPG)
1581.1Schs					DCFP(pa);
1591.1Schs				break;
1601.1Schs
1611.1Schs			default:
1621.1Schs				error = EINVAL;
1631.1Schs				break;
1641.1Schs			}
1651.1Schs			if (doall)
1661.1Schs				break;
1671.1Schs			pa += inc;
1681.1Schs			addr += inc;
1691.1Schs		} while (addr < end);
1701.1Schs		return (error);
1711.1Schs	}
1721.1Schs#endif
1731.1Schs	switch (req) {
1741.1Schs	case CC_EXTPURGE|CC_PURGE:
1751.1Schs	case CC_EXTPURGE|CC_FLUSH:
1761.1Schs#if defined(CACHE_HAVE_PAC)
1771.1Schs		if (ectype == EC_PHYS)
1781.1Schs			PCIA();
1791.1Schs		/* fall into... */
1801.1Schs#endif
1811.1Schs	case CC_PURGE:
1821.1Schs	case CC_FLUSH:
1831.1Schs		DCIU();
1841.1Schs		break;
1851.1Schs	case CC_EXTPURGE|CC_IPURGE:
1861.1Schs#if defined(CACHE_HAVE_PAC)
1871.1Schs		if (ectype == EC_PHYS)
1881.1Schs			PCIA();
1891.1Schs		else
1901.1Schs#endif
1911.1Schs		DCIU();
1921.1Schs		/* fall into... */
1931.1Schs	case CC_IPURGE:
1941.1Schs		ICIA();
1951.1Schs		break;
1961.1Schs	default:
1971.1Schs		error = EINVAL;
1981.1Schs		break;
1991.1Schs	}
2001.1Schs	return (error);
2011.1Schs}
2021.1Schs
2031.1Schsint
2041.1Schssys_sysarch(p, v, retval)
2051.1Schs	struct proc *p;
2061.1Schs	void *v;
2071.1Schs	register_t *retval;
2081.1Schs{
2091.1Schs
2101.1Schs	return (ENOSYS);
2111.1Schs}
2121.1Schs
2131.1Schs#if defined(amiga) || defined(x68k)
2141.1Schs
2151.1Schs/*
2161.1Schs * DMA cache control
2171.1Schs */
2181.1Schs
2191.1Schs/*ARGSUSED1*/
2201.1Schsint
2211.1Schsdma_cachectl(addr, len)
2221.1Schs	caddr_t	addr;
2231.1Schs	int len;
2241.1Schs{
2251.1Schs#if defined(M68040) || defined(M68060)
2261.1Schs	int inc = 0;
2271.1Schs	int pa = 0;
2281.1Schs	caddr_t end;
2291.1Schs
2301.1Schs	if (mmutype != MMU_68040) {
2311.1Schs		return (0);
2321.1Schs	}
2331.1Schs
2341.1Schs	end = addr + len;
2351.1Schs	if (len <= 1024) {
2361.1Schs		addr = (caddr_t)((vaddr_t)addr & ~0xf);
2371.1Schs		inc = 16;
2381.1Schs	} else {
2391.1Schs		addr = (caddr_t)((vaddr_t)addr & ~PGOFSET);
2401.1Schs		inc = NBPG;
2411.1Schs	}
2421.1Schs	do {
2431.1Schs		/*
2441.1Schs		 * Convert to physical address.
2451.1Schs		 */
2461.1Schs		if (pa == 0 || ((vaddr_t)addr & PGOFSET) == 0) {
2471.1Schs			pa = kvtop(addr);
2481.1Schs		}
2491.1Schs		if (inc == 16) {
2501.1Schs			DCFL(pa);
2511.1Schs			ICPL(pa);
2521.1Schs		} else {
2531.1Schs			DCFP(pa);
2541.1Schs			ICPP(pa);
2551.1Schs		}
2561.1Schs		pa += inc;
2571.1Schs		addr += inc;
2581.1Schs	} while (addr < end);
2591.1Schs#endif	/* defined(M68040) || defined(M68060) */
2601.1Schs	return (0);
2611.1Schs}
2621.1Schs#endif	/* defined(amiga) || defined(x68k) */
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