mac68k5380.c revision 1.13
1 /* $NetBSD: mac68k5380.c,v 1.13 1995/09/30 21:34:54 briggs Exp $ */ 2 3 /* 4 * Copyright (c) 1995 Allen Briggs 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Allen Briggs 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * Derived from atari5380.c for the mac68k port of NetBSD. 33 * 34 */ 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/kernel.h> 39 #include <sys/device.h> 40 #include <sys/dkstat.h> 41 #include <sys/syslog.h> 42 #include <sys/buf.h> 43 #include <scsi/scsi_all.h> 44 #include <scsi/scsi_message.h> 45 #include <scsi/scsiconf.h> 46 47 /* 48 * Include the driver definitions 49 */ 50 #include <mac68k/dev/ncr5380reg.h> 51 52 #include <machine/stdarg.h> 53 54 #include "../mac68k/via.h" 55 56 /* 57 * Set the various driver options 58 */ 59 #define NREQ 18 /* Size of issue queue */ 60 #define AUTO_SENSE 1 /* Automatically issue a request-sense */ 61 62 #define DRNAME ncrscsi /* used in various prints */ 63 #undef DBG_SEL /* Show the selection process */ 64 #undef DBG_REQ /* Show enqueued/ready requests */ 65 #undef DBG_NOWRITE /* Do not allow writes to the targets */ 66 #undef DBG_PIO /* Show the polled-I/O process */ 67 #undef DBG_INF /* Show information transfer process */ 68 #define DBG_NOSTATIC /* No static functions, all in DDB trace*/ 69 #undef DBG_PID /* Keep track of driver */ 70 #undef REAL_DMA /* Use DMA if sensible */ 71 #define fair_to_keep_dma() 1 72 #define claimed_dma() 1 73 #define reconsider_dma() 74 #define USE_PDMA 1 /* Use special pdma-transfer function */ 75 #define MIN_PHYS 0x2000 /* pdma space w/ /DSACK is only 0x2000 */ 76 77 #define ENABLE_NCR5380(sc) cur_softc = sc; 78 79 /* 80 * softc of currently active controller (well, we only have one for now). 81 */ 82 83 static struct ncr_softc *cur_softc; 84 85 struct scsi_5380 { 86 volatile u_char scsi_5380[8*16]; /* 8 regs, 1 every 16th byte. */ 87 }; 88 89 extern vm_offset_t SCSIBase; 90 static volatile u_char *ncr = (volatile u_char *) 0x10000; 91 static volatile u_char *ncr_5380_with_drq = (volatile u_char *) 0x6000; 92 static volatile u_char *ncr_5380_without_drq = (volatile u_char *) 0x12000; 93 94 static volatile u_char *scsi_enable = NULL; 95 96 #define SCSI_5380 ((struct scsi_5380 *) ncr) 97 #define GET_5380_REG(rnum) SCSI_5380->scsi_5380[((rnum)<<4)] 98 #define SET_5380_REG(rnum,val) (SCSI_5380->scsi_5380[((rnum)<<4)] = (val)) 99 100 void ncr5380_irq_intr(void *); 101 void ncr5380_drq_intr(void *); 102 103 static __inline__ void 104 scsi_clr_ipend() 105 { 106 int tmp; 107 108 tmp = GET_5380_REG(NCR5380_IRCV); 109 } 110 111 extern __inline__ void 112 scsi_ienable() 113 { 114 int s; 115 116 s = splhigh(); 117 *scsi_enable = 0x80 | (V2IF_SCSIIRQ | V2IF_SCSIDRQ); 118 splx(s); 119 } 120 121 extern __inline__ void 122 scsi_idisable() 123 { 124 int s; 125 126 s = splhigh(); 127 *scsi_enable = V2IF_SCSIIRQ | V2IF_SCSIDRQ; 128 splx(s); 129 } 130 131 static void 132 scsi_mach_init(sc) 133 struct ncr_softc *sc; 134 { 135 static int initted = 0; 136 137 if (initted++) 138 panic("scsi_mach_init called again.\n"); 139 140 ncr = (volatile u_char *) 141 (SCSIBase + (u_long) ncr); 142 ncr_5380_with_drq = (volatile u_char *) 143 (SCSIBase + (u_int) ncr_5380_with_drq); 144 ncr_5380_without_drq = (volatile u_char *) 145 (SCSIBase + (u_int) ncr_5380_without_drq); 146 147 if (VIA2 == VIA2OFF) 148 scsi_enable = Via1Base + VIA2 * 0x2000 + vIER; 149 else 150 scsi_enable = Via1Base + VIA2 * 0x2000 + rIER; 151 152 mac68k_register_scsi_irq(ncr5380_irq_intr, sc); 153 mac68k_register_scsi_drq(ncr5380_drq_intr, sc); 154 } 155 156 static int 157 machine_match(pdp, cdp, auxp, cd) 158 struct device *pdp; 159 struct cfdata *cdp; 160 void *auxp; 161 struct cfdriver *cd; 162 { 163 if (matchbyname(pdp, cdp, auxp) == 0) 164 return 0; 165 if (!mac68k_machine.scsi80) 166 return 0; 167 if (cdp->cf_unit != 0) 168 return 0; 169 return 1; 170 } 171 172 #if USE_PDMA 173 int pdma_5380_dir = 0; 174 175 u_char *pending_5380_data; 176 u_long pending_5380_count; 177 178 /* #define DEBUG 1 Maybe we try with this off eventually. */ 179 180 #if DEBUG 181 int pdma_5380_sends = 0; 182 int pdma_5380_bytes = 0; 183 184 char *pdma_5380_state=""; 185 186 void 187 pdma_stat() 188 { 189 printf("PDMA SCSI: %d xfers completed for %d bytes.\n", 190 pdma_5380_sends, pdma_5380_bytes); 191 printf("pdma_5380_dir = %d.\n", 192 pdma_5380_dir); 193 printf("datap = 0x%x, remainder = %d.\n", 194 pending_5380_data, pending_5380_count); 195 printf("pdma_5380_state = %s.\n", pdma_5380_state); 196 } 197 #endif 198 199 void 200 pdma_cleanup(void) 201 { 202 SC_REQ *reqp = connected; 203 int bytes, s; 204 205 s = splbio(); 206 207 pdma_5380_dir = 0; 208 209 #if DEBUG 210 pdma_5380_state = "in pdma_cleanup()."; 211 pdma_5380_sends++; 212 pdma_5380_bytes+=(reqp->xdata_len - pending_5380_count); 213 #endif 214 215 /* 216 * Update pointers. 217 */ 218 reqp->xdata_ptr += reqp->xdata_len - pending_5380_count; 219 reqp->xdata_len = pending_5380_count; 220 221 /* 222 * Reset DMA mode. 223 */ 224 SET_5380_REG(NCR5380_MODE, GET_5380_REG(NCR5380_MODE) & ~SC_M_DMA); 225 226 /* 227 * Clear any pending interrupts. 228 */ 229 scsi_clr_ipend(); 230 231 /* 232 * Tell interrupt functions that DMA has ended. 233 */ 234 reqp->dr_flag &= ~DRIVER_IN_DMA; 235 236 SET_5380_REG(NCR5380_MODE, IMODE_BASE); 237 SET_5380_REG(NCR5380_ICOM, 0); 238 239 splx(s); 240 241 /* 242 * Back for more punishment. 243 */ 244 run_main(cur_softc); 245 } 246 #endif 247 248 static __inline__ int 249 pdma_ready() 250 { 251 #if USE_PDMA 252 SC_REQ *reqp = connected; 253 int dmstat, idstat; 254 extern u_char ncr5380_no_parchk; 255 256 if (pdma_5380_dir) { 257 #if DEBUG 258 pdma_5380_state = "got irq interrupt in xfer."; 259 #endif 260 /* 261 * If Mr. IRQ isn't set one might wonder how we got 262 * here. It does happen, though. 263 */ 264 dmstat = GET_5380_REG(NCR5380_DMSTAT); 265 if (!(dmstat & SC_IRQ_SET)) { 266 return 0; 267 } 268 /* 269 * For a phase mis-match, ATN is a "don't care," IRQ is 1 and 270 * all other bits in the Bus & Status Register are 0. Also, 271 * the current SCSI Bus Status Register has a 1 for BSY and 272 * REQ. Since we're just checking that this interrupt isn't a 273 * reselection or a reset, we just check for either. 274 */ 275 idstat = GET_5380_REG(NCR5380_IDSTAT); 276 if ( ((dmstat & (0xff & ~SC_ATN_STAT)) == SC_IRQ_SET) 277 && ((idstat & (SC_S_BSY|SC_S_REQ)) 278 == (SC_S_BSY | SC_S_REQ)) ) { 279 pdma_cleanup(); 280 return 1; 281 } else if (PH_IN(reqp->phase) && (dmstat & SC_PAR_ERR)) { 282 if (!(ncr5380_no_parchk & (1 << reqp->targ_id))) 283 /* XXX: Should be parity error ???? */ 284 reqp->xs->error = XS_DRIVER_STUFFUP; 285 /* XXX: is this the right reaction? */ 286 pdma_cleanup(); 287 return 1; 288 } else if ( !(idstat & SC_S_REQ) 289 || (((idstat>>2) & 7) != reqp->phase)) { 290 #ifdef DIAGNOSTIC 291 /* XXX: is this the right reaction? Can this happen? */ 292 scsi_show(); 293 printf("Unexpected phase change.\n"); 294 #endif 295 reqp->xs->error = XS_DRIVER_STUFFUP; 296 pdma_cleanup(); 297 return 1; 298 } else { 299 scsi_show(); 300 panic("Spurious interrupt during PDMA xfer.\n"); 301 } 302 } 303 #endif 304 return 0; 305 } 306 307 void 308 ncr5380_irq_intr(p) 309 void *p; 310 { 311 struct ncr_softc *sc = p; 312 313 #if USE_PDMA 314 if (pdma_ready()) { 315 return; 316 } 317 #endif 318 if (GET_5380_REG(NCR5380_DMSTAT) & SC_IRQ_SET) { 319 scsi_idisable(); 320 ncr_ctrl_intr(cur_softc); 321 } 322 } 323 324 /* 325 * This is the meat of the PDMA transfer. 326 * When we get here, we shove data as fast as the mac can take it. 327 * We depend on several things: 328 * * All macs after the Mac Plus that have a 5380 chip should have a general 329 * logic IC that handshakes data for blind transfers. 330 * * If the SCSI controller finishes sending/receiving data before we do, 331 * the same general logic IC will generate a /BERR for us in short order. 332 * * The fault address for said /BERR minus the base address for the 333 * transfer will be the amount of data that was actually written. 334 * 335 * We use the nofault flag and the setjmp/longjmp in locore.s so we can 336 * detect and handle the bus error for early termination of a command. 337 * This is usually caused by a disconnecting target. 338 */ 339 void 340 ncr5380_drq_intr(p) 341 void *p; 342 { 343 #if USE_PDMA 344 extern int *nofault, mac68k_buserr_addr; 345 struct ncr_softc *sc = p; 346 label_t faultbuf; 347 register int count; 348 volatile u_int32_t *long_drq; 349 u_int32_t *long_data; 350 volatile u_int8_t *drq; 351 u_int8_t *data; 352 353 /* 354 * If we're not ready to xfer data, just return. 355 */ 356 if ( !(GET_5380_REG(NCR5380_DMSTAT) & SC_DMA_REQ) 357 || !pdma_5380_dir) 358 return; 359 360 #if DEBUG 361 pdma_5380_state = "got drq interrupt."; 362 #endif 363 364 /* 365 * Setup for a possible bus error caused by SCSI controller 366 * switching out of DATA-IN/OUT before we're done with the 367 * current transfer. 368 */ 369 nofault = (int *) &faultbuf; 370 371 if (setjmp((label_t *) nofault)) { 372 nofault = (int *) 0; 373 #if DEBUG 374 pdma_5380_state = "buserr in xfer."; 375 #endif 376 count = ( (u_long) mac68k_buserr_addr 377 - (u_long) ncr_5380_with_drq); 378 if ((count < 0) || (count > pending_5380_count)) { 379 printf("pdma in: count = %d (0x%x) (pending " 380 "count %d)\n", count, count, 381 pending_5380_count); 382 panic("something is wrong"); 383 } 384 385 pending_5380_data += count; 386 pending_5380_count -= count; 387 388 #if DEBUG 389 pdma_5380_state = "handled bus error in xfer."; 390 #endif 391 mac68k_buserr_addr = 0; 392 return; 393 } 394 395 if (pdma_5380_dir == 2) { /* Data In */ 396 int resid; 397 398 /* 399 * Get the dest address aligned. 400 */ 401 resid = count = 4 - (((int) pending_5380_data) & 0x3); 402 if (count < 4) { 403 data = (u_int8_t *) pending_5380_data; 404 drq = (u_int8_t *) ncr_5380_with_drq; 405 while (count) { 406 #define R1 *data++ = *drq++ 407 R1; count--; 408 #undef R1 409 } 410 pending_5380_data += resid; 411 pending_5380_count -= resid; 412 } 413 414 /* 415 * Get ready to start the transfer. 416 */ 417 while (pending_5380_count) { 418 int dcount; 419 420 dcount = count = min(pending_5380_count, MIN_PHYS); 421 long_drq = (volatile u_int32_t *) ncr_5380_with_drq; 422 long_data = (u_int32_t *) pending_5380_data; 423 424 #define R4 *long_data++ = *long_drq++ 425 while ( count >= 512 ) { 426 if (!(GET_5380_REG(NCR5380_DMSTAT) & SC_DMA_REQ)) { 427 nofault = (int *) 0; 428 429 pending_5380_data += (pending_5380_count-count); 430 pending_5380_count = count; 431 #if DEBUG 432 pdma_5380_state = "drq low"; 433 #endif 434 return; 435 } 436 R4; R4; R4; R4; R4; R4; R4; R4; 437 R4; R4; R4; R4; R4; R4; R4; R4; /* 64 */ 438 R4; R4; R4; R4; R4; R4; R4; R4; 439 R4; R4; R4; R4; R4; R4; R4; R4; /* 128 */ 440 R4; R4; R4; R4; R4; R4; R4; R4; 441 R4; R4; R4; R4; R4; R4; R4; R4; 442 R4; R4; R4; R4; R4; R4; R4; R4; 443 R4; R4; R4; R4; R4; R4; R4; R4; /* 256 */ 444 R4; R4; R4; R4; R4; R4; R4; R4; 445 R4; R4; R4; R4; R4; R4; R4; R4; 446 R4; R4; R4; R4; R4; R4; R4; R4; 447 R4; R4; R4; R4; R4; R4; R4; R4; 448 R4; R4; R4; R4; R4; R4; R4; R4; 449 R4; R4; R4; R4; R4; R4; R4; R4; 450 R4; R4; R4; R4; R4; R4; R4; R4; 451 R4; R4; R4; R4; R4; R4; R4; R4; /* 512 */ 452 count -= 512; 453 } 454 while (count >= 4) { 455 R4; count -= 4; 456 } 457 #undef R4 458 data = (u_int8_t *) long_data; 459 drq = (u_int8_t *) long_drq; 460 while (count) { 461 #define R1 *data++ = *drq++ 462 R1; count--; 463 #undef R1 464 } 465 pending_5380_count -= dcount; 466 pending_5380_data += dcount; 467 } 468 } else { 469 int resid; 470 471 /* 472 * Get the source address aligned. 473 */ 474 resid = count = 4 - (((int) pending_5380_data) & 0x3); 475 if (count < 4) { 476 data = (u_int8_t *) pending_5380_data; 477 drq = (u_int8_t *) ncr_5380_with_drq; 478 while (count) { 479 #define W1 *drq++ = *data++ 480 W1; count--; 481 #undef W1 482 } 483 pending_5380_data += resid; 484 pending_5380_count -= resid; 485 } 486 487 /* 488 * Get ready to start the transfer. 489 */ 490 while (pending_5380_count) { 491 int dcount; 492 493 dcount = count = min(pending_5380_count, MIN_PHYS); 494 long_drq = (volatile u_int32_t *) ncr_5380_with_drq; 495 long_data = (u_int32_t *) pending_5380_data; 496 497 #define W4 *long_drq++ = *long_data++ 498 while ( count >= 64 ) { 499 W4; W4; W4; W4; W4; W4; W4; W4; 500 W4; W4; W4; W4; W4; W4; W4; W4; /* 64 */ 501 count -= 64; 502 } 503 while (count >= 4) { 504 W4; count -= 4; 505 } 506 #undef W4 507 data = (u_int8_t *) long_data; 508 drq = (u_int8_t *) long_drq; 509 while (count) { 510 #define W1 *drq++ = *data++ 511 W1; count--; 512 #undef W1 513 } 514 pending_5380_count -= dcount; 515 pending_5380_data += dcount; 516 } 517 } 518 519 /* 520 * OK. No bus error occurred above. Clear the nofault flag 521 * so we no longer short-circuit bus errors. 522 */ 523 nofault = (int *) 0; 524 525 #if DEBUG 526 pdma_5380_state = "done in xfer--waiting."; 527 #endif 528 529 /* 530 * Is this necessary? 531 */ 532 while (!( (GET_5380_REG(NCR5380_DMSTAT) & SC_ACK_STAT) 533 || (GET_5380_REG(NCR5380_IDSTAT) & SC_S_REQ) )); 534 535 /* 536 * Update pointers for pdma_cleanup(). 537 */ 538 pending_5380_data += pending_5380_count; 539 pending_5380_count = 0; 540 541 #if DEBUG 542 pdma_5380_state = "done in xfer."; 543 #endif 544 545 pdma_cleanup(); 546 return; 547 #endif /* if USE_PDMA */ 548 } 549 550 #if USE_PDMA 551 552 #define SCSI_TIMEOUT_VAL 10000000 553 554 static int 555 transfer_pdma(phasep, data, count) 556 u_char *phasep; 557 u_char *data; 558 u_long *count; 559 { 560 SC_REQ *reqp = connected; 561 int len = *count, i, scsi_timeout = SCSI_TIMEOUT_VAL; 562 int s, err; 563 564 if (pdma_5380_dir) { 565 panic("ncrscsi: transfer_pdma called when operation already " 566 "pending.\n"); 567 } 568 #if DEBUG 569 pdma_5380_state = "in transfer_pdma."; 570 #endif 571 572 /* 573 * Don't bother with PDMA if we can't sleep or for small transfers. 574 */ 575 if (reqp->dr_flag & DRIVER_NOINT) { 576 #if DEBUG 577 pdma_5380_state = "pdma, actually using transfer_pio."; 578 #endif 579 transfer_pio(phasep, data, count, 0); 580 return -1; 581 } 582 583 /* 584 * We are probably already at spl2(), so this is likely a no-op. 585 * Paranoia. 586 */ 587 s = splbio(); 588 589 scsi_idisable(); 590 591 /* 592 * Match phases with target. 593 */ 594 SET_5380_REG(NCR5380_TCOM, *phasep); 595 596 /* 597 * Clear pending interrupts. 598 */ 599 scsi_clr_ipend(); 600 601 /* 602 * Wait until target asserts BSY. 603 */ 604 while ( ((GET_5380_REG(NCR5380_IDSTAT) & SC_S_BSY) == 0) 605 && (--scsi_timeout) ); 606 if (!scsi_timeout) { 607 #if DIAGNOSTIC 608 printf("scsi timeout: waiting for BSY in %s.\n", 609 (*phasep == PH_DATAOUT) ? "pdma_out" : "pdma_in"); 610 #endif 611 goto scsi_timeout_error; 612 } 613 614 /* 615 * Tell the driver that we're in DMA mode. 616 */ 617 reqp->dr_flag |= DRIVER_IN_DMA; 618 619 /* 620 * Set DMA mode and assert data bus. 621 */ 622 SET_5380_REG(NCR5380_MODE, GET_5380_REG(NCR5380_MODE) | SC_M_DMA); 623 SET_5380_REG(NCR5380_ICOM, GET_5380_REG(NCR5380_ICOM) | SC_ADTB); 624 625 /* 626 * Load transfer values for DRQ interrupt handlers. 627 */ 628 pending_5380_data = data; 629 pending_5380_count = len; 630 631 #if DEBUG 632 pdma_5380_state = "wait for interrupt."; 633 #endif 634 635 /* 636 * Set the transfer function to be called on DRQ interrupts. 637 * And note that we're waiting. 638 */ 639 switch (*phasep) { 640 default: 641 panic("Unexpected phase in transfer_pdma.\n"); 642 case PH_DATAOUT: 643 pdma_5380_dir = 1; 644 SET_5380_REG(NCR5380_DMSTAT, 0); 645 break; 646 case PH_DATAIN: 647 pdma_5380_dir = 2; 648 SET_5380_REG(NCR5380_IRCV, 0); 649 break; 650 } 651 652 /* 653 * Now that we're set up, enable interrupts and drop processor 654 * priority back down. 655 */ 656 scsi_ienable(); 657 splx(s); 658 return 0; 659 660 scsi_timeout_error: 661 /* 662 * Clear the DMA mode. 663 */ 664 SET_5380_REG(NCR5380_MODE, GET_5380_REG(NCR5380_MODE) & ~SC_M_DMA); 665 return -1; 666 } 667 #endif /* if USE_PDMA */ 668 669 /* Include general routines. */ 670 #include <mac68k/dev/ncr5380.c> 671
Indexes created Thu Oct 02 07:10:07 GMT 2025