mac68k5380.c revision 1.17
1 /* $NetBSD: mac68k5380.c,v 1.17 1996/01/24 06:02:06 briggs Exp $ */ 2 3 /* 4 * Copyright (c) 1995 Allen Briggs 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Allen Briggs 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * Derived from atari5380.c for the mac68k port of NetBSD. 33 * 34 */ 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/kernel.h> 39 #include <sys/device.h> 40 #include <sys/dkstat.h> 41 #include <sys/syslog.h> 42 #include <sys/buf.h> 43 #include <scsi/scsi_all.h> 44 #include <scsi/scsi_message.h> 45 #include <scsi/scsiconf.h> 46 47 /* 48 * Include the driver definitions 49 */ 50 #include <mac68k/dev/ncr5380reg.h> 51 52 #include <machine/stdarg.h> 53 54 #include "../mac68k/via.h" 55 56 /* 57 * Set the various driver options 58 */ 59 #define NREQ 18 /* Size of issue queue */ 60 #define AUTO_SENSE 1 /* Automatically issue a request-sense */ 61 62 #define DRNAME ncrscsi /* used in various prints */ 63 #undef DBG_SEL /* Show the selection process */ 64 #undef DBG_REQ /* Show enqueued/ready requests */ 65 #undef DBG_NOWRITE /* Do not allow writes to the targets */ 66 #undef DBG_PIO /* Show the polled-I/O process */ 67 #undef DBG_INF /* Show information transfer process */ 68 #define DBG_NOSTATIC /* No static functions, all in DDB trace*/ 69 #define DBG_PID 20 /* Keep track of driver */ 70 #undef REAL_DMA /* Use DMA if sensible */ 71 #define fair_to_keep_dma() 1 72 #define claimed_dma() 1 73 #define reconsider_dma() 74 #define USE_PDMA 1 /* Use special pdma-transfer function */ 75 #define MIN_PHYS 0x2000 /* pdma space w/ /DSACK is only 0x2000 */ 76 77 #define ENABLE_NCR5380(sc) cur_softc = sc; 78 79 /* 80 * softc of currently active controller (well, we only have one for now). 81 */ 82 83 static struct ncr_softc *cur_softc; 84 85 struct scsi_5380 { 86 volatile u_char scsi_5380[8*16]; /* 8 regs, 1 every 16th byte. */ 87 }; 88 89 extern vm_offset_t SCSIBase; 90 static volatile u_char *ncr = (volatile u_char *) 0x10000; 91 static volatile u_char *ncr_5380_with_drq = (volatile u_char *) 0x6000; 92 static volatile u_char *ncr_5380_without_drq = (volatile u_char *) 0x12000; 93 94 static volatile u_char *scsi_enable = NULL; 95 96 #define SCSI_5380 ((struct scsi_5380 *) ncr) 97 #define GET_5380_REG(rnum) SCSI_5380->scsi_5380[((rnum)<<4)] 98 #define SET_5380_REG(rnum,val) (SCSI_5380->scsi_5380[((rnum)<<4)] = (val)) 99 100 void ncr5380_irq_intr(void *); 101 void ncr5380_drq_intr(void *); 102 103 static __inline__ void 104 scsi_clr_ipend() 105 { 106 int tmp; 107 108 tmp = GET_5380_REG(NCR5380_IRCV); 109 } 110 111 extern __inline__ void 112 scsi_ienable() 113 { 114 int s; 115 116 s = splhigh(); 117 *scsi_enable = 0x80 | (V2IF_SCSIIRQ | V2IF_SCSIDRQ); 118 splx(s); 119 } 120 121 extern __inline__ void 122 scsi_idisable() 123 { 124 int s; 125 126 s = splhigh(); 127 *scsi_enable = V2IF_SCSIIRQ | V2IF_SCSIDRQ; 128 splx(s); 129 } 130 131 static void 132 scsi_mach_init(sc) 133 struct ncr_softc *sc; 134 { 135 static int initted = 0; 136 137 if (initted++) 138 panic("scsi_mach_init called again.\n"); 139 140 ncr = (volatile u_char *) 141 (SCSIBase + (u_long) ncr); 142 ncr_5380_with_drq = (volatile u_char *) 143 (SCSIBase + (u_int) ncr_5380_with_drq); 144 ncr_5380_without_drq = (volatile u_char *) 145 (SCSIBase + (u_int) ncr_5380_without_drq); 146 147 if (VIA2 == VIA2OFF) 148 scsi_enable = Via1Base + VIA2 * 0x2000 + vIER; 149 else 150 scsi_enable = Via1Base + VIA2 * 0x2000 + rIER; 151 152 mac68k_register_scsi_irq(ncr5380_irq_intr, sc); 153 mac68k_register_scsi_drq(ncr5380_drq_intr, sc); 154 } 155 156 static int 157 machine_match(pdp, cdp, auxp, cd) 158 struct device *pdp; 159 struct cfdata *cdp; 160 void *auxp; 161 struct cfdriver *cd; 162 { 163 if (matchbyname(pdp, cdp, auxp) == 0) 164 return 0; 165 if (!mac68k_machine.scsi80) 166 return 0; 167 if (cdp->cf_unit != 0) 168 return 0; 169 return 1; 170 } 171 172 #if USE_PDMA 173 int pdma_5380_dir = 0; 174 175 u_char *pending_5380_data; 176 u_long pending_5380_count; 177 178 #define NCR5380_PDMA_DEBUG 1 /* Maybe we try with this off eventually. */ 179 180 #if NCR5380_PDMA_DEBUG 181 int pdma_5380_sends = 0; 182 int pdma_5380_bytes = 0; 183 184 char *pdma_5380_state="", *pdma_5380_prev_state=""; 185 #define DBG_SET(x) {pdma_5380_prev_state=pdma_5380_state; pdma_5380_state=(x);} 186 187 void 188 pdma_stat() 189 { 190 printf("PDMA SCSI: %d xfers completed for %d bytes.\n", 191 pdma_5380_sends, pdma_5380_bytes); 192 printf("pdma_5380_dir = %d\t", 193 pdma_5380_dir); 194 printf("datap = 0x%x, remainder = %d.\n", 195 pending_5380_data, pending_5380_count); 196 printf("state: %s\t", pdma_5380_state); 197 printf("last state: %s\n", pdma_5380_prev_state); 198 scsi_show(); 199 } 200 #endif 201 202 void 203 pdma_cleanup(void) 204 { 205 SC_REQ *reqp = connected; 206 int bytes, s; 207 208 s = splbio(); 209 210 pdma_5380_dir = 0; 211 212 #if NCR5380_PDMA_DEBUG 213 DBG_SET("in pdma_cleanup().") 214 pdma_5380_sends++; 215 pdma_5380_bytes+=(reqp->xdata_len - pending_5380_count); 216 #endif 217 218 /* 219 * Update pointers. 220 */ 221 reqp->xdata_ptr += reqp->xdata_len - pending_5380_count; 222 reqp->xdata_len = pending_5380_count; 223 224 /* 225 * Reset DMA mode. 226 */ 227 SET_5380_REG(NCR5380_MODE, GET_5380_REG(NCR5380_MODE) & ~SC_M_DMA); 228 229 /* 230 * Clear any pending interrupts. 231 */ 232 scsi_clr_ipend(); 233 234 /* 235 * Tell interrupt functions that DMA has ended. 236 */ 237 reqp->dr_flag &= ~DRIVER_IN_DMA; 238 239 SET_5380_REG(NCR5380_MODE, IMODE_BASE); 240 SET_5380_REG(NCR5380_ICOM, 0); 241 242 splx(s); 243 244 /* 245 * Back for more punishment. 246 */ 247 #if NCR5380_PDMA_DEBUG 248 pdma_5380_state = "pdma_cleanup() -- going back to run_main()."; 249 #endif 250 run_main(cur_softc); 251 #if NCR5380_PDMA_DEBUG 252 pdma_5380_state = "pdma_cleanup() -- back from run_main()."; 253 #endif 254 } 255 #endif 256 257 static __inline__ int 258 pdma_ready() 259 { 260 #if USE_PDMA 261 SC_REQ *reqp = connected; 262 int dmstat, idstat; 263 extern u_char ncr5380_no_parchk; 264 265 if (pdma_5380_dir) { 266 #if NCR5380_PDMA_DEBUG 267 DBG_SET("got irq interrupt in xfer.") 268 #endif 269 /* 270 * If Mr. IRQ isn't set one might wonder how we got 271 * here. It does happen, though. 272 */ 273 dmstat = GET_5380_REG(NCR5380_DMSTAT); 274 if (!(dmstat & SC_IRQ_SET)) { 275 #if NCR5380_PDMA_DEBUG 276 DBG_SET("irq not set.") 277 #endif 278 return 0; 279 } 280 /* 281 * For a phase mis-match, ATN is a "don't care," IRQ is 1 and 282 * all other bits in the Bus & Status Register are 0. Also, 283 * the current SCSI Bus Status Register has a 1 for BSY and 284 * REQ. Since we're just checking that this interrupt isn't a 285 * reselection or a reset, we just check for either. 286 */ 287 idstat = GET_5380_REG(NCR5380_IDSTAT); 288 if ( ((dmstat & (0xff & ~SC_ATN_STAT)) == SC_IRQ_SET) 289 && ((idstat & (SC_S_BSY|SC_S_REQ)) 290 == (SC_S_BSY | SC_S_REQ)) ) { 291 #if NCR5380_PDMA_DEBUG 292 DBG_SET("BSY|REQ.") 293 #endif 294 pdma_cleanup(); 295 return 1; 296 } else if (PH_IN(reqp->phase) && (dmstat & SC_PAR_ERR)) { 297 if (!(ncr5380_no_parchk & (1 << reqp->targ_id))) 298 /* XXX: Should be parity error ???? */ 299 reqp->xs->error = XS_DRIVER_STUFFUP; 300 #if NCR5380_PDMA_DEBUG 301 DBG_SET("PARITY.") 302 #endif 303 /* XXX: is this the right reaction? */ 304 pdma_cleanup(); 305 return 1; 306 } else if ( !(idstat & SC_S_REQ) 307 || (((idstat>>2) & 7) != reqp->phase)) { 308 #ifdef DIAGNOSTIC 309 /* XXX: is this the right reaction? Can this happen? */ 310 scsi_show(); 311 printf("Unexpected phase change.\n"); 312 #endif 313 reqp->xs->error = XS_DRIVER_STUFFUP; 314 pdma_cleanup(); 315 return 1; 316 } else { 317 scsi_show(); 318 panic("Spurious interrupt during PDMA xfer.\n"); 319 } 320 } 321 #endif 322 return 0; 323 } 324 325 void 326 ncr5380_irq_intr(p) 327 void *p; 328 { 329 struct ncr_softc *sc = p; 330 331 #if USE_PDMA 332 if (pdma_ready()) { 333 return; 334 } 335 #endif 336 if (GET_5380_REG(NCR5380_DMSTAT) & SC_IRQ_SET) { 337 scsi_idisable(); 338 ncr_ctrl_intr(cur_softc); 339 } 340 } 341 342 /* 343 * This is the meat of the PDMA transfer. 344 * When we get here, we shove data as fast as the mac can take it. 345 * We depend on several things: 346 * * All macs after the Mac Plus that have a 5380 chip should have a general 347 * logic IC that handshakes data for blind transfers. 348 * * If the SCSI controller finishes sending/receiving data before we do, 349 * the same general logic IC will generate a /BERR for us in short order. 350 * * The fault address for said /BERR minus the base address for the 351 * transfer will be the amount of data that was actually written. 352 * 353 * We use the nofault flag and the setjmp/longjmp in locore.s so we can 354 * detect and handle the bus error for early termination of a command. 355 * This is usually caused by a disconnecting target. 356 */ 357 void 358 ncr5380_drq_intr(p) 359 void *p; 360 { 361 #if USE_PDMA 362 extern int *nofault, mac68k_buserr_addr; 363 struct ncr_softc *sc = p; 364 label_t faultbuf; 365 register int count; 366 volatile u_int32_t *long_drq; 367 u_int32_t *long_data; 368 volatile u_int8_t *drq; 369 u_int8_t *data; 370 371 /* 372 * If we're not ready to xfer data, just return. 373 */ 374 if ( !(GET_5380_REG(NCR5380_DMSTAT) & SC_DMA_REQ) 375 || !pdma_5380_dir) { 376 return; 377 } 378 379 /* 380 * I don't think this should be necessary, but it is 381 * for writes--at least to some devices. They don't 382 * let go of PH_DATAOUT until we do pdma_cleanup(). 383 */ 384 if (pending_5380_count == 0) { 385 #if NCR5380_PDMA_DEBUG 386 DBG_SET("forcing pdma_cleanup().") 387 #endif 388 pdma_cleanup(); 389 return; 390 } 391 392 #if NCR5380_PDMA_DEBUG 393 DBG_SET("got drq interrupt.") 394 #endif 395 396 /* 397 * Setup for a possible bus error caused by SCSI controller 398 * switching out of DATA-IN/OUT before we're done with the 399 * current transfer. 400 */ 401 nofault = (int *) &faultbuf; 402 403 if (setjmp((label_t *) nofault)) { 404 nofault = (int *) 0; 405 #if NCR5380_PDMA_DEBUG 406 DBG_SET("buserr in xfer.") 407 #endif 408 count = ( (u_long) mac68k_buserr_addr 409 - (u_long) ncr_5380_with_drq); 410 if ((count < 0) || (count > pending_5380_count)) { 411 printf("pdma %s: count = %d (0x%x) (pending " 412 "count %d)\n", 413 (pdma_5380_dir == 2) ? "in" : "out", 414 count, count, pending_5380_count); 415 panic("something is wrong"); 416 } 417 418 pending_5380_data += count; 419 pending_5380_count -= count; 420 421 #if NCR5380_PDMA_DEBUG 422 DBG_SET("handled bus error in xfer.") 423 #endif 424 mac68k_buserr_addr = 0; 425 return; 426 } 427 428 if (pdma_5380_dir == 2) { /* Data In */ 429 int resid; 430 431 #if NCR5380_PDMA_DEBUG 432 DBG_SET("Data in.") 433 #endif 434 /* 435 * Get the dest address aligned. 436 */ 437 resid = count = min(pending_5380_count, 438 4 - (((int) pending_5380_data) & 0x3)); 439 if (count && (count < 4)) { 440 #if NCR5380_PDMA_DEBUG 441 DBG_SET("Data in (aligning dest).") 442 #endif 443 data = (u_int8_t *) pending_5380_data; 444 drq = (u_int8_t *) ncr_5380_with_drq; 445 while (count) { 446 #define R1 *data++ = *drq++ 447 R1; count--; 448 #undef R1 449 } 450 pending_5380_data += resid; 451 pending_5380_count -= resid; 452 } 453 454 /* 455 * Get ready to start the transfer. 456 */ 457 while (pending_5380_count) { 458 int dcount; 459 460 #if NCR5380_PDMA_DEBUG 461 DBG_SET("Data in (starting read).") 462 #endif 463 dcount = count = min(pending_5380_count, MIN_PHYS); 464 long_drq = (volatile u_int32_t *) ncr_5380_with_drq; 465 long_data = (u_int32_t *) pending_5380_data; 466 467 #define R4 *long_data++ = *long_drq++ 468 while ( count >= 512 ) { 469 if (!(GET_5380_REG(NCR5380_DMSTAT) & SC_DMA_REQ)) { 470 nofault = (int *) 0; 471 472 pending_5380_data += (dcount - count); 473 pending_5380_count -= (dcount - count); 474 #if NCR5380_PDMA_DEBUG 475 DBG_SET("drq low") 476 #endif 477 return; 478 } 479 R4; R4; R4; R4; R4; R4; R4; R4; 480 R4; R4; R4; R4; R4; R4; R4; R4; /* 64 */ 481 R4; R4; R4; R4; R4; R4; R4; R4; 482 R4; R4; R4; R4; R4; R4; R4; R4; /* 128 */ 483 R4; R4; R4; R4; R4; R4; R4; R4; 484 R4; R4; R4; R4; R4; R4; R4; R4; 485 R4; R4; R4; R4; R4; R4; R4; R4; 486 R4; R4; R4; R4; R4; R4; R4; R4; /* 256 */ 487 R4; R4; R4; R4; R4; R4; R4; R4; 488 R4; R4; R4; R4; R4; R4; R4; R4; 489 R4; R4; R4; R4; R4; R4; R4; R4; 490 R4; R4; R4; R4; R4; R4; R4; R4; 491 R4; R4; R4; R4; R4; R4; R4; R4; 492 R4; R4; R4; R4; R4; R4; R4; R4; 493 R4; R4; R4; R4; R4; R4; R4; R4; 494 R4; R4; R4; R4; R4; R4; R4; R4; /* 512 */ 495 count -= 512; 496 } 497 while (count >= 4) { 498 R4; count -= 4; 499 } 500 #undef R4 501 #if NCR5380_PDMA_DEBUG 502 DBG_SET("Data in (finishing up).") 503 #endif 504 data = (u_int8_t *) long_data; 505 drq = (u_int8_t *) long_drq; 506 while (count) { 507 #define R1 *data++ = *drq++ 508 R1; count--; 509 #undef R1 510 } 511 pending_5380_count -= dcount; 512 pending_5380_data += dcount; 513 } 514 } else { 515 int resid; 516 517 #if NCR5380_PDMA_DEBUG 518 DBG_SET("Data out.") 519 #endif 520 /* 521 * Get the source address aligned. 522 */ 523 resid = count = min(pending_5380_count, 524 4 - (((int) pending_5380_data) & 0x3)); 525 if (count && (count < 4)) { 526 #if NCR5380_PDMA_DEBUG 527 DBG_SET("Data out (aligning dest).") 528 #endif 529 data = (u_int8_t *) pending_5380_data; 530 drq = (u_int8_t *) ncr_5380_with_drq; 531 while (count) { 532 #define W1 *drq++ = *data++ 533 W1; count--; 534 #undef W1 535 } 536 pending_5380_data += resid; 537 pending_5380_count -= resid; 538 } 539 540 /* 541 * Get ready to start the transfer. 542 */ 543 while (pending_5380_count) { 544 int dcount; 545 546 #if NCR5380_PDMA_DEBUG 547 DBG_SET("Data out (starting write).") 548 #endif 549 dcount = count = min(pending_5380_count, MIN_PHYS); 550 long_drq = (volatile u_int32_t *) ncr_5380_with_drq; 551 long_data = (u_int32_t *) pending_5380_data; 552 553 #define W4 *long_drq++ = *long_data++ 554 while ( count >= 64 ) { 555 W4; W4; W4; W4; W4; W4; W4; W4; 556 W4; W4; W4; W4; W4; W4; W4; W4; /* 64 */ 557 count -= 64; 558 } 559 while (count >= 4) { 560 W4; count -= 4; 561 } 562 #undef W4 563 #if NCR5380_PDMA_DEBUG 564 DBG_SET("Data out (cleaning up).") 565 #endif 566 data = (u_int8_t *) long_data; 567 drq = (u_int8_t *) long_drq; 568 while (count) { 569 #define W1 *drq++ = *data++ 570 W1; count--; 571 #undef W1 572 } 573 pending_5380_count -= dcount; 574 pending_5380_data += dcount; 575 } 576 } 577 578 /* 579 * OK. No bus error occurred above. Clear the nofault flag 580 * so we no longer short-circuit bus errors. 581 */ 582 nofault = (int *) 0; 583 584 #if NCR5380_PDMA_DEBUG 585 DBG_SET("done in xfer.") 586 #endif 587 588 #endif /* if USE_PDMA */ 589 } 590 591 #if USE_PDMA 592 593 #define SCSI_TIMEOUT_VAL 10000000 594 595 static int 596 transfer_pdma(phasep, data, count) 597 u_char *phasep; 598 u_char *data; 599 u_long *count; 600 { 601 SC_REQ *reqp = connected; 602 int len = *count, i, scsi_timeout = SCSI_TIMEOUT_VAL; 603 int s, err; 604 605 if (pdma_5380_dir) { 606 panic("ncrscsi: transfer_pdma called when operation already " 607 "pending.\n"); 608 } 609 #if NCR5380_PDMA_DEBUG 610 DBG_SET("in transfer_pdma.") 611 #endif 612 613 /* 614 * Don't bother with PDMA if we can't sleep or for small transfers. 615 */ 616 if (reqp->dr_flag & DRIVER_NOINT) { 617 #if NCR5380_PDMA_DEBUG 618 DBG_SET("pdma, actually using transfer_pio.") 619 #endif 620 transfer_pio(phasep, data, count, 0); 621 return -1; 622 } 623 624 /* 625 * We are probably already at spl2(), so this is likely a no-op. 626 * Paranoia. 627 */ 628 s = splbio(); 629 630 scsi_idisable(); 631 632 /* 633 * Match phases with target. 634 */ 635 SET_5380_REG(NCR5380_TCOM, *phasep); 636 637 /* 638 * Clear pending interrupts. 639 */ 640 scsi_clr_ipend(); 641 642 /* 643 * Wait until target asserts BSY. 644 */ 645 while ( ((GET_5380_REG(NCR5380_IDSTAT) & SC_S_BSY) == 0) 646 && (--scsi_timeout) ); 647 if (!scsi_timeout) { 648 #if DIAGNOSTIC 649 printf("scsi timeout: waiting for BSY in %s.\n", 650 (*phasep == PH_DATAOUT) ? "pdma_out" : "pdma_in"); 651 #endif 652 goto scsi_timeout_error; 653 } 654 655 /* 656 * Tell the driver that we're in DMA mode. 657 */ 658 reqp->dr_flag |= DRIVER_IN_DMA; 659 660 /* 661 * Load transfer values for DRQ interrupt handlers. 662 */ 663 pending_5380_data = data; 664 pending_5380_count = len; 665 666 #if NCR5380_PDMA_DEBUG 667 DBG_SET("setting up for interrupt.") 668 #endif 669 670 /* 671 * Set the transfer function to be called on DRQ interrupts. 672 * And note that we're waiting. 673 */ 674 switch (*phasep) { 675 default: 676 panic("Unexpected phase in transfer_pdma.\n"); 677 case PH_DATAOUT: 678 pdma_5380_dir = 1; 679 SET_5380_REG(NCR5380_ICOM, GET_5380_REG(NCR5380_ICOM)|SC_ADTB); 680 SET_5380_REG(NCR5380_MODE, GET_5380_REG(NCR5380_MODE)|SC_M_DMA); 681 SET_5380_REG(NCR5380_DMSTAT, 0); 682 break; 683 case PH_DATAIN: 684 pdma_5380_dir = 2; 685 SET_5380_REG(NCR5380_ICOM, 0); 686 SET_5380_REG(NCR5380_MODE, GET_5380_REG(NCR5380_MODE)|SC_M_DMA); 687 SET_5380_REG(NCR5380_IRCV, 0); 688 break; 689 } 690 691 #if NCR5380_PDMA_DEBUG 692 DBG_SET("wait for interrupt.") 693 #endif 694 695 /* 696 * Now that we're set up, enable interrupts and drop processor 697 * priority back down. 698 */ 699 scsi_ienable(); 700 splx(s); 701 return 0; 702 703 scsi_timeout_error: 704 /* 705 * Clear the DMA mode. 706 */ 707 SET_5380_REG(NCR5380_MODE, GET_5380_REG(NCR5380_MODE) & ~SC_M_DMA); 708 return -1; 709 } 710 #endif /* if USE_PDMA */ 711 712 /* Include general routines. */ 713 #include <mac68k/dev/ncr5380.c> 714
Indexes created Thu Oct 02 07:10:07 GMT 2025