mac68k5380.c revision 1.19
1 /* $NetBSD: mac68k5380.c,v 1.19 1996/02/19 02:51:03 briggs Exp $ */ 2 3 /* 4 * Copyright (c) 1995 Allen Briggs 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Allen Briggs 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * Derived from atari5380.c for the mac68k port of NetBSD. 33 * 34 */ 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/kernel.h> 39 #include <sys/device.h> 40 #include <sys/dkstat.h> 41 #include <sys/syslog.h> 42 #include <sys/buf.h> 43 #include <scsi/scsi_all.h> 44 #include <scsi/scsi_message.h> 45 #include <scsi/scsiconf.h> 46 47 /* 48 * Include the driver definitions 49 */ 50 #include <mac68k/dev/ncr5380reg.h> 51 52 #include <machine/stdarg.h> 53 54 #include "../mac68k/via.h" 55 56 /* 57 * Set the various driver options 58 */ 59 #define NREQ 18 /* Size of issue queue */ 60 #define AUTO_SENSE 1 /* Automatically issue a request-sense */ 61 62 #define DRNAME ncrscsi /* used in various prints */ 63 #undef DBG_SEL /* Show the selection process */ 64 #undef DBG_REQ /* Show enqueued/ready requests */ 65 #undef DBG_NOWRITE /* Do not allow writes to the targets */ 66 #undef DBG_PIO /* Show the polled-I/O process */ 67 #undef DBG_INF /* Show information transfer process */ 68 #define DBG_NOSTATIC /* No static functions, all in DDB trace*/ 69 #define DBG_PID 25 /* Keep track of driver */ 70 #ifdef DBG_NOSTATIC 71 # define static 72 #endif 73 #ifdef DBG_SEL 74 # define DBG_SELPRINT(a,b) printf(a,b) 75 #else 76 # define DBG_SELPRINT(a,b) 77 #endif 78 #ifdef DBG_PIO 79 # define DBG_PIOPRINT(a,b,c) printf(a,b,c) 80 #else 81 # define DBG_PIOPRINT(a,b,c) 82 #endif 83 #ifdef DBG_INF 84 # define DBG_INFPRINT(a,b,c) a(b,c) 85 #else 86 # define DBG_INFPRINT(a,b,c) 87 #endif 88 #ifdef DBG_PID 89 /* static char *last_hit = NULL, *olast_hit = NULL; */ 90 static char *last_hit[DBG_PID]; 91 # define PID(a) \ 92 { int i; \ 93 for (i=0; i< DBG_PID-1; i++) \ 94 last_hit[i] = last_hit[i+1]; \ 95 last_hit[DBG_PID-1] = a; } 96 #else 97 # define PID(a) 98 #endif 99 100 #undef REAL_DMA /* Use DMA if sensible */ 101 #define scsi_ipending() (GET_5380_REG(NCR5380_DMSTAT) & SC_IRQ_SET) 102 #define fair_to_keep_dma() 1 103 #define claimed_dma() 1 104 #define reconsider_dma() 105 #define USE_PDMA 1 /* Use special pdma-transfer function */ 106 #define MIN_PHYS 0x2000 /* pdma space w/ /DSACK is only 0x2000 */ 107 108 #define ENABLE_NCR5380(sc) cur_softc = sc; 109 110 /* 111 * softc of currently active controller (well, we only have one for now). 112 */ 113 114 static struct ncr_softc *cur_softc; 115 116 struct scsi_5380 { 117 volatile u_char scsi_5380[8*16]; /* 8 regs, 1 every 16th byte. */ 118 }; 119 120 extern vm_offset_t SCSIBase; 121 static volatile u_char *ncr = (volatile u_char *) 0x10000; 122 static volatile u_char *ncr_5380_with_drq = (volatile u_char *) 0x6000; 123 static volatile u_char *ncr_5380_without_drq = (volatile u_char *) 0x12000; 124 125 static volatile u_char *scsi_enable = NULL; 126 127 #define SCSI_5380 ((struct scsi_5380 *) ncr) 128 #define GET_5380_REG(rnum) SCSI_5380->scsi_5380[((rnum)<<4)] 129 #define SET_5380_REG(rnum,val) (SCSI_5380->scsi_5380[((rnum)<<4)] = (val)) 130 131 void ncr5380_irq_intr(void *); 132 void ncr5380_drq_intr(void *); 133 134 static __inline__ void 135 scsi_clr_ipend() 136 { 137 int tmp; 138 139 tmp = GET_5380_REG(NCR5380_IRCV); 140 } 141 142 extern __inline__ void 143 scsi_ienable() 144 { 145 int s; 146 147 s = splhigh(); 148 *scsi_enable = 0x80 | (V2IF_SCSIIRQ | V2IF_SCSIDRQ); 149 splx(s); 150 } 151 152 extern __inline__ void 153 scsi_idisable() 154 { 155 int s; 156 157 s = splhigh(); 158 *scsi_enable = V2IF_SCSIIRQ | V2IF_SCSIDRQ; 159 splx(s); 160 } 161 162 static void 163 scsi_mach_init(sc) 164 struct ncr_softc *sc; 165 { 166 static int initted = 0; 167 168 if (initted++) 169 panic("scsi_mach_init called again.\n"); 170 171 ncr = (volatile u_char *) 172 (SCSIBase + (u_long) ncr); 173 ncr_5380_with_drq = (volatile u_char *) 174 (SCSIBase + (u_int) ncr_5380_with_drq); 175 ncr_5380_without_drq = (volatile u_char *) 176 (SCSIBase + (u_int) ncr_5380_without_drq); 177 178 if (VIA2 == VIA2OFF) 179 scsi_enable = Via1Base + VIA2 * 0x2000 + vIER; 180 else 181 scsi_enable = Via1Base + VIA2 * 0x2000 + rIER; 182 183 mac68k_register_scsi_irq(ncr5380_irq_intr, sc); 184 mac68k_register_scsi_drq(ncr5380_drq_intr, sc); 185 } 186 187 static int 188 machine_match(pdp, cdp, auxp, cd) 189 struct device *pdp; 190 struct cfdata *cdp; 191 void *auxp; 192 struct cfdriver *cd; 193 { 194 if (matchbyname(pdp, cdp, auxp) == 0) 195 return 0; 196 if (!mac68k_machine.scsi80) 197 return 0; 198 if (cdp->cf_unit != 0) 199 return 0; 200 return 1; 201 } 202 203 #if USE_PDMA 204 int pdma_5380_dir = 0; 205 206 u_char *pending_5380_data; 207 u_long pending_5380_count; 208 209 #define NCR5380_PDMA_DEBUG 1 /* Maybe we try with this off eventually. */ 210 211 #if NCR5380_PDMA_DEBUG 212 int pdma_5380_sends = 0; 213 int pdma_5380_bytes = 0; 214 215 void 216 pdma_stat() 217 { 218 printf("PDMA SCSI: %d xfers completed for %d bytes.\n", 219 pdma_5380_sends, pdma_5380_bytes); 220 printf("pdma_5380_dir = %d\t", 221 pdma_5380_dir); 222 printf("datap = 0x%x, remainder = %d.\n", 223 pending_5380_data, pending_5380_count); 224 scsi_show(); 225 } 226 #endif 227 228 void 229 pdma_cleanup(void) 230 { 231 SC_REQ *reqp = connected; 232 int bytes, s; 233 234 s = splbio(); 235 PID("pdma_cleanup0"); 236 237 pdma_5380_dir = 0; 238 239 #if NCR5380_PDMA_DEBUG 240 pdma_5380_sends++; 241 pdma_5380_bytes+=(reqp->xdata_len - pending_5380_count); 242 #endif 243 244 /* 245 * Update pointers. 246 */ 247 reqp->xdata_ptr += reqp->xdata_len - pending_5380_count; 248 reqp->xdata_len = pending_5380_count; 249 250 /* 251 * Reset DMA mode. 252 */ 253 SET_5380_REG(NCR5380_MODE, GET_5380_REG(NCR5380_MODE) & ~SC_M_DMA); 254 255 /* 256 * Clear any pending interrupts. 257 */ 258 scsi_clr_ipend(); 259 260 /* 261 * Tell interrupt functions that DMA has ended. 262 */ 263 reqp->dr_flag &= ~DRIVER_IN_DMA; 264 265 SET_5380_REG(NCR5380_MODE, IMODE_BASE); 266 SET_5380_REG(NCR5380_ICOM, 0); 267 268 splx(s); 269 270 /* 271 * Back for more punishment. 272 */ 273 PID("pdma_cleanup1"); 274 run_main(cur_softc); 275 PID("pdma_cleanup2"); 276 } 277 #endif 278 279 static __inline__ int 280 pdma_ready() 281 { 282 #if USE_PDMA 283 SC_REQ *reqp = connected; 284 int dmstat, idstat; 285 extern u_char ncr5380_no_parchk; 286 287 PID("pdma_ready0"); 288 if (pdma_5380_dir) { 289 PID("pdma_ready1.") 290 /* 291 * If Mr. IRQ isn't set one might wonder how we got 292 * here. It does happen, though. 293 */ 294 dmstat = GET_5380_REG(NCR5380_DMSTAT); 295 if (!(dmstat & SC_IRQ_SET)) { 296 PID("pdma_ready2"); 297 return 0; 298 } 299 /* 300 * For a phase mis-match, ATN is a "don't care," IRQ is 1 and 301 * all other bits in the Bus & Status Register are 0. Also, 302 * the current SCSI Bus Status Register has a 1 for BSY and 303 * REQ. Since we're just checking that this interrupt isn't a 304 * reselection or a reset, we just check for either. 305 */ 306 idstat = GET_5380_REG(NCR5380_IDSTAT); 307 if ( ((dmstat & (0xff & ~SC_ATN_STAT)) == SC_IRQ_SET) 308 && ((idstat & (SC_S_BSY|SC_S_REQ)) 309 == (SC_S_BSY | SC_S_REQ)) ) { 310 PID("pdma_ready3"); 311 pdma_cleanup(); 312 return 1; 313 } else if (PH_IN(reqp->phase) && (dmstat & SC_PAR_ERR)) { 314 if (!(ncr5380_no_parchk & (1 << reqp->targ_id))) 315 /* XXX: Should be parity error ???? */ 316 reqp->xs->error = XS_DRIVER_STUFFUP; 317 PID("pdma_ready4"); 318 /* XXX: is this the right reaction? */ 319 pdma_cleanup(); 320 return 1; 321 } else if ( !(idstat & SC_S_REQ) 322 || (((idstat>>2) & 7) != reqp->phase)) { 323 #ifdef DIAGNOSTIC 324 /* XXX: is this the right reaction? Can this happen? */ 325 scsi_show(); 326 printf("Unexpected phase change.\n"); 327 #endif 328 reqp->xs->error = XS_DRIVER_STUFFUP; 329 pdma_cleanup(); 330 return 1; 331 } else { 332 scsi_show(); 333 panic("Spurious interrupt during PDMA xfer.\n"); 334 } 335 } else 336 PID("pdma_ready5"); 337 #endif 338 return 0; 339 } 340 341 void 342 ncr5380_irq_intr(p) 343 void *p; 344 { 345 struct ncr_softc *sc = p; 346 347 PID("irq"); 348 #if USE_PDMA 349 if (pdma_ready()) { 350 return; 351 } 352 #endif 353 if (GET_5380_REG(NCR5380_DMSTAT) & SC_IRQ_SET) { 354 scsi_idisable(); 355 ncr_ctrl_intr(cur_softc); 356 } 357 } 358 359 /* 360 * This is the meat of the PDMA transfer. 361 * When we get here, we shove data as fast as the mac can take it. 362 * We depend on several things: 363 * * All macs after the Mac Plus that have a 5380 chip should have a general 364 * logic IC that handshakes data for blind transfers. 365 * * If the SCSI controller finishes sending/receiving data before we do, 366 * the same general logic IC will generate a /BERR for us in short order. 367 * * The fault address for said /BERR minus the base address for the 368 * transfer will be the amount of data that was actually written. 369 * 370 * We use the nofault flag and the setjmp/longjmp in locore.s so we can 371 * detect and handle the bus error for early termination of a command. 372 * This is usually caused by a disconnecting target. 373 */ 374 void 375 ncr5380_drq_intr(p) 376 void *p; 377 { 378 #if USE_PDMA 379 extern int *nofault, mac68k_buserr_addr; 380 struct ncr_softc *sc = p; 381 label_t faultbuf; 382 register int count; 383 volatile u_int32_t *long_drq; 384 u_int32_t *long_data; 385 volatile u_int8_t *drq; 386 u_int8_t *data; 387 388 /* 389 * If we're not ready to xfer data, just return. 390 */ 391 if ( !(GET_5380_REG(NCR5380_DMSTAT) & SC_DMA_REQ) 392 || !pdma_5380_dir) { 393 PID("drq0"); 394 return; 395 } 396 397 /* 398 * I don't think this should be necessary, but it is 399 * for writes--at least to some devices. They don't 400 * let go of PH_DATAOUT until we do pdma_cleanup(). 401 */ 402 if (pending_5380_count == 0) { 403 #if DBG_PID 404 if (pdma_5380_dir == 2) { 405 PID("drq1 (in)"); 406 } else { 407 PID("drq1 (out)"); 408 } 409 #endif 410 pdma_cleanup(); 411 return; 412 } 413 414 #if DBG_PID 415 if (pdma_5380_dir == 2) { 416 PID("drq (in)"); 417 } else { 418 PID("drq (out)"); 419 } 420 #endif 421 422 /* 423 * Setup for a possible bus error caused by SCSI controller 424 * switching out of DATA-IN/OUT before we're done with the 425 * current transfer. 426 */ 427 nofault = (int *) &faultbuf; 428 429 if (setjmp((label_t *) nofault)) { 430 PID("drq berr"); 431 nofault = (int *) 0; 432 count = ( (u_long) mac68k_buserr_addr 433 - (u_long) ncr_5380_with_drq); 434 if ((count < 0) || (count > pending_5380_count)) { 435 printf("pdma %s: count = %d (0x%x) (pending " 436 "count %d)\n", 437 (pdma_5380_dir == 2) ? "in" : "out", 438 count, count, pending_5380_count); 439 panic("something is wrong"); 440 } 441 442 pending_5380_data += count; 443 pending_5380_count -= count; 444 445 PID("end drq early"); 446 mac68k_buserr_addr = 0; 447 return; 448 } 449 450 if (pdma_5380_dir == 2) { /* Data In */ 451 int resid; 452 453 /* 454 * Get the dest address aligned. 455 */ 456 resid = count = min(pending_5380_count, 457 4 - (((int) pending_5380_data) & 0x3)); 458 if (count && (count < 4)) { 459 data = (u_int8_t *) pending_5380_data; 460 drq = (u_int8_t *) ncr_5380_with_drq; 461 while (count) { 462 #define R1 *data++ = *drq++ 463 R1; count--; 464 #undef R1 465 } 466 pending_5380_data += resid; 467 pending_5380_count -= resid; 468 } 469 470 /* 471 * Get ready to start the transfer. 472 */ 473 while (pending_5380_count) { 474 int dcount; 475 476 dcount = count = min(pending_5380_count, MIN_PHYS); 477 long_drq = (volatile u_int32_t *) ncr_5380_with_drq; 478 long_data = (u_int32_t *) pending_5380_data; 479 480 #define R4 *long_data++ = *long_drq++ 481 while ( count >= 512 ) { 482 if (!(GET_5380_REG(NCR5380_DMSTAT) & SC_DMA_REQ)) { 483 nofault = (int *) 0; 484 485 pending_5380_data += (dcount - count); 486 pending_5380_count -= (dcount - count); 487 return; 488 } 489 R4; R4; R4; R4; R4; R4; R4; R4; 490 R4; R4; R4; R4; R4; R4; R4; R4; /* 64 */ 491 R4; R4; R4; R4; R4; R4; R4; R4; 492 R4; R4; R4; R4; R4; R4; R4; R4; /* 128 */ 493 R4; R4; R4; R4; R4; R4; R4; R4; 494 R4; R4; R4; R4; R4; R4; R4; R4; 495 R4; R4; R4; R4; R4; R4; R4; R4; 496 R4; R4; R4; R4; R4; R4; R4; R4; /* 256 */ 497 R4; R4; R4; R4; R4; R4; R4; R4; 498 R4; R4; R4; R4; R4; R4; R4; R4; 499 R4; R4; R4; R4; R4; R4; R4; R4; 500 R4; R4; R4; R4; R4; R4; R4; R4; 501 R4; R4; R4; R4; R4; R4; R4; R4; 502 R4; R4; R4; R4; R4; R4; R4; R4; 503 R4; R4; R4; R4; R4; R4; R4; R4; 504 R4; R4; R4; R4; R4; R4; R4; R4; /* 512 */ 505 count -= 512; 506 } 507 while (count >= 4) { 508 R4; count -= 4; 509 } 510 #undef R4 511 data = (u_int8_t *) long_data; 512 drq = (u_int8_t *) long_drq; 513 while (count) { 514 #define R1 *data++ = *drq++ 515 R1; count--; 516 #undef R1 517 } 518 pending_5380_count -= dcount; 519 pending_5380_data += dcount; 520 } 521 } else { 522 int resid; 523 524 /* 525 * Get the source address aligned. 526 */ 527 resid = count = min(pending_5380_count, 528 4 - (((int) pending_5380_data) & 0x3)); 529 if (count && (count < 4)) { 530 data = (u_int8_t *) pending_5380_data; 531 drq = (u_int8_t *) ncr_5380_with_drq; 532 while (count) { 533 #define W1 *drq++ = *data++ 534 W1; count--; 535 #undef W1 536 } 537 pending_5380_data += resid; 538 pending_5380_count -= resid; 539 } 540 541 /* 542 * Get ready to start the transfer. 543 */ 544 while (pending_5380_count) { 545 int dcount; 546 547 dcount = count = min(pending_5380_count, MIN_PHYS); 548 long_drq = (volatile u_int32_t *) ncr_5380_with_drq; 549 long_data = (u_int32_t *) pending_5380_data; 550 551 #define W4 *long_drq++ = *long_data++ 552 while ( count >= 64 ) { 553 W4; W4; W4; W4; W4; W4; W4; W4; 554 W4; W4; W4; W4; W4; W4; W4; W4; /* 64 */ 555 count -= 64; 556 } 557 while (count >= 4) { 558 W4; count -= 4; 559 } 560 #undef W4 561 data = (u_int8_t *) long_data; 562 drq = (u_int8_t *) long_drq; 563 while (count) { 564 #define W1 *drq++ = *data++ 565 W1; count--; 566 #undef W1 567 } 568 pending_5380_count -= dcount; 569 pending_5380_data += dcount; 570 } 571 } 572 573 /* 574 * OK. No bus error occurred above. Clear the nofault flag 575 * so we no longer short-circuit bus errors. 576 */ 577 nofault = (int *) 0; 578 579 PID("end drq"); 580 #endif /* if USE_PDMA */ 581 } 582 583 #if USE_PDMA 584 585 #define SCSI_TIMEOUT_VAL 10000000 586 587 static int 588 transfer_pdma(phasep, data, count) 589 u_char *phasep; 590 u_char *data; 591 u_long *count; 592 { 593 SC_REQ *reqp = connected; 594 int len = *count, i, scsi_timeout = SCSI_TIMEOUT_VAL; 595 int s, err; 596 597 if (pdma_5380_dir) { 598 panic("ncrscsi: transfer_pdma called when operation already " 599 "pending.\n"); 600 } 601 PID("transfer_pdma0") 602 603 /* 604 * Don't bother with PDMA if we can't sleep or for small transfers. 605 */ 606 if (reqp->dr_flag & DRIVER_NOINT) { 607 PID("pdma, falling back to transfer_pio.") 608 transfer_pio(phasep, data, count, 0); 609 return -1; 610 } 611 612 /* 613 * We are probably already at spl2(), so this is likely a no-op. 614 * Paranoia. 615 */ 616 s = splbio(); 617 618 scsi_idisable(); 619 620 /* 621 * Match phases with target. 622 */ 623 SET_5380_REG(NCR5380_TCOM, *phasep); 624 625 /* 626 * Clear pending interrupts. 627 */ 628 scsi_clr_ipend(); 629 630 /* 631 * Wait until target asserts BSY. 632 */ 633 while ( ((GET_5380_REG(NCR5380_IDSTAT) & SC_S_BSY) == 0) 634 && (--scsi_timeout) ); 635 if (!scsi_timeout) { 636 #if DIAGNOSTIC 637 printf("scsi timeout: waiting for BSY in %s.\n", 638 (*phasep == PH_DATAOUT) ? "pdma_out" : "pdma_in"); 639 #endif 640 goto scsi_timeout_error; 641 } 642 643 /* 644 * Tell the driver that we're in DMA mode. 645 */ 646 reqp->dr_flag |= DRIVER_IN_DMA; 647 648 /* 649 * Load transfer values for DRQ interrupt handlers. 650 */ 651 pending_5380_data = data; 652 pending_5380_count = len; 653 654 /* 655 * Set the transfer function to be called on DRQ interrupts. 656 * And note that we're waiting. 657 */ 658 switch (*phasep) { 659 default: 660 panic("Unexpected phase in transfer_pdma.\n"); 661 case PH_DATAOUT: 662 pdma_5380_dir = 1; 663 SET_5380_REG(NCR5380_ICOM, GET_5380_REG(NCR5380_ICOM)|SC_ADTB); 664 SET_5380_REG(NCR5380_MODE, GET_5380_REG(NCR5380_MODE)|SC_M_DMA); 665 SET_5380_REG(NCR5380_DMSTAT, 0); 666 break; 667 case PH_DATAIN: 668 pdma_5380_dir = 2; 669 SET_5380_REG(NCR5380_ICOM, 0); 670 SET_5380_REG(NCR5380_MODE, GET_5380_REG(NCR5380_MODE)|SC_M_DMA); 671 SET_5380_REG(NCR5380_IRCV, 0); 672 break; 673 } 674 675 PID("waiting for interrupt.") 676 677 /* 678 * Now that we're set up, enable interrupts and drop processor 679 * priority back down. 680 */ 681 scsi_ienable(); 682 splx(s); 683 return 0; 684 685 scsi_timeout_error: 686 /* 687 * Clear the DMA mode. 688 */ 689 SET_5380_REG(NCR5380_MODE, GET_5380_REG(NCR5380_MODE) & ~SC_M_DMA); 690 return -1; 691 } 692 #endif /* if USE_PDMA */ 693 694 /* Include general routines. */ 695 #include <mac68k/dev/ncr5380.c> 696
Indexes created Thu Oct 02 07:10:07 GMT 2025