mac68k5380.c revision 1.23
1 /* $NetBSD: mac68k5380.c,v 1.23 1996/05/05 06:16:51 briggs Exp $ */ 2 3 /* 4 * Copyright (c) 1995 Allen Briggs 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Allen Briggs 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * Derived from atari5380.c for the mac68k port of NetBSD. 33 * 34 */ 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/kernel.h> 39 #include <sys/device.h> 40 #include <sys/dkstat.h> 41 #include <sys/syslog.h> 42 #include <sys/buf.h> 43 #include <scsi/scsi_all.h> 44 #include <scsi/scsi_message.h> 45 #include <scsi/scsiconf.h> 46 47 /* 48 * Include the driver definitions 49 */ 50 #include "ncr5380reg.h" 51 52 #include <machine/stdarg.h> 53 #include <machine/viareg.h> 54 55 #include "ncr5380var.h" 56 57 /* 58 * Set the various driver options 59 */ 60 #define NREQ 18 /* Size of issue queue */ 61 #define AUTO_SENSE 1 /* Automatically issue a request-sense */ 62 63 #define DRNAME ncrscsi /* used in various prints */ 64 #undef DBG_SEL /* Show the selection process */ 65 #undef DBG_REQ /* Show enqueued/ready requests */ 66 #undef DBG_NOWRITE /* Do not allow writes to the targets */ 67 #undef DBG_PIO /* Show the polled-I/O process */ 68 #undef DBG_INF /* Show information transfer process */ 69 #define DBG_NOSTATIC /* No static functions, all in DDB trace*/ 70 #define DBG_PID 25 /* Keep track of driver */ 71 #ifdef DBG_NOSTATIC 72 # define static 73 #endif 74 #ifdef DBG_SEL 75 # define DBG_SELPRINT(a,b) printf(a,b) 76 #else 77 # define DBG_SELPRINT(a,b) 78 #endif 79 #ifdef DBG_PIO 80 # define DBG_PIOPRINT(a,b,c) printf(a,b,c) 81 #else 82 # define DBG_PIOPRINT(a,b,c) 83 #endif 84 #ifdef DBG_INF 85 # define DBG_INFPRINT(a,b,c) a(b,c) 86 #else 87 # define DBG_INFPRINT(a,b,c) 88 #endif 89 #ifdef DBG_PID 90 /* static char *last_hit = NULL, *olast_hit = NULL; */ 91 static char *last_hit[DBG_PID]; 92 # define PID(a) \ 93 { int i; \ 94 for (i=0; i< DBG_PID-1; i++) \ 95 last_hit[i] = last_hit[i+1]; \ 96 last_hit[DBG_PID-1] = a; } 97 #else 98 # define PID(a) 99 #endif 100 101 #undef REAL_DMA /* Use DMA if sensible */ 102 #define scsi_ipending() (GET_5380_REG(NCR5380_DMSTAT) & SC_IRQ_SET) 103 #define fair_to_keep_dma() 1 104 #define claimed_dma() 1 105 #define reconsider_dma() 106 #define USE_PDMA 1 /* Use special pdma-transfer function */ 107 #define MIN_PHYS 0x2000 /* pdma space w/ /DSACK is only 0x2000 */ 108 109 #define ENABLE_NCR5380(sc) cur_softc = sc; 110 111 /* 112 * softc of currently active controller (well, we only have one for now). 113 */ 114 115 static struct ncr_softc *cur_softc; 116 117 struct scsi_5380 { 118 volatile u_char scsi_5380[8*16]; /* 8 regs, 1 every 16th byte. */ 119 }; 120 121 extern vm_offset_t SCSIBase; 122 static volatile u_char *ncr = (volatile u_char *) 0x10000; 123 static volatile u_char *ncr_5380_with_drq = (volatile u_char *) 0x6000; 124 static volatile u_char *ncr_5380_without_drq = (volatile u_char *) 0x12000; 125 126 #define SCSI_5380 ((struct scsi_5380 *) ncr) 127 #define GET_5380_REG(rnum) SCSI_5380->scsi_5380[((rnum)<<4)] 128 #define SET_5380_REG(rnum,val) (SCSI_5380->scsi_5380[((rnum)<<4)] = (val)) 129 130 void ncr5380_irq_intr(void *); 131 void ncr5380_drq_intr(void *); 132 133 static __inline__ void scsi_clr_ipend __P((void)); 134 static void scsi_mach_init __P((struct ncr_softc *sc)); 135 static int machine_match __P((struct device *pdp, void *match, 136 void *auxp, struct cfdriver *cd)); 137 static __inline__ int pdma_ready __P((void)); 138 static int transfer_pdma __P((u_char *phasep, u_char *data, 139 u_long *count)); 140 141 static __inline__ void 142 scsi_clr_ipend() 143 { 144 int tmp; 145 146 tmp = GET_5380_REG(NCR5380_IRCV); 147 } 148 149 static void 150 scsi_mach_init(sc) 151 struct ncr_softc *sc; 152 { 153 static int initted = 0; 154 155 if (initted++) 156 panic("scsi_mach_init called again.\n"); 157 158 ncr = (volatile u_char *) 159 (SCSIBase + (u_long) ncr); 160 ncr_5380_with_drq = (volatile u_char *) 161 (SCSIBase + (u_int) ncr_5380_with_drq); 162 ncr_5380_without_drq = (volatile u_char *) 163 (SCSIBase + (u_int) ncr_5380_without_drq); 164 165 if (VIA2 == VIA2OFF) 166 scsi_enable = Via1Base + VIA2 * 0x2000 + vIER; 167 else 168 scsi_enable = Via1Base + VIA2 * 0x2000 + rIER; 169 170 mac68k_register_scsi_irq(ncr5380_irq_intr, sc); 171 mac68k_register_scsi_drq(ncr5380_drq_intr, sc); 172 } 173 174 static int 175 machine_match(pdp, match, auxp, cd) 176 struct device *pdp; 177 void *match, *auxp; 178 struct cfdriver *cd; 179 { 180 if (!mac68k_machine.scsi80) 181 return 0; 182 return 1; 183 } 184 185 #if USE_PDMA 186 int pdma_5380_dir = 0; 187 188 u_char *pending_5380_data; 189 u_long pending_5380_count; 190 191 #define NCR5380_PDMA_DEBUG 1 /* Maybe we try with this off eventually. */ 192 193 #if NCR5380_PDMA_DEBUG 194 int pdma_5380_sends = 0; 195 int pdma_5380_bytes = 0; 196 197 void 198 pdma_stat() 199 { 200 printf("PDMA SCSI: %d xfers completed for %d bytes.\n", 201 pdma_5380_sends, pdma_5380_bytes); 202 printf("pdma_5380_dir = %d\t", 203 pdma_5380_dir); 204 printf("datap = %p, remainder = %ld.\n", 205 pending_5380_data, pending_5380_count); 206 scsi_show(); 207 } 208 #endif 209 210 void 211 pdma_cleanup(void) 212 { 213 SC_REQ *reqp = connected; 214 int s; 215 216 s = splbio(); 217 PID("pdma_cleanup0"); 218 219 pdma_5380_dir = 0; 220 221 #if NCR5380_PDMA_DEBUG 222 pdma_5380_sends++; 223 pdma_5380_bytes+=(reqp->xdata_len - pending_5380_count); 224 #endif 225 226 /* 227 * Update pointers. 228 */ 229 reqp->xdata_ptr += reqp->xdata_len - pending_5380_count; 230 reqp->xdata_len = pending_5380_count; 231 232 /* 233 * Reset DMA mode. 234 */ 235 SET_5380_REG(NCR5380_MODE, GET_5380_REG(NCR5380_MODE) & ~SC_M_DMA); 236 237 /* 238 * Clear any pending interrupts. 239 */ 240 scsi_clr_ipend(); 241 242 /* 243 * Tell interrupt functions that DMA has ended. 244 */ 245 reqp->dr_flag &= ~DRIVER_IN_DMA; 246 247 SET_5380_REG(NCR5380_MODE, IMODE_BASE); 248 SET_5380_REG(NCR5380_ICOM, 0); 249 250 splx(s); 251 252 /* 253 * Back for more punishment. 254 */ 255 PID("pdma_cleanup1"); 256 run_main(cur_softc); 257 PID("pdma_cleanup2"); 258 } 259 #endif 260 261 static __inline__ int 262 pdma_ready() 263 { 264 #if USE_PDMA 265 SC_REQ *reqp = connected; 266 int dmstat, idstat; 267 extern u_char ncr5380_no_parchk; 268 269 PID("pdma_ready0"); 270 if (pdma_5380_dir) { 271 PID("pdma_ready1.") 272 /* 273 * If Mr. IRQ isn't set one might wonder how we got 274 * here. It does happen, though. 275 */ 276 dmstat = GET_5380_REG(NCR5380_DMSTAT); 277 if (!(dmstat & SC_IRQ_SET)) { 278 PID("pdma_ready2"); 279 return 0; 280 } 281 /* 282 * For a phase mis-match, ATN is a "don't care," IRQ is 1 and 283 * all other bits in the Bus & Status Register are 0. Also, 284 * the current SCSI Bus Status Register has a 1 for BSY and 285 * REQ. Since we're just checking that this interrupt isn't a 286 * reselection or a reset, we just check for either. 287 */ 288 idstat = GET_5380_REG(NCR5380_IDSTAT); 289 if ( ((dmstat & (0xff & ~SC_ATN_STAT)) == SC_IRQ_SET) 290 && ((idstat & (SC_S_BSY|SC_S_REQ)) 291 == (SC_S_BSY | SC_S_REQ)) ) { 292 PID("pdma_ready3"); 293 pdma_cleanup(); 294 return 1; 295 } else if (PH_IN(reqp->phase) && (dmstat & SC_PAR_ERR)) { 296 if (!(ncr5380_no_parchk & (1 << reqp->targ_id))) 297 /* XXX: Should be parity error ???? */ 298 reqp->xs->error = XS_DRIVER_STUFFUP; 299 PID("pdma_ready4"); 300 /* XXX: is this the right reaction? */ 301 pdma_cleanup(); 302 return 1; 303 } else if ( !(idstat & SC_S_REQ) 304 || (((idstat>>2) & 7) != reqp->phase)) { 305 #ifdef DIAGNOSTIC 306 /* XXX: is this the right reaction? Can this happen? */ 307 scsi_show(); 308 printf("Unexpected phase change.\n"); 309 #endif 310 reqp->xs->error = XS_DRIVER_STUFFUP; 311 pdma_cleanup(); 312 return 1; 313 } else { 314 scsi_show(); 315 panic("Spurious interrupt during PDMA xfer.\n"); 316 } 317 } else 318 PID("pdma_ready5"); 319 #endif 320 return 0; 321 } 322 323 void 324 ncr5380_irq_intr(p) 325 void *p; 326 { 327 PID("irq"); 328 #if USE_PDMA 329 if (pdma_ready()) { 330 return; 331 } 332 #endif 333 if (GET_5380_REG(NCR5380_DMSTAT) & SC_IRQ_SET) { 334 scsi_idisable(); 335 ncr_ctrl_intr(cur_softc); 336 } 337 } 338 339 /* 340 * This is the meat of the PDMA transfer. 341 * When we get here, we shove data as fast as the mac can take it. 342 * We depend on several things: 343 * * All macs after the Mac Plus that have a 5380 chip should have a general 344 * logic IC that handshakes data for blind transfers. 345 * * If the SCSI controller finishes sending/receiving data before we do, 346 * the same general logic IC will generate a /BERR for us in short order. 347 * * The fault address for said /BERR minus the base address for the 348 * transfer will be the amount of data that was actually written. 349 * 350 * We use the nofault flag and the setjmp/longjmp in locore.s so we can 351 * detect and handle the bus error for early termination of a command. 352 * This is usually caused by a disconnecting target. 353 */ 354 void 355 ncr5380_drq_intr(p) 356 void *p; 357 { 358 #if USE_PDMA 359 extern int *nofault, mac68k_buserr_addr; 360 label_t faultbuf; 361 register int count; 362 volatile u_int32_t *long_drq; 363 u_int32_t *long_data; 364 volatile u_int8_t *drq; 365 u_int8_t *data; 366 367 /* 368 * If we're not ready to xfer data, just return. 369 */ 370 if ( !(GET_5380_REG(NCR5380_DMSTAT) & SC_DMA_REQ) 371 || !pdma_5380_dir) { 372 PID("drq0"); 373 return; 374 } 375 376 /* 377 * I don't think this should be necessary, but it is 378 * for writes--at least to some devices. They don't 379 * let go of PH_DATAOUT until we do pdma_cleanup(). 380 */ 381 if (pending_5380_count == 0) { 382 #if DBG_PID 383 if (pdma_5380_dir == 2) { 384 PID("drq1 (in)"); 385 } else { 386 PID("drq1 (out)"); 387 } 388 #endif 389 pdma_cleanup(); 390 return; 391 } 392 393 #if DBG_PID 394 if (pdma_5380_dir == 2) { 395 PID("drq (in)"); 396 } else { 397 PID("drq (out)"); 398 } 399 #endif 400 401 /* 402 * Setup for a possible bus error caused by SCSI controller 403 * switching out of DATA-IN/OUT before we're done with the 404 * current transfer. 405 */ 406 nofault = (int *) &faultbuf; 407 408 if (setjmp((label_t *) nofault)) { 409 PID("drq berr"); 410 nofault = (int *) 0; 411 count = ( (u_long) mac68k_buserr_addr 412 - (u_long) ncr_5380_with_drq); 413 if ((count < 0) || (count > pending_5380_count)) { 414 printf("pdma %s: cnt = %d (0x%x) (pending cnt %ld)\n", 415 (pdma_5380_dir == 2) ? "in" : "out", 416 count, count, pending_5380_count); 417 panic("something is wrong"); 418 } 419 420 pending_5380_data += count; 421 pending_5380_count -= count; 422 423 PID("end drq early"); 424 mac68k_buserr_addr = 0; 425 return; 426 } 427 428 if (pdma_5380_dir == 2) { /* Data In */ 429 int resid; 430 431 /* 432 * Get the dest address aligned. 433 */ 434 resid = count = min(pending_5380_count, 435 4 - (((int) pending_5380_data) & 0x3)); 436 if (count && (count < 4)) { 437 data = (u_int8_t *) pending_5380_data; 438 drq = (u_int8_t *) ncr_5380_with_drq; 439 while (count) { 440 #define R1 *data++ = *drq++ 441 R1; count--; 442 #undef R1 443 } 444 pending_5380_data += resid; 445 pending_5380_count -= resid; 446 } 447 448 /* 449 * Get ready to start the transfer. 450 */ 451 while (pending_5380_count) { 452 int dcount; 453 454 dcount = count = min(pending_5380_count, MIN_PHYS); 455 long_drq = (volatile u_int32_t *) ncr_5380_with_drq; 456 long_data = (u_int32_t *) pending_5380_data; 457 458 #define R4 *long_data++ = *long_drq++ 459 while ( count >= 512 ) { 460 if (!(GET_5380_REG(NCR5380_DMSTAT) & SC_DMA_REQ)) { 461 nofault = (int *) 0; 462 463 pending_5380_data += (dcount - count); 464 pending_5380_count -= (dcount - count); 465 return; 466 } 467 R4; R4; R4; R4; R4; R4; R4; R4; 468 R4; R4; R4; R4; R4; R4; R4; R4; /* 64 */ 469 R4; R4; R4; R4; R4; R4; R4; R4; 470 R4; R4; R4; R4; R4; R4; R4; R4; /* 128 */ 471 R4; R4; R4; R4; R4; R4; R4; R4; 472 R4; R4; R4; R4; R4; R4; R4; R4; 473 R4; R4; R4; R4; R4; R4; R4; R4; 474 R4; R4; R4; R4; R4; R4; R4; R4; /* 256 */ 475 R4; R4; R4; R4; R4; R4; R4; R4; 476 R4; R4; R4; R4; R4; R4; R4; R4; 477 R4; R4; R4; R4; R4; R4; R4; R4; 478 R4; R4; R4; R4; R4; R4; R4; R4; 479 R4; R4; R4; R4; R4; R4; R4; R4; 480 R4; R4; R4; R4; R4; R4; R4; R4; 481 R4; R4; R4; R4; R4; R4; R4; R4; 482 R4; R4; R4; R4; R4; R4; R4; R4; /* 512 */ 483 count -= 512; 484 } 485 while (count >= 4) { 486 R4; count -= 4; 487 } 488 #undef R4 489 data = (u_int8_t *) long_data; 490 drq = (u_int8_t *) long_drq; 491 while (count) { 492 #define R1 *data++ = *drq++ 493 R1; count--; 494 #undef R1 495 } 496 pending_5380_count -= dcount; 497 pending_5380_data += dcount; 498 } 499 } else { 500 int resid; 501 502 /* 503 * Get the source address aligned. 504 */ 505 resid = count = min(pending_5380_count, 506 4 - (((int) pending_5380_data) & 0x3)); 507 if (count && (count < 4)) { 508 data = (u_int8_t *) pending_5380_data; 509 drq = (u_int8_t *) ncr_5380_with_drq; 510 while (count) { 511 #define W1 *drq++ = *data++ 512 W1; count--; 513 #undef W1 514 } 515 pending_5380_data += resid; 516 pending_5380_count -= resid; 517 } 518 519 /* 520 * Get ready to start the transfer. 521 */ 522 while (pending_5380_count) { 523 int dcount; 524 525 dcount = count = min(pending_5380_count, MIN_PHYS); 526 long_drq = (volatile u_int32_t *) ncr_5380_with_drq; 527 long_data = (u_int32_t *) pending_5380_data; 528 529 #define W4 *long_drq++ = *long_data++ 530 while ( count >= 64 ) { 531 W4; W4; W4; W4; W4; W4; W4; W4; 532 W4; W4; W4; W4; W4; W4; W4; W4; /* 64 */ 533 count -= 64; 534 } 535 while (count >= 4) { 536 W4; count -= 4; 537 } 538 #undef W4 539 data = (u_int8_t *) long_data; 540 drq = (u_int8_t *) long_drq; 541 while (count) { 542 #define W1 *drq++ = *data++ 543 W1; count--; 544 #undef W1 545 } 546 pending_5380_count -= dcount; 547 pending_5380_data += dcount; 548 } 549 } 550 551 /* 552 * OK. No bus error occurred above. Clear the nofault flag 553 * so we no longer short-circuit bus errors. 554 */ 555 nofault = (int *) 0; 556 557 PID("end drq"); 558 #endif /* if USE_PDMA */ 559 } 560 561 #if USE_PDMA 562 563 #define SCSI_TIMEOUT_VAL 10000000 564 565 static int 566 transfer_pdma(phasep, data, count) 567 u_char *phasep; 568 u_char *data; 569 u_long *count; 570 { 571 SC_REQ *reqp = connected; 572 int len = *count, s, scsi_timeout = SCSI_TIMEOUT_VAL; 573 574 if (pdma_5380_dir) { 575 panic("ncrscsi: transfer_pdma called when operation already " 576 "pending.\n"); 577 } 578 PID("transfer_pdma0") 579 580 /* 581 * Don't bother with PDMA if we can't sleep or for small transfers. 582 */ 583 if (reqp->dr_flag & DRIVER_NOINT) { 584 PID("pdma, falling back to transfer_pio.") 585 transfer_pio(phasep, data, count, 0); 586 return -1; 587 } 588 589 /* 590 * We are probably already at spl2(), so this is likely a no-op. 591 * Paranoia. 592 */ 593 s = splbio(); 594 595 scsi_idisable(); 596 597 /* 598 * Match phases with target. 599 */ 600 SET_5380_REG(NCR5380_TCOM, *phasep); 601 602 /* 603 * Clear pending interrupts. 604 */ 605 scsi_clr_ipend(); 606 607 /* 608 * Wait until target asserts BSY. 609 */ 610 while ( ((GET_5380_REG(NCR5380_IDSTAT) & SC_S_BSY) == 0) 611 && (--scsi_timeout) ); 612 if (!scsi_timeout) { 613 #if DIAGNOSTIC 614 printf("scsi timeout: waiting for BSY in %s.\n", 615 (*phasep == PH_DATAOUT) ? "pdma_out" : "pdma_in"); 616 #endif 617 goto scsi_timeout_error; 618 } 619 620 /* 621 * Tell the driver that we're in DMA mode. 622 */ 623 reqp->dr_flag |= DRIVER_IN_DMA; 624 625 /* 626 * Load transfer values for DRQ interrupt handlers. 627 */ 628 pending_5380_data = data; 629 pending_5380_count = len; 630 631 /* 632 * Set the transfer function to be called on DRQ interrupts. 633 * And note that we're waiting. 634 */ 635 switch (*phasep) { 636 default: 637 panic("Unexpected phase in transfer_pdma.\n"); 638 case PH_DATAOUT: 639 pdma_5380_dir = 1; 640 SET_5380_REG(NCR5380_ICOM, GET_5380_REG(NCR5380_ICOM)|SC_ADTB); 641 SET_5380_REG(NCR5380_MODE, GET_5380_REG(NCR5380_MODE)|SC_M_DMA); 642 SET_5380_REG(NCR5380_DMSTAT, 0); 643 break; 644 case PH_DATAIN: 645 pdma_5380_dir = 2; 646 SET_5380_REG(NCR5380_ICOM, 0); 647 SET_5380_REG(NCR5380_MODE, GET_5380_REG(NCR5380_MODE)|SC_M_DMA); 648 SET_5380_REG(NCR5380_IRCV, 0); 649 break; 650 } 651 652 PID("waiting for interrupt.") 653 654 /* 655 * Now that we're set up, enable interrupts and drop processor 656 * priority back down. 657 */ 658 scsi_ienable(); 659 splx(s); 660 return 0; 661 662 scsi_timeout_error: 663 /* 664 * Clear the DMA mode. 665 */ 666 SET_5380_REG(NCR5380_MODE, GET_5380_REG(NCR5380_MODE) & ~SC_M_DMA); 667 return -1; 668 } 669 #endif /* if USE_PDMA */ 670 671 /* Include general routines. */ 672 #include <mac68k/dev/ncr5380.c> 673
Indexes created Thu Oct 02 14:10:14 GMT 2025