Home | History | Annotate | Line # | Download | only in dev
sbc.c revision 1.60
      1  1.60       nat /*	$NetBSD: sbc.c,v 1.60 2024/09/14 21:11:07 nat Exp $	*/
      2   1.1    scottr 
      3   1.1    scottr /*
      4  1.19    scottr  * Copyright (C) 1996 Scott Reynolds.  All rights reserved.
      5   1.1    scottr  *
      6   1.1    scottr  * Redistribution and use in source and binary forms, with or without
      7   1.1    scottr  * modification, are permitted provided that the following conditions
      8   1.1    scottr  * are met:
      9   1.1    scottr  * 1. Redistributions of source code must retain the above copyright
     10   1.1    scottr  *    notice, this list of conditions and the following disclaimer.
     11   1.1    scottr  * 2. Redistributions in binary form must reproduce the above copyright
     12   1.1    scottr  *    notice, this list of conditions and the following disclaimer in the
     13   1.1    scottr  *    documentation and/or other materials provided with the distribution.
     14  1.32    scottr  * 3. The name of the author may not be used to endorse or promote products
     15  1.19    scottr  *    derived from this software without specific prior written permission
     16   1.1    scottr  *
     17  1.19    scottr  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     18   1.1    scottr  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     19   1.1    scottr  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     20  1.19    scottr  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     21   1.1    scottr  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     22   1.1    scottr  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     23   1.1    scottr  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     24   1.1    scottr  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     25   1.1    scottr  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     26   1.1    scottr  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     27   1.1    scottr  */
     28   1.1    scottr 
     29   1.1    scottr /*
     30   1.1    scottr  * This file contains only the machine-dependent parts of the mac68k
     31   1.1    scottr  * NCR 5380 SCSI driver.  (Autoconfig stuff and PDMA functions.)
     32   1.1    scottr  * The machine-independent parts are in ncr5380sbc.c
     33   1.1    scottr  *
     34   1.1    scottr  * Supported hardware includes:
     35   1.1    scottr  * Macintosh II family 5380-based controller
     36   1.1    scottr  *
     37   1.1    scottr  * Credits, history:
     38   1.1    scottr  *
     39   1.1    scottr  * Scott Reynolds wrote this module, based on work by Allen Briggs
     40   1.9    scottr  * (mac68k), Gordon W. Ross and David Jones (sun3), and Leo Weppelman
     41   1.9    scottr  * (atari).  Thanks to Allen for supplying crucial interpretation of the
     42   1.9    scottr  * NetBSD/mac68k 1.1 'ncrscsi' driver.  Also, Allen, Gordon, and Jason
     43   1.9    scottr  * Thorpe all helped to refine this code, and were considerable sources
     44   1.9    scottr  * of moral support.
     45   1.1    scottr  */
     46  1.44     lukem 
     47  1.44     lukem #include <sys/cdefs.h>
     48  1.60       nat __KERNEL_RCSID(0, "$NetBSD: sbc.c,v 1.60 2024/09/14 21:11:07 nat Exp $");
     49  1.44     lukem 
     50  1.36  jonathan #include "opt_ddb.h"
     51   1.1    scottr 
     52   1.1    scottr #include <sys/types.h>
     53   1.1    scottr #include <sys/param.h>
     54   1.1    scottr #include <sys/systm.h>
     55   1.1    scottr #include <sys/kernel.h>
     56   1.1    scottr #include <sys/errno.h>
     57   1.1    scottr #include <sys/device.h>
     58   1.1    scottr #include <sys/buf.h>
     59   1.1    scottr #include <sys/proc.h>
     60   1.1    scottr 
     61  1.30    bouyer #include <dev/scsipi/scsi_all.h>
     62  1.30    bouyer #include <dev/scsipi/scsipi_all.h>
     63  1.30    bouyer #include <dev/scsipi/scsipi_debug.h>
     64  1.30    bouyer #include <dev/scsipi/scsiconf.h>
     65   1.1    scottr 
     66   1.1    scottr #include <dev/ic/ncr5380reg.h>
     67   1.1    scottr #include <dev/ic/ncr5380var.h>
     68   1.1    scottr 
     69   1.8    scottr #include <machine/cpu.h>
     70   1.1    scottr #include <machine/viareg.h>
     71   1.1    scottr 
     72  1.29    scottr #include <mac68k/dev/sbcreg.h>
     73  1.29    scottr #include <mac68k/dev/sbcvar.h>
     74  1.36  jonathan 
     75  1.36  jonathan /* SBC_DEBUG --  relies on DDB */
     76  1.36  jonathan #ifdef SBC_DEBUG
     77  1.36  jonathan # define	SBC_DB_INTR	0x01
     78  1.36  jonathan # define	SBC_DB_DMA	0x02
     79  1.36  jonathan # define	SBC_DB_REG	0x04
     80  1.36  jonathan # define	SBC_DB_BREAK	0x08
     81  1.36  jonathan # ifndef DDB
     82  1.36  jonathan #  define	Debugger()	printf("Debug: sbc.c:%d\n", __LINE__)
     83  1.36  jonathan # endif
     84  1.36  jonathan # define	SBC_BREAK \
     85  1.36  jonathan 		do { if (sbc_debug & SBC_DB_BREAK) Debugger(); } while (0)
     86  1.36  jonathan #else
     87  1.36  jonathan # define	SBC_BREAK
     88  1.36  jonathan #endif
     89  1.36  jonathan 
     90   1.1    scottr 
     91  1.22    scottr int	sbc_debug = 0 /* | SBC_DB_INTR | SBC_DB_DMA */;
     92  1.22    scottr int	sbc_link_flags = 0 /* | SDEV_DB2 */;
     93  1.24    scottr int	sbc_options = 0 /* | SBC_PDMA */;
     94   1.1    scottr 
     95  1.31    scottr extern label_t	*nofault;
     96  1.52  christos extern void *	m68k_fault_addr;
     97  1.31    scottr 
     98  1.45       chs static	int	sbc_wait_busy(struct ncr5380_softc *);
     99  1.45       chs static	int	sbc_ready(struct ncr5380_softc *);
    100  1.45       chs static	int	sbc_wait_dreq(struct ncr5380_softc *);
    101   1.1    scottr 
    102   1.1    scottr 
    103   1.1    scottr /***
    104   1.1    scottr  * General support for Mac-specific SCSI logic.
    105   1.1    scottr  ***/
    106   1.1    scottr 
    107  1.28    scottr /* These are used in the following inline functions. */
    108  1.28    scottr int sbc_wait_busy_timo = 1000 * 5000;	/* X2 = 10 S. */
    109  1.28    scottr int sbc_ready_timo = 1000 * 5000;	/* X2 = 10 S. */
    110  1.28    scottr int sbc_wait_dreq_timo = 1000 * 5000;	/* X2 = 10 S. */
    111  1.28    scottr 
    112  1.28    scottr /* Return zero on success. */
    113  1.48     perry static inline int
    114  1.45       chs sbc_wait_busy(struct ncr5380_softc *sc)
    115  1.28    scottr {
    116  1.28    scottr 	int timo = sbc_wait_busy_timo;
    117  1.28    scottr 	for (;;) {
    118  1.28    scottr 		if (SCI_BUSY(sc)) {
    119  1.28    scottr 			timo = 0;	/* return 0 */
    120  1.28    scottr 			break;
    121  1.28    scottr 		}
    122  1.28    scottr 		if (--timo < 0)
    123  1.28    scottr 			break;	/* return -1 */
    124  1.28    scottr 		delay(2);
    125  1.28    scottr 	}
    126  1.28    scottr 	return (timo);
    127  1.28    scottr }
    128  1.28    scottr 
    129  1.48     perry static inline int
    130  1.45       chs sbc_ready(struct ncr5380_softc *sc)
    131  1.28    scottr {
    132  1.28    scottr 	int timo = sbc_ready_timo;
    133  1.28    scottr 
    134  1.28    scottr 	for (;;) {
    135  1.28    scottr 		if ((*sc->sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH))
    136  1.28    scottr 		    == (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) {
    137  1.28    scottr 			timo = 0;
    138  1.28    scottr 			break;
    139  1.28    scottr 		}
    140  1.28    scottr 		if (((*sc->sci_csr & SCI_CSR_PHASE_MATCH) == 0)
    141  1.28    scottr 		    || (SCI_BUSY(sc) == 0)) {
    142  1.28    scottr 			timo = -1;
    143  1.28    scottr 			break;
    144  1.28    scottr 		}
    145  1.28    scottr 		if (--timo < 0)
    146  1.28    scottr 			break;	/* return -1 */
    147  1.28    scottr 		delay(2);
    148  1.28    scottr 	}
    149  1.28    scottr 	return (timo);
    150  1.28    scottr }
    151  1.28    scottr 
    152  1.48     perry static inline int
    153  1.45       chs sbc_wait_dreq(struct ncr5380_softc *sc)
    154  1.28    scottr {
    155  1.28    scottr 	int timo = sbc_wait_dreq_timo;
    156  1.28    scottr 
    157  1.28    scottr 	for (;;) {
    158  1.28    scottr 		if ((*sc->sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH))
    159  1.28    scottr 		    == (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) {
    160  1.28    scottr 			timo = 0;
    161  1.28    scottr 			break;
    162  1.28    scottr 		}
    163  1.28    scottr 		if (--timo < 0)
    164  1.28    scottr 			break;	/* return -1 */
    165  1.28    scottr 		delay(2);
    166  1.28    scottr 	}
    167  1.28    scottr 	return (timo);
    168  1.28    scottr }
    169  1.28    scottr 
    170   1.1    scottr void
    171  1.45       chs sbc_irq_intr(void *p)
    172   1.1    scottr {
    173  1.23    scottr 	struct ncr5380_softc *ncr_sc = p;
    174  1.33    scottr 	struct sbc_softc *sc = (struct sbc_softc *)ncr_sc;
    175  1.23    scottr 	int claimed = 0;
    176   1.1    scottr 
    177   1.1    scottr 	/* How we ever arrive here without IRQ set is a mystery... */
    178   1.1    scottr 	if (*ncr_sc->sci_csr & SCI_CSR_INT) {
    179   1.3    scottr #ifdef SBC_DEBUG
    180   1.3    scottr 		if (sbc_debug & SBC_DB_INTR)
    181   1.3    scottr 			decode_5380_intr(ncr_sc);
    182   1.3    scottr #endif
    183  1.33    scottr 		if (!cold)
    184  1.33    scottr 			claimed = ncr5380_intr(ncr_sc);
    185   1.1    scottr 		if (!claimed) {
    186   1.1    scottr 			if (((*ncr_sc->sci_csr & ~SCI_CSR_PHASE_MATCH) == SCI_CSR_INT)
    187  1.33    scottr 			    && ((*ncr_sc->sci_bus_csr & ~SCI_BUS_RST) == 0)) {
    188   1.1    scottr 				SCI_CLR_INTR(ncr_sc);	/* RST interrupt */
    189  1.33    scottr 				if (sc->sc_clrintr)
    190  1.33    scottr 					(*sc->sc_clrintr)(ncr_sc);
    191  1.33    scottr 			}
    192   1.1    scottr #ifdef SBC_DEBUG
    193   1.1    scottr 			else {
    194  1.13  christos 				printf("%s: spurious intr\n",
    195  1.53   tsutsui 				    device_xname(ncr_sc->sc_dev));
    196   1.3    scottr 				SBC_BREAK;
    197   1.1    scottr 			}
    198   1.1    scottr #endif
    199   1.1    scottr 		}
    200   1.1    scottr 	}
    201   1.1    scottr }
    202   1.1    scottr 
    203   1.3    scottr #ifdef SBC_DEBUG
    204   1.3    scottr void
    205  1.45       chs decode_5380_intr(struct ncr5380_softc *ncr_sc)
    206   1.3    scottr {
    207  1.28    scottr 	u_int8_t csr = *ncr_sc->sci_csr;
    208  1.28    scottr 	u_int8_t bus_csr = *ncr_sc->sci_bus_csr;
    209   1.3    scottr 
    210   1.3    scottr 	if (((csr & ~(SCI_CSR_PHASE_MATCH | SCI_CSR_ATN)) == SCI_CSR_INT) &&
    211   1.3    scottr 	    ((bus_csr & ~(SCI_BUS_MSG | SCI_BUS_CD | SCI_BUS_IO | SCI_BUS_DBP)) == SCI_BUS_SEL)) {
    212   1.3    scottr 		if (csr & SCI_BUS_IO)
    213  1.53   tsutsui 			printf("%s: reselect\n", device_xname(ncr_sc->sc_dev));
    214   1.3    scottr 		else
    215  1.53   tsutsui 			printf("%s: select\n", device_xname(ncr_sc->sc_dev));
    216   1.3    scottr 	} else if (((csr & ~SCI_CSR_ACK) == (SCI_CSR_DONE | SCI_CSR_INT)) &&
    217   1.3    scottr 	    ((bus_csr & (SCI_BUS_RST | SCI_BUS_BSY | SCI_BUS_SEL)) == SCI_BUS_BSY))
    218  1.53   tsutsui 		printf("%s: DMA eop\n", device_xname(ncr_sc->sc_dev));
    219   1.3    scottr 	else if (((csr & ~SCI_CSR_PHASE_MATCH) == SCI_CSR_INT) &&
    220   1.3    scottr 	    ((bus_csr & ~SCI_BUS_RST) == 0))
    221  1.53   tsutsui 		printf("%s: bus reset\n", device_xname(ncr_sc->sc_dev));
    222   1.3    scottr 	else if (((csr & ~(SCI_CSR_DREQ | SCI_CSR_ATN | SCI_CSR_ACK)) == (SCI_CSR_PERR | SCI_CSR_INT | SCI_CSR_PHASE_MATCH)) &&
    223   1.3    scottr 	    ((bus_csr & (SCI_BUS_RST | SCI_BUS_BSY | SCI_BUS_SEL)) == SCI_BUS_BSY))
    224  1.53   tsutsui 		printf("%s: parity error\n", device_xname(ncr_sc->sc_dev));
    225   1.3    scottr 	else if (((csr & ~SCI_CSR_ATN) == SCI_CSR_INT) &&
    226   1.3    scottr 	    ((bus_csr & (SCI_BUS_RST | SCI_BUS_BSY | SCI_BUS_REQ | SCI_BUS_SEL)) == (SCI_BUS_BSY | SCI_BUS_REQ)))
    227  1.53   tsutsui 		printf("%s: phase mismatch\n", device_xname(ncr_sc->sc_dev));
    228   1.3    scottr 	else if (((csr & ~SCI_CSR_PHASE_MATCH) == (SCI_CSR_INT | SCI_CSR_DISC)) &&
    229   1.3    scottr 	    (bus_csr == 0))
    230  1.53   tsutsui 		printf("%s: disconnect\n", device_xname(ncr_sc->sc_dev));
    231   1.3    scottr 	else
    232  1.13  christos 		printf("%s: unknown intr: csr=%x, bus_csr=%x\n",
    233  1.53   tsutsui 		    device_xname(ncr_sc->sc_dev), csr, bus_csr);
    234   1.3    scottr }
    235   1.3    scottr #endif
    236   1.1    scottr 
    237   1.8    scottr 
    238   1.1    scottr /***
    239   1.1    scottr  * The following code implements polled PDMA.
    240   1.1    scottr  ***/
    241   1.1    scottr 
    242  1.23    scottr int
    243  1.45       chs sbc_pdma_in(struct ncr5380_softc *ncr_sc, int phase, int datalen, u_char *data)
    244  1.23    scottr {
    245  1.23    scottr 	struct sbc_softc *sc = (struct sbc_softc *)ncr_sc;
    246  1.24    scottr 	volatile u_int32_t *long_data = (u_int32_t *)sc->sc_drq_addr;
    247  1.24    scottr 	volatile u_int8_t *byte_data = (u_int8_t *)sc->sc_nodrq_addr;
    248  1.49       chs 	label_t faultbuf;
    249  1.23    scottr 	int resid, s;
    250  1.23    scottr 
    251  1.28    scottr 	if (datalen < ncr_sc->sc_min_dma_len ||
    252  1.58       nat 	    (sc->sc_options & SBC_PDMA) == 0 ||
    253  1.58       nat 	    (ncr_sc->sc_current != NULL &&
    254  1.58       nat 	    (ncr_sc->sc_current->sr_xs->xs_control & XS_CTL_POLL)))
    255  1.28    scottr 		return ncr5380_pio_in(ncr_sc, phase, datalen, data);
    256  1.28    scottr 
    257  1.23    scottr 	s = splbio();
    258  1.28    scottr 	if (sbc_wait_busy(ncr_sc)) {
    259  1.28    scottr 		splx(s);
    260  1.28    scottr 		return 0;
    261  1.28    scottr 	}
    262  1.28    scottr 
    263  1.23    scottr 	*ncr_sc->sci_mode |= SCI_MODE_DMA;
    264  1.23    scottr 	*ncr_sc->sci_irecv = 0;
    265   1.1    scottr 
    266  1.49       chs 	resid = datalen;
    267  1.49       chs 
    268  1.49       chs 	/*
    269  1.49       chs 	 * Setup for a possible bus error caused by SCSI controller
    270  1.49       chs 	 * switching out of DATA OUT before we're done with the
    271  1.49       chs 	 * current transfer.  (See comment before sbc_drq_intr().)
    272  1.49       chs 	 */
    273  1.49       chs 	nofault = &faultbuf;
    274  1.49       chs 	if (setjmp(nofault)) {
    275  1.49       chs 		goto interrupt;
    276  1.49       chs 	}
    277  1.49       chs 
    278  1.50     skrll #define R4	*(u_int32_t *)data = *long_data, data += 4;
    279  1.49       chs 	for (; resid >= 128; resid -= 128) {
    280  1.28    scottr 		if (sbc_ready(ncr_sc))
    281  1.23    scottr 			goto interrupt;
    282  1.23    scottr 		R4; R4; R4; R4; R4; R4; R4; R4;
    283  1.23    scottr 		R4; R4; R4; R4; R4; R4; R4; R4;
    284  1.23    scottr 		R4; R4; R4; R4; R4; R4; R4; R4;
    285  1.28    scottr 		R4; R4; R4; R4; R4; R4; R4; R4;		/* 128 */
    286  1.23    scottr 	}
    287  1.23    scottr 	while (resid) {
    288  1.28    scottr 		if (sbc_ready(ncr_sc))
    289  1.23    scottr 			goto interrupt;
    290  1.55     hauke 		*(u_int8_t *)data = *byte_data, data += 1;
    291  1.23    scottr 		resid--;
    292   1.1    scottr 	}
    293  1.23    scottr #undef R4
    294   1.1    scottr 
    295  1.23    scottr interrupt:
    296  1.49       chs 	nofault = NULL;
    297   1.1    scottr 	SCI_CLR_INTR(ncr_sc);
    298   1.1    scottr 	*ncr_sc->sci_mode &= ~SCI_MODE_DMA;
    299  1.28    scottr 	*ncr_sc->sci_icmd = 0;
    300  1.23    scottr 	splx(s);
    301  1.28    scottr 	return (datalen - resid);
    302   1.1    scottr }
    303   1.1    scottr 
    304  1.22    scottr int
    305  1.45       chs sbc_pdma_out(struct ncr5380_softc *ncr_sc, int phase, int datalen, u_char *data)
    306   1.1    scottr {
    307   1.1    scottr 	struct sbc_softc *sc = (struct sbc_softc *)ncr_sc;
    308  1.24    scottr 	volatile u_int32_t *long_data = (u_int32_t *)sc->sc_drq_addr;
    309  1.24    scottr 	volatile u_int8_t *byte_data = (u_int8_t *)sc->sc_nodrq_addr;
    310  1.31    scottr 	label_t faultbuf;
    311  1.28    scottr 	int resid, s;
    312  1.28    scottr 	u_int8_t icmd;
    313  1.23    scottr 
    314  1.31    scottr #if 1
    315  1.31    scottr 	/* Work around lame gcc initialization bug */
    316  1.31    scottr 	(void)&data;
    317  1.31    scottr #endif
    318  1.31    scottr 
    319  1.28    scottr 	if (datalen < ncr_sc->sc_min_dma_len ||
    320  1.58       nat 	    (sc->sc_options & SBC_PDMA) == 0 ||
    321  1.59       nat 	    (sc->sc_options & SBC_PDMA_NO_WRITE) ||
    322  1.58       nat 	    (ncr_sc->sc_current != NULL &&
    323  1.58       nat 	    (ncr_sc->sc_current->sr_xs->xs_control & XS_CTL_POLL)))
    324  1.24    scottr 		return ncr5380_pio_out(ncr_sc, phase, datalen, data);
    325  1.24    scottr 
    326  1.23    scottr 	s = splbio();
    327  1.28    scottr 	if (sbc_wait_busy(ncr_sc)) {
    328  1.28    scottr 		splx(s);
    329  1.28    scottr 		return 0;
    330  1.28    scottr 	}
    331  1.28    scottr 
    332  1.23    scottr 	icmd = *(ncr_sc->sci_icmd) & SCI_ICMD_RMASK;
    333  1.23    scottr 	*ncr_sc->sci_icmd = icmd | SCI_ICMD_DATA;
    334  1.23    scottr 	*ncr_sc->sci_mode |= SCI_MODE_DMA;
    335  1.23    scottr 	*ncr_sc->sci_dma_send = 0;
    336  1.23    scottr 
    337  1.31    scottr 	/*
    338  1.31    scottr 	 * Setup for a possible bus error caused by SCSI controller
    339  1.31    scottr 	 * switching out of DATA OUT before we're done with the
    340  1.31    scottr 	 * current transfer.  (See comment before sbc_drq_intr().)
    341  1.31    scottr 	 */
    342  1.31    scottr 	nofault = &faultbuf;
    343  1.31    scottr 
    344  1.31    scottr 	if (setjmp(nofault)) {
    345  1.31    scottr 		printf("buf = 0x%lx, fault = 0x%lx\n",
    346  1.31    scottr 		    (u_long)sc->sc_drq_addr, (u_long)m68k_fault_addr);
    347  1.31    scottr 		panic("Unexpected bus error in sbc_pdma_out()");
    348  1.31    scottr 	}
    349  1.31    scottr 
    350  1.50     skrll #define W1	*byte_data = *(u_int8_t *)data, data += 1
    351  1.50     skrll #define W4	*long_data = *(u_int32_t *)data, data += 4
    352  1.28    scottr 	for (resid = datalen; resid >= 64; resid -= 64) {
    353  1.28    scottr 		if (sbc_ready(ncr_sc))
    354  1.23    scottr 			goto interrupt;
    355  1.23    scottr 		W1;
    356  1.28    scottr 		if (sbc_ready(ncr_sc))
    357  1.23    scottr 			goto interrupt;
    358  1.23    scottr 		W1;
    359  1.28    scottr 		if (sbc_ready(ncr_sc))
    360  1.23    scottr 			goto interrupt;
    361  1.23    scottr 		W1;
    362  1.28    scottr 		if (sbc_ready(ncr_sc))
    363  1.23    scottr 			goto interrupt;
    364  1.23    scottr 		W1;
    365  1.28    scottr 		if (sbc_ready(ncr_sc))
    366  1.23    scottr 			goto interrupt;
    367  1.23    scottr 		W4; W4; W4; W4;
    368  1.23    scottr 		W4; W4; W4; W4;
    369  1.23    scottr 		W4; W4; W4; W4;
    370  1.23    scottr 		W4; W4; W4;
    371  1.23    scottr 	}
    372  1.28    scottr 	while (resid) {
    373  1.28    scottr 		if (sbc_ready(ncr_sc))
    374  1.23    scottr 			goto interrupt;
    375  1.23    scottr 		W1;
    376  1.28    scottr 		resid--;
    377  1.23    scottr 	}
    378  1.23    scottr #undef  W1
    379  1.23    scottr #undef  W4
    380  1.28    scottr 	if (sbc_wait_dreq(ncr_sc))
    381  1.28    scottr 		printf("%s: timeout waiting for DREQ.\n",
    382  1.53   tsutsui 		    device_xname(ncr_sc->sc_dev));
    383  1.28    scottr 
    384  1.28    scottr 	*byte_data = 0;
    385  1.28    scottr 	goto done;
    386   1.1    scottr 
    387  1.28    scottr interrupt:
    388  1.28    scottr 	if ((*ncr_sc->sci_csr & SCI_CSR_PHASE_MATCH) == 0) {
    389  1.28    scottr 		*ncr_sc->sci_icmd = icmd & ~SCI_ICMD_DATA;
    390  1.28    scottr 		--resid;
    391   1.1    scottr 	}
    392   1.1    scottr 
    393  1.28    scottr done:
    394   1.1    scottr 	SCI_CLR_INTR(ncr_sc);
    395   1.1    scottr 	*ncr_sc->sci_mode &= ~SCI_MODE_DMA;
    396  1.23    scottr 	*ncr_sc->sci_icmd = icmd;
    397  1.23    scottr 	splx(s);
    398  1.23    scottr 	return (datalen - resid);
    399   1.1    scottr }
    400   1.1    scottr 
    401   1.1    scottr 
    402   1.1    scottr /***
    403   1.1    scottr  * The following code implements interrupt-driven PDMA.
    404   1.1    scottr  ***/
    405   1.1    scottr 
    406   1.1    scottr /*
    407   1.1    scottr  * This is the meat of the PDMA transfer.
    408   1.1    scottr  * When we get here, we shove data as fast as the mac can take it.
    409   1.1    scottr  * We depend on several things:
    410   1.1    scottr  *   * All macs after the Mac Plus that have a 5380 chip should have a general
    411   1.1    scottr  *     logic IC that handshakes data for blind transfers.
    412   1.1    scottr  *   * If the SCSI controller finishes sending/receiving data before we do,
    413   1.1    scottr  *     the same general logic IC will generate a /BERR for us in short order.
    414   1.1    scottr  *   * The fault address for said /BERR minus the base address for the
    415   1.1    scottr  *     transfer will be the amount of data that was actually written.
    416   1.1    scottr  *
    417   1.1    scottr  * We use the nofault flag and the setjmp/longjmp in locore.s so we can
    418   1.1    scottr  * detect and handle the bus error for early termination of a command.
    419   1.1    scottr  * This is usually caused by a disconnecting target.
    420   1.1    scottr  */
    421   1.1    scottr void
    422  1.45       chs sbc_drq_intr(void *p)
    423   1.1    scottr {
    424  1.24    scottr 	struct sbc_softc *sc = (struct sbc_softc *)p;
    425  1.24    scottr 	struct ncr5380_softc *ncr_sc = (struct ncr5380_softc *)p;
    426  1.23    scottr 	struct sci_req *sr = ncr_sc->sc_current;
    427  1.23    scottr 	struct sbc_pdma_handle *dh = sr->sr_dma_hand;
    428  1.23    scottr 	label_t faultbuf;
    429  1.23    scottr 	volatile u_int32_t *long_drq;
    430  1.23    scottr 	u_int32_t *long_data;
    431  1.51    mhitch 	volatile u_int8_t *drq = 0;	/* XXX gcc4 -Wuninitialized */
    432  1.23    scottr 	u_int8_t *data;
    433  1.60       nat 	int block, count, dcount, resid;
    434  1.26    scottr 
    435   1.1    scottr 	/*
    436   1.1    scottr 	 * If we're not ready to xfer data, or have no more, just return.
    437   1.1    scottr 	 */
    438   1.3    scottr 	if ((*ncr_sc->sci_csr & SCI_CSR_DREQ) == 0 || dh->dh_len == 0)
    439   1.1    scottr 		return;
    440   1.1    scottr 
    441   1.1    scottr #ifdef SBC_DEBUG
    442   1.1    scottr 	if (sbc_debug & SBC_DB_INTR)
    443  1.13  christos 		printf("%s: drq intr, dh_len=0x%x, dh_flags=0x%x\n",
    444  1.53   tsutsui 		    device_xname(ncr_sc->sc_dev), dh->dh_len, dh->dh_flags);
    445   1.1    scottr #endif
    446   1.1    scottr 
    447   1.1    scottr 	/*
    448   1.1    scottr 	 * Setup for a possible bus error caused by SCSI controller
    449   1.1    scottr 	 * switching out of DATA-IN/OUT before we're done with the
    450   1.1    scottr 	 * current transfer.
    451   1.1    scottr 	 */
    452  1.31    scottr 	nofault = &faultbuf;
    453   1.1    scottr 
    454  1.33    scottr 	if (setjmp(nofault)) {
    455  1.31    scottr 		nofault = (label_t *)0;
    456   1.8    scottr 		if ((dh->dh_flags & SBC_DH_DONE) == 0) {
    457  1.27    scottr 			count = ((  (u_long)m68k_fault_addr
    458  1.24    scottr 				  - (u_long)sc->sc_drq_addr));
    459   1.8    scottr 
    460   1.8    scottr 			if ((count < 0) || (count > dh->dh_len)) {
    461  1.13  christos 				printf("%s: complete=0x%x (pending 0x%x)\n",
    462  1.53   tsutsui 				    device_xname(ncr_sc->sc_dev), count,
    463  1.53   tsutsui 				    dh->dh_len);
    464   1.8    scottr 				panic("something is wrong");
    465   1.8    scottr 			}
    466   1.1    scottr 
    467   1.8    scottr 			dh->dh_addr += count;
    468   1.8    scottr 			dh->dh_len -= count;
    469  1.18    scottr 		} else
    470  1.18    scottr 			count = 0;
    471   1.8    scottr 
    472   1.1    scottr #ifdef SBC_DEBUG
    473   1.1    scottr 		if (sbc_debug & SBC_DB_INTR)
    474  1.13  christos 			printf("%s: drq /berr, complete=0x%x (pending 0x%x)\n",
    475  1.53   tsutsui 			   device_xname(ncr_sc->sc_dev), count, dh->dh_len);
    476   1.1    scottr #endif
    477  1.27    scottr 		m68k_fault_addr = 0;
    478   1.3    scottr 
    479   1.1    scottr 		return;
    480   1.1    scottr 	}
    481   1.1    scottr 
    482   1.1    scottr 	if (dh->dh_flags & SBC_DH_OUT) { /* Data Out */
    483  1.26    scottr 		dcount = 0;
    484  1.26    scottr 
    485   1.1    scottr 		/*
    486   1.1    scottr 		 * Get the source address aligned.
    487   1.1    scottr 		 */
    488   1.6    scottr 		resid =
    489  1.57  riastrad 		    count = uimin(dh->dh_len, 4 - (((int)dh->dh_addr) & 0x3));
    490   1.1    scottr 		if (count && count < 4) {
    491  1.24    scottr 			drq = (volatile u_int8_t *)sc->sc_drq_addr;
    492  1.24    scottr 			data = (u_int8_t *)dh->dh_addr;
    493   1.8    scottr 
    494   1.1    scottr #define W1		*drq++ = *data++
    495   1.1    scottr 			while (count) {
    496   1.1    scottr 				W1; count--;
    497   1.1    scottr 			}
    498   1.1    scottr #undef W1
    499   1.1    scottr 			dh->dh_addr += resid;
    500   1.1    scottr 			dh->dh_len -= resid;
    501   1.1    scottr 		}
    502   1.1    scottr 
    503   1.1    scottr 		/*
    504   1.8    scottr 		 * Start the transfer.
    505   1.1    scottr 		 */
    506   1.1    scottr 		while (dh->dh_len) {
    507  1.60       nat 			if ((*ncr_sc->sci_csr & SCI_CSR_DREQ) == 0)
    508  1.60       nat 				goto no_more;
    509  1.60       nat 
    510  1.60       nat 			block = 512;
    511  1.60       nat 			if (resid && resid != 4)
    512  1.60       nat 				block -= 4;
    513  1.60       nat 			resid = 0;
    514  1.60       nat 
    515  1.60       nat 			dcount = count = uimin(dh->dh_len, block);
    516  1.24    scottr 			long_drq = (volatile u_int32_t *)sc->sc_drq_addr;
    517  1.24    scottr 			long_data = (u_int32_t *)dh->dh_addr;
    518   1.1    scottr 
    519   1.1    scottr #define W4		*long_drq++ = *long_data++
    520   1.1    scottr 			while (count >= 64) {
    521   1.1    scottr 				W4; W4; W4; W4; W4; W4; W4; W4;
    522   1.1    scottr 				W4; W4; W4; W4; W4; W4; W4; W4; /*  64 */
    523   1.1    scottr 				count -= 64;
    524   1.1    scottr 			}
    525   1.1    scottr 			while (count >= 4) {
    526   1.1    scottr 				W4; count -= 4;
    527   1.1    scottr 			}
    528   1.1    scottr #undef W4
    529  1.24    scottr 			data = (u_int8_t *)long_data;
    530  1.46       jmc 			drq = (volatile u_int8_t *)long_drq;
    531   1.8    scottr 
    532   1.7    scottr #define W1		*drq++ = *data++
    533   1.7    scottr 			while (count) {
    534   1.7    scottr 				W1; count--;
    535   1.7    scottr 			}
    536   1.7    scottr #undef W1
    537   1.7    scottr 			dh->dh_len -= dcount;
    538   1.7    scottr 			dh->dh_addr += dcount;
    539   1.7    scottr 		}
    540   1.8    scottr 		dh->dh_flags |= SBC_DH_DONE;
    541   1.7    scottr 
    542   1.7    scottr 		/*
    543   1.8    scottr 		 * XXX -- Read a byte from the SBC to trigger a /BERR.
    544   1.8    scottr 		 * This seems to be necessary for us to notice that
    545   1.8    scottr 		 * the target has disconnected.  Ick.  06 jun 1996 (sr)
    546   1.7    scottr 		 */
    547  1.56    martin 		(void)*drq;
    548   1.1    scottr 	} else {	/* Data In */
    549   1.1    scottr 		/*
    550   1.1    scottr 		 * Get the dest address aligned.
    551   1.1    scottr 		 */
    552   1.6    scottr 		resid =
    553  1.57  riastrad 		    count = uimin(dh->dh_len, 4 - (((int)dh->dh_addr) & 0x3));
    554   1.1    scottr 		if (count && count < 4) {
    555  1.24    scottr 			data = (u_int8_t *)dh->dh_addr;
    556  1.24    scottr 			drq = (volatile u_int8_t *)sc->sc_drq_addr;
    557   1.1    scottr 			while (count) {
    558  1.55     hauke 				*data++ = *drq++;
    559  1.55     hauke 				count--;
    560   1.1    scottr 			}
    561   1.1    scottr 			dh->dh_addr += resid;
    562   1.1    scottr 			dh->dh_len -= resid;
    563   1.1    scottr 		}
    564   1.1    scottr 
    565   1.1    scottr 		/*
    566   1.8    scottr 		 * Start the transfer.
    567   1.1    scottr 		 */
    568   1.1    scottr 		while (dh->dh_len) {
    569  1.60       nat 			if ((*ncr_sc->sci_csr & SCI_CSR_DREQ) == 0)
    570  1.60       nat 				goto no_more;
    571  1.60       nat 
    572  1.60       nat 			block = 512;
    573  1.60       nat 			if (resid && resid != 4)
    574  1.60       nat 				block -= 4;
    575  1.60       nat 			resid = 0;
    576  1.60       nat 
    577  1.60       nat 			dcount = count = uimin(dh->dh_len, block);
    578  1.24    scottr 			long_data = (u_int32_t *)dh->dh_addr;
    579  1.24    scottr 			long_drq = (volatile u_int32_t *)sc->sc_drq_addr;
    580   1.1    scottr 
    581   1.1    scottr #define R4		*long_data++ = *long_drq++
    582   1.8    scottr 			while (count >= 64) {
    583   1.1    scottr 				R4; R4; R4; R4; R4; R4; R4; R4;
    584   1.1    scottr 				R4; R4; R4; R4; R4; R4; R4; R4;	/* 64 */
    585   1.8    scottr 				count -= 64;
    586   1.1    scottr 			}
    587   1.1    scottr 			while (count >= 4) {
    588   1.1    scottr 				R4; count -= 4;
    589   1.1    scottr 			}
    590   1.1    scottr #undef R4
    591  1.24    scottr 			data = (u_int8_t *)long_data;
    592  1.24    scottr 			drq = (volatile u_int8_t *)long_drq;
    593   1.1    scottr 			while (count) {
    594  1.55     hauke 				*data++ = *drq++;
    595  1.55     hauke 				count--;
    596   1.1    scottr 			}
    597   1.1    scottr 			dh->dh_len -= dcount;
    598   1.1    scottr 			dh->dh_addr += dcount;
    599   1.1    scottr 		}
    600   1.8    scottr 		dh->dh_flags |= SBC_DH_DONE;
    601   1.1    scottr 	}
    602   1.1    scottr 
    603  1.60       nat no_more:
    604   1.1    scottr 	/*
    605   1.1    scottr 	 * OK.  No bus error occurred above.  Clear the nofault flag
    606   1.1    scottr 	 * so we no longer short-circuit bus errors.
    607   1.1    scottr 	 */
    608  1.31    scottr 	nofault = (label_t *)0;
    609   1.7    scottr 
    610   1.7    scottr #ifdef SBC_DEBUG
    611   1.7    scottr 	if (sbc_debug & (SBC_DB_REG | SBC_DB_INTR))
    612  1.13  christos 		printf("%s: drq intr complete: csr=0x%x, bus_csr=0x%x\n",
    613  1.53   tsutsui 		    device_xname(ncr_sc->sc_dev), *ncr_sc->sci_csr,
    614   1.7    scottr 		    *ncr_sc->sci_bus_csr);
    615   1.7    scottr #endif
    616   1.1    scottr }
    617   1.1    scottr 
    618   1.1    scottr void
    619  1.45       chs sbc_dma_alloc(struct ncr5380_softc *ncr_sc)
    620   1.1    scottr {
    621  1.24    scottr 	struct sbc_softc *sc = (struct sbc_softc *)ncr_sc;
    622   1.1    scottr 	struct sci_req *sr = ncr_sc->sc_current;
    623  1.30    bouyer 	struct scsipi_xfer *xs = sr->sr_xs;
    624   1.1    scottr 	struct sbc_pdma_handle *dh;
    625   1.1    scottr 	int		i, xlen;
    626   1.1    scottr 
    627   1.6    scottr #ifdef DIAGNOSTIC
    628   1.1    scottr 	if (sr->sr_dma_hand != NULL)
    629   1.1    scottr 		panic("sbc_dma_alloc: already have PDMA handle");
    630   1.1    scottr #endif
    631   1.1    scottr 
    632   1.1    scottr 	/* Polled transfers shouldn't allocate a PDMA handle. */
    633   1.1    scottr 	if (sr->sr_flags & SR_IMMED)
    634   1.1    scottr 		return;
    635   1.1    scottr 
    636   1.1    scottr 	xlen = ncr_sc->sc_datalen;
    637   1.1    scottr 
    638   1.1    scottr 	/* Make sure our caller checked sc_min_dma_len. */
    639   1.1    scottr 	if (xlen < MIN_DMA_LEN)
    640  1.42    provos 		panic("sbc_dma_alloc: len=0x%x", xlen);
    641   1.1    scottr 
    642   1.1    scottr 	/*
    643   1.1    scottr 	 * Find free PDMA handle.  Guaranteed to find one since we
    644   1.1    scottr 	 * have as many PDMA handles as the driver has processes.
    645   1.1    scottr 	 * (instances?)
    646   1.1    scottr 	 */
    647   1.1    scottr 	 for (i = 0; i < SCI_OPENINGS; i++) {
    648   1.1    scottr 		if ((sc->sc_pdma[i].dh_flags & SBC_DH_BUSY) == 0)
    649   1.1    scottr 			goto found;
    650   1.1    scottr 	}
    651   1.1    scottr 	panic("sbc: no free PDMA handles");
    652   1.1    scottr found:
    653   1.1    scottr 	dh = &sc->sc_pdma[i];
    654   1.1    scottr 	dh->dh_flags = SBC_DH_BUSY;
    655   1.1    scottr 	dh->dh_addr = ncr_sc->sc_dataptr;
    656   1.1    scottr 	dh->dh_len = xlen;
    657   1.1    scottr 
    658   1.1    scottr 	/* Copy the 'write' flag for convenience. */
    659  1.40    scottr 	if (xs->xs_control & XS_CTL_DATA_OUT)
    660   1.1    scottr 		dh->dh_flags |= SBC_DH_OUT;
    661   1.1    scottr 
    662   1.1    scottr 	sr->sr_dma_hand = dh;
    663   1.1    scottr }
    664   1.1    scottr 
    665   1.1    scottr void
    666  1.45       chs sbc_dma_free(struct ncr5380_softc *ncr_sc)
    667   1.1    scottr {
    668   1.1    scottr 	struct sci_req *sr = ncr_sc->sc_current;
    669   1.1    scottr 	struct sbc_pdma_handle *dh = sr->sr_dma_hand;
    670   1.1    scottr 
    671   1.6    scottr #ifdef DIAGNOSTIC
    672   1.1    scottr 	if (sr->sr_dma_hand == NULL)
    673   1.1    scottr 		panic("sbc_dma_free: no DMA handle");
    674   1.1    scottr #endif
    675   1.1    scottr 
    676   1.1    scottr 	if (ncr_sc->sc_state & NCR_DOINGDMA)
    677   1.1    scottr 		panic("sbc_dma_free: free while in progress");
    678   1.1    scottr 
    679   1.1    scottr 	if (dh->dh_flags & SBC_DH_BUSY) {
    680   1.1    scottr 		dh->dh_flags = 0;
    681   1.1    scottr 		dh->dh_addr = NULL;
    682   1.1    scottr 		dh->dh_len = 0;
    683   1.1    scottr 	}
    684   1.1    scottr 	sr->sr_dma_hand = NULL;
    685   1.1    scottr }
    686   1.1    scottr 
    687   1.1    scottr void
    688  1.45       chs sbc_dma_poll(struct ncr5380_softc *ncr_sc)
    689   1.1    scottr {
    690   1.1    scottr 	struct sci_req *sr = ncr_sc->sc_current;
    691   1.1    scottr 
    692   1.3    scottr 	/*
    693   1.3    scottr 	 * We shouldn't arrive here; if SR_IMMED is set, then
    694   1.3    scottr 	 * dma_alloc() should have refused to allocate a handle
    695   1.3    scottr 	 * for the transfer.  This forces the polled PDMA code
    696   1.3    scottr 	 * to handle the request...
    697   1.3    scottr 	 */
    698   1.6    scottr #ifdef SBC_DEBUG
    699   1.1    scottr 	if (sbc_debug & SBC_DB_DMA)
    700  1.53   tsutsui 		printf("%s: lost DRQ interrupt?\n",
    701  1.53   tsutsui 		    device_xname(ncr_sc->sc_dev));
    702   1.1    scottr #endif
    703   1.3    scottr 	sr->sr_flags |= SR_OVERDUE;
    704   1.1    scottr }
    705   1.1    scottr 
    706   1.1    scottr void
    707  1.45       chs sbc_dma_setup(struct ncr5380_softc *ncr_sc)
    708   1.1    scottr {
    709   1.1    scottr 	/* Not needed; we don't have real DMA */
    710   1.1    scottr }
    711   1.1    scottr 
    712   1.1    scottr void
    713  1.45       chs sbc_dma_start(struct ncr5380_softc *ncr_sc)
    714   1.1    scottr {
    715  1.24    scottr 	struct sbc_softc *sc = (struct sbc_softc *)ncr_sc;
    716   1.1    scottr 	struct sci_req *sr = ncr_sc->sc_current;
    717   1.1    scottr 	struct sbc_pdma_handle *dh = sr->sr_dma_hand;
    718   1.1    scottr 
    719   1.1    scottr 	/*
    720   1.7    scottr 	 * Match bus phase, clear pending interrupts, set DMA mode, and
    721   1.7    scottr 	 * assert data bus (for writing only), then start the transfer.
    722   1.1    scottr 	 */
    723   1.1    scottr 	if (dh->dh_flags & SBC_DH_OUT) {
    724   1.1    scottr 		*ncr_sc->sci_tcmd = PHASE_DATA_OUT;
    725   1.1    scottr 		SCI_CLR_INTR(ncr_sc);
    726  1.22    scottr 		if (sc->sc_clrintr)
    727  1.22    scottr 			(*sc->sc_clrintr)(ncr_sc);
    728   1.1    scottr 		*ncr_sc->sci_mode |= SCI_MODE_DMA;
    729   1.1    scottr 		*ncr_sc->sci_icmd = SCI_ICMD_DATA;
    730   1.1    scottr 		*ncr_sc->sci_dma_send = 0;
    731   1.1    scottr 	} else {
    732   1.1    scottr 		*ncr_sc->sci_tcmd = PHASE_DATA_IN;
    733   1.1    scottr 		SCI_CLR_INTR(ncr_sc);
    734  1.22    scottr 		if (sc->sc_clrintr)
    735  1.22    scottr 			(*sc->sc_clrintr)(ncr_sc);
    736   1.1    scottr 		*ncr_sc->sci_mode |= SCI_MODE_DMA;
    737   1.1    scottr 		*ncr_sc->sci_icmd = 0;
    738   1.1    scottr 		*ncr_sc->sci_irecv = 0;
    739   1.1    scottr 	}
    740   1.3    scottr 	ncr_sc->sc_state |= NCR_DOINGDMA;
    741   1.1    scottr 
    742   1.6    scottr #ifdef SBC_DEBUG
    743   1.1    scottr 	if (sbc_debug & SBC_DB_DMA)
    744  1.13  christos 		printf("%s: PDMA started, va=%p, len=0x%x\n",
    745  1.53   tsutsui 		    device_xname(ncr_sc->sc_dev), dh->dh_addr, dh->dh_len);
    746   1.1    scottr #endif
    747   1.1    scottr }
    748   1.1    scottr 
    749   1.1    scottr void
    750  1.45       chs sbc_dma_eop(struct ncr5380_softc *ncr_sc)
    751   1.1    scottr {
    752   1.1    scottr 	/* Not used; the EOP pin is wired high (GMFH, pp. 389-390) */
    753   1.1    scottr }
    754   1.1    scottr 
    755   1.1    scottr void
    756  1.45       chs sbc_dma_stop(struct ncr5380_softc *ncr_sc)
    757   1.1    scottr {
    758  1.24    scottr 	struct sbc_softc *sc = (struct sbc_softc *)ncr_sc;
    759   1.1    scottr 	struct sci_req *sr = ncr_sc->sc_current;
    760   1.1    scottr 	struct sbc_pdma_handle *dh = sr->sr_dma_hand;
    761  1.23    scottr 	int ntrans;
    762   1.1    scottr 
    763   1.1    scottr 	if ((ncr_sc->sc_state & NCR_DOINGDMA) == 0) {
    764   1.1    scottr #ifdef SBC_DEBUG
    765   1.1    scottr 		if (sbc_debug & SBC_DB_DMA)
    766  1.13  christos 			printf("%s: dma_stop: DMA not running\n",
    767  1.53   tsutsui 			    device_xname(ncr_sc->sc_dev));
    768   1.1    scottr #endif
    769   1.1    scottr 		return;
    770   1.1    scottr 	}
    771   1.1    scottr 	ncr_sc->sc_state &= ~NCR_DOINGDMA;
    772   1.1    scottr 
    773   1.3    scottr 	if ((ncr_sc->sc_state & NCR_ABORTING) == 0) {
    774   1.1    scottr 		ntrans = ncr_sc->sc_datalen - dh->dh_len;
    775   1.1    scottr 
    776   1.1    scottr #ifdef SBC_DEBUG
    777   1.1    scottr 		if (sbc_debug & SBC_DB_DMA)
    778  1.13  christos 			printf("%s: dma_stop: ntrans=0x%x\n",
    779  1.53   tsutsui 			    device_xname(ncr_sc->sc_dev), ntrans);
    780   1.1    scottr #endif
    781   1.1    scottr 
    782   1.1    scottr 		if (ntrans > ncr_sc->sc_datalen)
    783  1.42    provos 			panic("sbc_dma_stop: excess transfer");
    784   1.1    scottr 
    785   1.1    scottr 		/* Adjust data pointer */
    786   1.1    scottr 		ncr_sc->sc_dataptr += ntrans;
    787   1.1    scottr 		ncr_sc->sc_datalen -= ntrans;
    788   1.1    scottr 
    789   1.1    scottr 		/* Clear any pending interrupts. */
    790   1.1    scottr 		SCI_CLR_INTR(ncr_sc);
    791  1.22    scottr 		if (sc->sc_clrintr)
    792  1.22    scottr 			(*sc->sc_clrintr)(ncr_sc);
    793   1.1    scottr 	}
    794   1.1    scottr 
    795   1.1    scottr 	/* Put SBIC back into PIO mode. */
    796   1.1    scottr 	*ncr_sc->sci_mode &= ~SCI_MODE_DMA;
    797   1.1    scottr 	*ncr_sc->sci_icmd = 0;
    798   1.1    scottr 
    799   1.1    scottr #ifdef SBC_DEBUG
    800   1.3    scottr 	if (sbc_debug & SBC_DB_REG)
    801  1.13  christos 		printf("%s: dma_stop: csr=0x%x, bus_csr=0x%x\n",
    802  1.53   tsutsui 		    device_xname(ncr_sc->sc_dev), *ncr_sc->sci_csr,
    803   1.1    scottr 		    *ncr_sc->sci_bus_csr);
    804   1.1    scottr #endif
    805   1.1    scottr }
    806