sbc.c revision 1.13
1 /* $NetBSD: sbc.c,v 1.13 1996/10/13 03:21:28 christos Exp $ */ 2 3 /* 4 * Copyright (c) 1996 Scott Reynolds 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the authors may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 4. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgements: 19 * This product includes software developed by Scott Reynolds. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * This file contains only the machine-dependent parts of the mac68k 35 * NCR 5380 SCSI driver. (Autoconfig stuff and PDMA functions.) 36 * The machine-independent parts are in ncr5380sbc.c 37 * 38 * Supported hardware includes: 39 * Macintosh II family 5380-based controller 40 * 41 * Credits, history: 42 * 43 * Scott Reynolds wrote this module, based on work by Allen Briggs 44 * (mac68k), Gordon W. Ross and David Jones (sun3), and Leo Weppelman 45 * (atari). Thanks to Allen for supplying crucial interpretation of the 46 * NetBSD/mac68k 1.1 'ncrscsi' driver. Also, Allen, Gordon, and Jason 47 * Thorpe all helped to refine this code, and were considerable sources 48 * of moral support. 49 */ 50 51 #include <sys/types.h> 52 #include <sys/param.h> 53 #include <sys/systm.h> 54 #include <sys/kernel.h> 55 #include <sys/errno.h> 56 #include <sys/device.h> 57 #include <sys/buf.h> 58 #include <sys/proc.h> 59 #include <sys/user.h> 60 61 #include <scsi/scsi_all.h> 62 #include <scsi/scsi_debug.h> 63 #include <scsi/scsiconf.h> 64 65 #include <dev/ic/ncr5380reg.h> 66 #include <dev/ic/ncr5380var.h> 67 68 #include <machine/cpu.h> 69 #include <machine/viareg.h> 70 71 #include "sbcreg.h" 72 73 /* 74 * Transfers smaller than this are done using PIO 75 * (on assumption they're not worth PDMA overhead) 76 */ 77 #define MIN_DMA_LEN 128 78 79 /* 80 * Transfers larger than 8192 bytes need to be split up 81 * due to the size of the PDMA space. 82 */ 83 #define MAX_DMA_LEN 0x2000 84 85 /* 86 * From Guide to the Macintosh Family Hardware, pp. 137-143 87 * These are offsets from SCSIBase (see pmap_bootstrap.c) 88 */ 89 #define SBC_REG_OFS 0x10000 90 #define SBC_HSK_OFS 0x06000 91 #define SBC_DMA_OFS 0x12000 92 93 #define SBC_DMA_OFS_PB500 0x06000 94 95 #define SBC_REG_OFS_IIFX 0x08000 /* Just guessing... */ 96 #define SBC_HSK_OFS_IIFX 0x0e000 97 #define SBC_DMA_OFS_IIFX 0x0c000 98 99 #ifdef SBC_DEBUG 100 # define SBC_DB_INTR 0x01 101 # define SBC_DB_DMA 0x02 102 # define SBC_DB_REG 0x04 103 # define SBC_DB_BREAK 0x08 104 105 int sbc_debug = 0 /* | SBC_DB_INTR | SBC_DB_DMA */; 106 int sbc_link_flags = 0 /* | SDEV_DB2 */; 107 108 # ifndef DDB 109 # define Debugger() printf("Debug: sbc.c:%d\n", __LINE__) 110 # endif 111 # define SBC_BREAK \ 112 do { if (sbc_debug & SBC_DB_BREAK) Debugger(); } while (0) 113 #else 114 # define SBC_BREAK 115 #endif 116 117 /* 118 * This structure is used to keep track of PDMA requests. 119 */ 120 struct sbc_pdma_handle { 121 int dh_flags; /* flags */ 122 #define SBC_DH_BUSY 0x01 /* This handle is in use */ 123 #define SBC_DH_OUT 0x02 /* PDMA data out (write) */ 124 #define SBC_DH_DONE 0x04 /* PDMA transfer is complete */ 125 u_char *dh_addr; /* data buffer */ 126 int dh_len; /* length of data buffer */ 127 }; 128 129 /* 130 * The first structure member has to be the ncr5380_softc 131 * so we can just cast to go back and forth between them. 132 */ 133 struct sbc_softc { 134 struct ncr5380_softc ncr_sc; 135 volatile struct sbc_regs *sc_regs; 136 volatile vm_offset_t sc_drq_addr; 137 volatile vm_offset_t sc_nodrq_addr; 138 volatile u_int8_t *sc_ienable; 139 volatile u_int8_t *sc_iflag; 140 int sc_options; /* options for this instance. */ 141 struct sbc_pdma_handle sc_pdma[SCI_OPENINGS]; 142 }; 143 144 /* 145 * Options. By default, SCSI interrupts and reselect are disabled. 146 * You may enable either of these features with the `flags' directive 147 * in your kernel's configuration file. 148 * 149 * Alternatively, you can patch your kernel with DDB or some other 150 * mechanism. The sc_options member of the softc is OR'd with 151 * the value in sbc_options. 152 * 153 * The options code is based on the sparc 'si' driver's version of 154 * the same. 155 */ 156 #define SBC_PDMA 0x01 /* Use PDMA for polled transfers */ 157 #define SBC_INTR 0x02 /* Allow SCSI IRQ/DRQ interrupts */ 158 #define SBC_RESELECT 0x04 /* Allow disconnect/reselect */ 159 #define SBC_OPTIONS_MASK (SBC_RESELECT|SBC_INTR|SBC_PDMA) 160 #define SBC_OPTIONS_BITS "\10\3RESELECT\2INTR\1PDMA" 161 int sbc_options = SBC_PDMA; 162 163 static int sbc_match __P((struct device *, void *, void *)); 164 static void sbc_attach __P((struct device *, struct device *, void *)); 165 static void sbc_minphys __P((struct buf *bp)); 166 167 static int sbc_wait_busy __P((struct ncr5380_softc *)); 168 static int sbc_ready __P((struct ncr5380_softc *)); 169 static int sbc_wait_dreq __P((struct ncr5380_softc *)); 170 static int sbc_pdma_in __P((struct ncr5380_softc *, int, int, u_char *)); 171 static int sbc_pdma_out __P((struct ncr5380_softc *, int, int, u_char *)); 172 #ifdef SBC_DEBUG 173 static void decode_5380_intr __P((struct ncr5380_softc *)); 174 #endif 175 176 void sbc_intr_enable __P((struct ncr5380_softc *)); 177 void sbc_intr_disable __P((struct ncr5380_softc *)); 178 void sbc_irq_intr __P((void *)); 179 void sbc_drq_intr __P((void *)); 180 void sbc_dma_alloc __P((struct ncr5380_softc *)); 181 void sbc_dma_free __P((struct ncr5380_softc *)); 182 void sbc_dma_poll __P((struct ncr5380_softc *)); 183 void sbc_dma_setup __P((struct ncr5380_softc *)); 184 void sbc_dma_start __P((struct ncr5380_softc *)); 185 void sbc_dma_eop __P((struct ncr5380_softc *)); 186 void sbc_dma_stop __P((struct ncr5380_softc *)); 187 188 static struct scsi_adapter sbc_ops = { 189 ncr5380_scsi_cmd, /* scsi_cmd() */ 190 sbc_minphys, /* scsi_minphys() */ 191 NULL, /* open_target_lu() */ 192 NULL, /* close_target_lu() */ 193 }; 194 195 /* This is copied from julian's bt driver */ 196 /* "so we have a default dev struct for our link struct." */ 197 static struct scsi_device sbc_dev = { 198 NULL, /* Use default error handler. */ 199 NULL, /* Use default start handler. */ 200 NULL, /* Use default async handler. */ 201 NULL, /* Use default "done" routine. */ 202 }; 203 204 struct cfattach sbc_ca = { 205 sizeof(struct sbc_softc), sbc_match, sbc_attach 206 }; 207 208 struct cfdriver sbc_cd = { 209 NULL, "sbc", DV_DULL 210 }; 211 212 213 static int 214 sbc_match(parent, match, args) 215 struct device *parent; 216 void *match, *args; 217 { 218 if (!mac68k_machine.scsi80) 219 return 0; 220 return 1; 221 } 222 223 static void 224 sbc_attach(parent, self, args) 225 struct device *parent, *self; 226 void *args; 227 { 228 struct sbc_softc *sc = (struct sbc_softc *) self; 229 struct ncr5380_softc *ncr_sc = (struct ncr5380_softc *) sc; 230 extern vm_offset_t SCSIBase; 231 232 /* Pull in the options flags. */ 233 sc->sc_options = ((ncr_sc->sc_dev.dv_cfdata->cf_flags | sbc_options) 234 & SBC_OPTIONS_MASK); 235 236 /* 237 * Set up offsets to 5380 registers and GLUE I/O space, and turn 238 * off options we know we can't support on certain models. 239 */ 240 switch (current_mac_model->machineid) { 241 case MACH_MACIIFX: /* Note: the IIfx isn't (yet) supported. */ 242 sc->sc_regs = (struct sbc_regs *)(SCSIBase + SBC_REG_OFS_IIFX); 243 sc->sc_drq_addr = (vm_offset_t)(SCSIBase + SBC_HSK_OFS_IIFX); 244 sc->sc_nodrq_addr = (vm_offset_t)(SCSIBase + SBC_DMA_OFS_IIFX); 245 sc->sc_options &= ~(SBC_INTR | SBC_RESELECT); 246 break; 247 case MACH_MACPB500: 248 sc->sc_regs = (struct sbc_regs *)(SCSIBase + SBC_REG_OFS); 249 sc->sc_drq_addr = (vm_offset_t)(SCSIBase + SBC_HSK_OFS); /*??*/ 250 sc->sc_nodrq_addr = (vm_offset_t)(SCSIBase + SBC_DMA_OFS_PB500); 251 sc->sc_options &= ~(SBC_INTR | SBC_RESELECT); 252 break; 253 default: 254 sc->sc_regs = (struct sbc_regs *)(SCSIBase + SBC_REG_OFS); 255 sc->sc_drq_addr = (vm_offset_t)(SCSIBase + SBC_HSK_OFS); 256 sc->sc_nodrq_addr = (vm_offset_t)(SCSIBase + SBC_DMA_OFS); 257 break; 258 } 259 260 /* 261 * Fill in the prototype scsi_link. 262 */ 263 ncr_sc->sc_link.channel = SCSI_CHANNEL_ONLY_ONE; 264 ncr_sc->sc_link.adapter_softc = sc; 265 ncr_sc->sc_link.adapter_target = 7; 266 ncr_sc->sc_link.adapter = &sbc_ops; 267 ncr_sc->sc_link.device = &sbc_dev; 268 269 /* 270 * Initialize fields used by the MI code 271 */ 272 ncr_sc->sci_r0 = &sc->sc_regs->sci_pr0.sci_reg; 273 ncr_sc->sci_r1 = &sc->sc_regs->sci_pr1.sci_reg; 274 ncr_sc->sci_r2 = &sc->sc_regs->sci_pr2.sci_reg; 275 ncr_sc->sci_r3 = &sc->sc_regs->sci_pr3.sci_reg; 276 ncr_sc->sci_r4 = &sc->sc_regs->sci_pr4.sci_reg; 277 ncr_sc->sci_r5 = &sc->sc_regs->sci_pr5.sci_reg; 278 ncr_sc->sci_r6 = &sc->sc_regs->sci_pr6.sci_reg; 279 ncr_sc->sci_r7 = &sc->sc_regs->sci_pr7.sci_reg; 280 281 /* 282 * MD function pointers used by the MI code. 283 */ 284 if (sc->sc_options & SBC_PDMA) { 285 ncr_sc->sc_pio_out = sbc_pdma_out; 286 ncr_sc->sc_pio_in = sbc_pdma_in; 287 } else { 288 ncr_sc->sc_pio_out = ncr5380_pio_out; 289 ncr_sc->sc_pio_in = ncr5380_pio_in; 290 } 291 ncr_sc->sc_dma_alloc = NULL; 292 ncr_sc->sc_dma_free = NULL; 293 ncr_sc->sc_dma_poll = NULL; 294 ncr_sc->sc_intr_on = NULL; 295 ncr_sc->sc_intr_off = NULL; 296 ncr_sc->sc_dma_setup = NULL; 297 ncr_sc->sc_dma_start = NULL; 298 ncr_sc->sc_dma_eop = NULL; 299 ncr_sc->sc_dma_stop = NULL; 300 ncr_sc->sc_flags = 0; 301 ncr_sc->sc_min_dma_len = MIN_DMA_LEN; 302 303 if (sc->sc_options & SBC_INTR) { 304 if (sc->sc_options & SBC_RESELECT) 305 ncr_sc->sc_flags |= NCR5380_PERMIT_RESELECT; 306 ncr_sc->sc_dma_alloc = sbc_dma_alloc; 307 ncr_sc->sc_dma_free = sbc_dma_free; 308 ncr_sc->sc_dma_poll = sbc_dma_poll; 309 ncr_sc->sc_dma_setup = sbc_dma_setup; 310 ncr_sc->sc_dma_start = sbc_dma_start; 311 ncr_sc->sc_dma_eop = sbc_dma_eop; 312 ncr_sc->sc_dma_stop = sbc_dma_stop; 313 mac68k_register_scsi_drq(sbc_drq_intr, ncr_sc); 314 mac68k_register_scsi_irq(sbc_irq_intr, ncr_sc); 315 } else 316 ncr_sc->sc_flags |= NCR5380_FORCE_POLLING; 317 318 /* 319 * Initialize fields used only here in the MD code. 320 */ 321 if (VIA2 == VIA2OFF) { 322 sc->sc_ienable = Via1Base + VIA2 * 0x2000 + vIER; 323 sc->sc_iflag = Via1Base + VIA2 * 0x2000 + vIFR; 324 } else { 325 sc->sc_ienable = Via1Base + VIA2 * 0x2000 + rIER; 326 sc->sc_iflag = Via1Base + VIA2 * 0x2000 + rIFR; 327 } 328 329 if (sc->sc_options) 330 printf(": options=%b", sc->sc_options, SBC_OPTIONS_BITS); 331 printf("\n"); 332 333 /* Now enable SCSI interrupts through VIA2, if appropriate */ 334 if (sc->sc_options & SBC_INTR) 335 sbc_intr_enable(ncr_sc); 336 337 #ifdef SBC_DEBUG 338 if (sbc_debug) 339 printf("%s: softc=%p regs=%p\n", ncr_sc->sc_dev.dv_xname, 340 sc, sc->sc_regs); 341 ncr_sc->sc_link.flags |= sbc_link_flags; 342 #endif 343 344 /* 345 * Initialize the SCSI controller itself. 346 */ 347 ncr5380_init(ncr_sc); 348 ncr5380_reset_scsibus(ncr_sc); 349 config_found(self, &(ncr_sc->sc_link), scsiprint); 350 } 351 352 static void 353 sbc_minphys(struct buf *bp) 354 { 355 if (bp->b_bcount > MAX_DMA_LEN) 356 bp->b_bcount = MAX_DMA_LEN; 357 return (minphys(bp)); 358 } 359 360 361 /*** 362 * General support for Mac-specific SCSI logic. 363 ***/ 364 365 /* These are used in the following inline functions. */ 366 int sbc_wait_busy_timo = 1000 * 5000; /* X2 = 10 S. */ 367 int sbc_ready_timo = 1000 * 5000; /* X2 = 10 S. */ 368 int sbc_wait_dreq_timo = 1000 * 5000; /* X2 = 10 S. */ 369 370 /* Return zero on success. */ 371 static __inline__ int 372 sbc_wait_busy(sc) 373 struct ncr5380_softc *sc; 374 { 375 register int timo = sbc_wait_busy_timo; 376 for (;;) { 377 if (SCI_BUSY(sc)) { 378 timo = 0; /* return 0 */ 379 break; 380 } 381 if (--timo < 0) 382 break; /* return -1 */ 383 delay(2); 384 } 385 return (timo); 386 } 387 388 static __inline__ int 389 sbc_ready(sc) 390 struct ncr5380_softc *sc; 391 { 392 register int timo = sbc_ready_timo; 393 394 for (;;) { 395 if ((*sc->sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) 396 == (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 397 timo = 0; 398 break; 399 } 400 if (((*sc->sci_csr & SCI_CSR_PHASE_MATCH) == 0) 401 || (SCI_BUSY(sc) == 0)) { 402 timo = -1; 403 break; 404 } 405 if (--timo < 0) 406 break; /* return -1 */ 407 delay(2); 408 } 409 return (timo); 410 } 411 412 static __inline__ int 413 sbc_wait_dreq(sc) 414 struct ncr5380_softc *sc; 415 { 416 register int timo = sbc_wait_dreq_timo; 417 418 for (;;) { 419 if ((*sc->sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) 420 == (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 421 timo = 0; 422 break; 423 } 424 if (--timo < 0) 425 break; /* return -1 */ 426 delay(2); 427 } 428 return (timo); 429 } 430 431 432 /*** 433 * Macintosh SCSI interrupt support routines. 434 ***/ 435 436 void 437 sbc_intr_enable(ncr_sc) 438 struct ncr5380_softc *ncr_sc; 439 { 440 register struct sbc_softc *sc = (struct sbc_softc *) ncr_sc; 441 int s; 442 443 s = splhigh(); 444 *sc->sc_ienable = 0x80 | (V2IF_SCSIIRQ | V2IF_SCSIDRQ); 445 splx(s); 446 } 447 448 void 449 sbc_intr_disable(ncr_sc) 450 struct ncr5380_softc *ncr_sc; 451 { 452 register struct sbc_softc *sc = (struct sbc_softc *) ncr_sc; 453 int s; 454 455 s = splhigh(); 456 *sc->sc_ienable = (V2IF_SCSIIRQ | V2IF_SCSIDRQ); 457 splx(s); 458 } 459 460 void 461 sbc_irq_intr(p) 462 void *p; 463 { 464 register struct ncr5380_softc *ncr_sc = p; 465 register int claimed = 0; 466 467 /* How we ever arrive here without IRQ set is a mystery... */ 468 if (*ncr_sc->sci_csr & SCI_CSR_INT) { 469 #ifdef SBC_DEBUG 470 if (sbc_debug & SBC_DB_INTR) 471 decode_5380_intr(ncr_sc); 472 #endif 473 claimed = ncr5380_intr(ncr_sc); 474 if (!claimed) { 475 if (((*ncr_sc->sci_csr & ~SCI_CSR_PHASE_MATCH) == SCI_CSR_INT) 476 && ((*ncr_sc->sci_bus_csr & ~SCI_BUS_RST) == 0)) 477 SCI_CLR_INTR(ncr_sc); /* RST interrupt */ 478 #ifdef SBC_DEBUG 479 else { 480 printf("%s: spurious intr\n", 481 ncr_sc->sc_dev.dv_xname); 482 SBC_BREAK; 483 } 484 #endif 485 } 486 } 487 } 488 489 #ifdef SBC_DEBUG 490 void 491 decode_5380_intr(ncr_sc) 492 struct ncr5380_softc *ncr_sc; 493 { 494 register u_char csr = *ncr_sc->sci_csr; 495 register u_char bus_csr = *ncr_sc->sci_bus_csr; 496 497 if (((csr & ~(SCI_CSR_PHASE_MATCH | SCI_CSR_ATN)) == SCI_CSR_INT) && 498 ((bus_csr & ~(SCI_BUS_MSG | SCI_BUS_CD | SCI_BUS_IO | SCI_BUS_DBP)) == SCI_BUS_SEL)) { 499 if (csr & SCI_BUS_IO) 500 printf("%s: reselect\n", ncr_sc->sc_dev.dv_xname); 501 else 502 printf("%s: select\n", ncr_sc->sc_dev.dv_xname); 503 } else if (((csr & ~SCI_CSR_ACK) == (SCI_CSR_DONE | SCI_CSR_INT)) && 504 ((bus_csr & (SCI_BUS_RST | SCI_BUS_BSY | SCI_BUS_SEL)) == SCI_BUS_BSY)) 505 printf("%s: dma eop\n", ncr_sc->sc_dev.dv_xname); 506 else if (((csr & ~SCI_CSR_PHASE_MATCH) == SCI_CSR_INT) && 507 ((bus_csr & ~SCI_BUS_RST) == 0)) 508 printf("%s: bus reset\n", ncr_sc->sc_dev.dv_xname); 509 else if (((csr & ~(SCI_CSR_DREQ | SCI_CSR_ATN | SCI_CSR_ACK)) == (SCI_CSR_PERR | SCI_CSR_INT | SCI_CSR_PHASE_MATCH)) && 510 ((bus_csr & (SCI_BUS_RST | SCI_BUS_BSY | SCI_BUS_SEL)) == SCI_BUS_BSY)) 511 printf("%s: parity error\n", ncr_sc->sc_dev.dv_xname); 512 else if (((csr & ~SCI_CSR_ATN) == SCI_CSR_INT) && 513 ((bus_csr & (SCI_BUS_RST | SCI_BUS_BSY | SCI_BUS_REQ | SCI_BUS_SEL)) == (SCI_BUS_BSY | SCI_BUS_REQ))) 514 printf("%s: phase mismatch\n", ncr_sc->sc_dev.dv_xname); 515 else if (((csr & ~SCI_CSR_PHASE_MATCH) == (SCI_CSR_INT | SCI_CSR_DISC)) && 516 (bus_csr == 0)) 517 printf("%s: disconnect\n", ncr_sc->sc_dev.dv_xname); 518 else 519 printf("%s: unknown intr: csr=%x, bus_csr=%x\n", 520 ncr_sc->sc_dev.dv_xname, csr, bus_csr); 521 } 522 #endif 523 524 525 /*** 526 * The following code implements polled PDMA. 527 ***/ 528 529 static int 530 sbc_pdma_out(ncr_sc, phase, count, data) 531 struct ncr5380_softc *ncr_sc; 532 int phase; 533 int count; 534 u_char *data; 535 { 536 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 537 register volatile long *long_data = (long *) sc->sc_drq_addr; 538 register volatile u_char *byte_data = (u_char *) sc->sc_nodrq_addr; 539 register int len = count; 540 541 if (count < ncr_sc->sc_min_dma_len || (sc->sc_options & SBC_PDMA) == 0) 542 return ncr5380_pio_out(ncr_sc, phase, count, data); 543 544 if (sbc_wait_busy(ncr_sc) == 0) { 545 *ncr_sc->sci_mode |= SCI_MODE_DMA; 546 *ncr_sc->sci_icmd |= SCI_ICMD_DATA; 547 *ncr_sc->sci_dma_send = 0; 548 549 #define W1 *byte_data = *data++ 550 #define W4 *long_data = *((long*)data)++ 551 while (len >= 64) { 552 if (sbc_ready(ncr_sc)) 553 goto timeout; 554 W1; 555 if (sbc_ready(ncr_sc)) 556 goto timeout; 557 W1; 558 if (sbc_ready(ncr_sc)) 559 goto timeout; 560 W1; 561 if (sbc_ready(ncr_sc)) 562 goto timeout; 563 W1; 564 if (sbc_ready(ncr_sc)) 565 goto timeout; 566 W4; W4; W4; W4; 567 W4; W4; W4; W4; 568 W4; W4; W4; W4; 569 W4; W4; W4; 570 len -= 64; 571 } 572 while (len) { 573 if (sbc_ready(ncr_sc)) 574 goto timeout; 575 W1; 576 len--; 577 } 578 #undef W1 579 #undef W4 580 if (sbc_wait_dreq(ncr_sc)) 581 printf("%s: timeout waiting for DREQ.\n", 582 ncr_sc->sc_dev.dv_xname); 583 584 *byte_data = 0; 585 586 SCI_CLR_INTR(ncr_sc); 587 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 588 *ncr_sc->sci_icmd = 0; 589 } 590 return count - len; 591 592 timeout: 593 printf("%s: pdma_out: timeout len=%d count=%d\n", 594 ncr_sc->sc_dev.dv_xname, len, count); 595 if ((*ncr_sc->sci_csr & SCI_CSR_PHASE_MATCH) == 0) { 596 *ncr_sc->sci_icmd &= ~SCI_ICMD_DATA; 597 --len; 598 } 599 600 SCI_CLR_INTR(ncr_sc); 601 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 602 *ncr_sc->sci_icmd = 0; 603 return count - len; 604 } 605 606 static int 607 sbc_pdma_in(ncr_sc, phase, count, data) 608 struct ncr5380_softc *ncr_sc; 609 int phase; 610 int count; 611 u_char *data; 612 { 613 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 614 register volatile long *long_data = (long *) sc->sc_drq_addr; 615 register volatile u_char *byte_data = (u_char *) sc->sc_nodrq_addr; 616 register int len = count; 617 618 if (count < ncr_sc->sc_min_dma_len || (sc->sc_options & SBC_PDMA) == 0) 619 return ncr5380_pio_in(ncr_sc, phase, count, data); 620 621 if (sbc_wait_busy(ncr_sc) == 0) { 622 *ncr_sc->sci_mode |= SCI_MODE_DMA; 623 *ncr_sc->sci_icmd |= SCI_ICMD_DATA; 624 *ncr_sc->sci_irecv = 0; 625 626 #define R4 *((long *)data)++ = *long_data 627 #define R1 *data++ = *byte_data 628 while (len >= 1024) { 629 if (sbc_ready(ncr_sc)) 630 goto timeout; 631 R4; R4; R4; R4; R4; R4; R4; R4; 632 R4; R4; R4; R4; R4; R4; R4; R4; 633 R4; R4; R4; R4; R4; R4; R4; R4; 634 R4; R4; R4; R4; R4; R4; R4; R4; /* 128 */ 635 if (sbc_ready(ncr_sc)) 636 goto timeout; 637 R4; R4; R4; R4; R4; R4; R4; R4; 638 R4; R4; R4; R4; R4; R4; R4; R4; 639 R4; R4; R4; R4; R4; R4; R4; R4; 640 R4; R4; R4; R4; R4; R4; R4; R4; /* 256 */ 641 if (sbc_ready(ncr_sc)) 642 goto timeout; 643 R4; R4; R4; R4; R4; R4; R4; R4; 644 R4; R4; R4; R4; R4; R4; R4; R4; 645 R4; R4; R4; R4; R4; R4; R4; R4; 646 R4; R4; R4; R4; R4; R4; R4; R4; /* 384 */ 647 if (sbc_ready(ncr_sc)) 648 goto timeout; 649 R4; R4; R4; R4; R4; R4; R4; R4; 650 R4; R4; R4; R4; R4; R4; R4; R4; 651 R4; R4; R4; R4; R4; R4; R4; R4; 652 R4; R4; R4; R4; R4; R4; R4; R4; /* 512 */ 653 if (sbc_ready(ncr_sc)) 654 goto timeout; 655 R4; R4; R4; R4; R4; R4; R4; R4; 656 R4; R4; R4; R4; R4; R4; R4; R4; 657 R4; R4; R4; R4; R4; R4; R4; R4; 658 R4; R4; R4; R4; R4; R4; R4; R4; /* 640 */ 659 if (sbc_ready(ncr_sc)) 660 goto timeout; 661 R4; R4; R4; R4; R4; R4; R4; R4; 662 R4; R4; R4; R4; R4; R4; R4; R4; 663 R4; R4; R4; R4; R4; R4; R4; R4; 664 R4; R4; R4; R4; R4; R4; R4; R4; /* 768 */ 665 if (sbc_ready(ncr_sc)) 666 goto timeout; 667 R4; R4; R4; R4; R4; R4; R4; R4; 668 R4; R4; R4; R4; R4; R4; R4; R4; 669 R4; R4; R4; R4; R4; R4; R4; R4; 670 R4; R4; R4; R4; R4; R4; R4; R4; /* 896 */ 671 if (sbc_ready(ncr_sc)) 672 goto timeout; 673 R4; R4; R4; R4; R4; R4; R4; R4; 674 R4; R4; R4; R4; R4; R4; R4; R4; 675 R4; R4; R4; R4; R4; R4; R4; R4; 676 R4; R4; R4; R4; R4; R4; R4; R4; /* 1024 */ 677 len -= 1024; 678 } 679 while (len >= 128) { 680 if (sbc_ready(ncr_sc)) 681 goto timeout; 682 R4; R4; R4; R4; R4; R4; R4; R4; 683 R4; R4; R4; R4; R4; R4; R4; R4; 684 R4; R4; R4; R4; R4; R4; R4; R4; 685 R4; R4; R4; R4; R4; R4; R4; R4; /* 128 */ 686 len -= 128; 687 } 688 while (len) { 689 if (sbc_ready(ncr_sc)) 690 goto timeout; 691 R1; 692 len--; 693 } 694 #undef R4 695 #undef R1 696 SCI_CLR_INTR(ncr_sc); 697 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 698 *ncr_sc->sci_icmd = 0; 699 } 700 return count - len; 701 702 timeout: 703 printf("%s: pdma_in: timeout len=%d count=%d\n", 704 ncr_sc->sc_dev.dv_xname, len, count); 705 706 SCI_CLR_INTR(ncr_sc); 707 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 708 *ncr_sc->sci_icmd = 0; 709 return count - len; 710 } 711 712 713 /*** 714 * The following code implements interrupt-driven PDMA. 715 ***/ 716 717 /* 718 * This is the meat of the PDMA transfer. 719 * When we get here, we shove data as fast as the mac can take it. 720 * We depend on several things: 721 * * All macs after the Mac Plus that have a 5380 chip should have a general 722 * logic IC that handshakes data for blind transfers. 723 * * If the SCSI controller finishes sending/receiving data before we do, 724 * the same general logic IC will generate a /BERR for us in short order. 725 * * The fault address for said /BERR minus the base address for the 726 * transfer will be the amount of data that was actually written. 727 * 728 * We use the nofault flag and the setjmp/longjmp in locore.s so we can 729 * detect and handle the bus error for early termination of a command. 730 * This is usually caused by a disconnecting target. 731 */ 732 void 733 sbc_drq_intr(p) 734 void *p; 735 { 736 extern int *nofault, mac68k_buserr_addr; 737 register struct sbc_softc *sc = (struct sbc_softc *) p; 738 register struct ncr5380_softc *ncr_sc = (struct ncr5380_softc *) p; 739 register struct sci_req *sr = ncr_sc->sc_current; 740 register struct sbc_pdma_handle *dh = sr->sr_dma_hand; 741 label_t faultbuf; 742 volatile u_int32_t *long_drq; 743 u_int32_t *long_data; 744 volatile u_int8_t *drq; 745 u_int8_t *data; 746 register int count; 747 int dcount, resid; 748 u_int8_t tmp; 749 750 /* 751 * If we're not ready to xfer data, or have no more, just return. 752 */ 753 if ((*ncr_sc->sci_csr & SCI_CSR_DREQ) == 0 || dh->dh_len == 0) 754 return; 755 756 #ifdef SBC_DEBUG 757 if (sbc_debug & SBC_DB_INTR) 758 printf("%s: drq intr, dh_len=0x%x, dh_flags=0x%x\n", 759 ncr_sc->sc_dev.dv_xname, dh->dh_len, dh->dh_flags); 760 #endif 761 762 /* 763 * Setup for a possible bus error caused by SCSI controller 764 * switching out of DATA-IN/OUT before we're done with the 765 * current transfer. 766 */ 767 nofault = (int *) &faultbuf; 768 769 if (setjmp((label_t *) nofault)) { 770 nofault = (int *) 0; 771 if ((dh->dh_flags & SBC_DH_DONE) == 0) { 772 count = (( (u_long) mac68k_buserr_addr 773 - (u_long) sc->sc_drq_addr)); 774 775 if ((count < 0) || (count > dh->dh_len)) { 776 printf("%s: complete=0x%x (pending 0x%x)\n", 777 ncr_sc->sc_dev.dv_xname, count, dh->dh_len); 778 panic("something is wrong"); 779 } 780 781 dh->dh_addr += count; 782 dh->dh_len -= count; 783 } 784 785 #ifdef SBC_DEBUG 786 if (sbc_debug & SBC_DB_INTR) 787 printf("%s: drq /berr, complete=0x%x (pending 0x%x)\n", 788 ncr_sc->sc_dev.dv_xname, count, dh->dh_len); 789 #endif 790 mac68k_buserr_addr = 0; 791 792 return; 793 } 794 795 if (dh->dh_flags & SBC_DH_OUT) { /* Data Out */ 796 #if notyet /* XXX */ 797 /* 798 * Get the source address aligned. 799 */ 800 resid = 801 count = min(dh->dh_len, 4 - (((int) dh->dh_addr) & 0x3)); 802 if (count && count < 4) { 803 drq = (volatile u_int8_t *) sc->sc_drq_addr; 804 data = (u_int8_t *) dh->dh_addr; 805 806 #define W1 *drq++ = *data++ 807 while (count) { 808 W1; count--; 809 } 810 #undef W1 811 dh->dh_addr += resid; 812 dh->dh_len -= resid; 813 } 814 815 /* 816 * Start the transfer. 817 */ 818 while (dh->dh_len) { 819 dcount = count = min(dh->dh_len, MAX_DMA_LEN); 820 long_drq = (volatile u_int32_t *) sc->sc_drq_addr; 821 long_data = (u_int32_t *) dh->dh_addr; 822 823 #define W4 *long_drq++ = *long_data++ 824 while (count >= 64) { 825 W4; W4; W4; W4; W4; W4; W4; W4; 826 W4; W4; W4; W4; W4; W4; W4; W4; /* 64 */ 827 count -= 64; 828 } 829 while (count >= 4) { 830 W4; count -= 4; 831 } 832 #undef W4 833 data = (u_int8_t *) long_data; 834 drq = (u_int8_t *) long_drq; 835 #else /* notyet */ 836 /* 837 * Start the transfer. 838 */ 839 while (dh->dh_len) { 840 dcount = count = min(dh->dh_len, MAX_DMA_LEN); 841 drq = (volatile u_int8_t *) sc->sc_drq_addr; 842 data = (u_int8_t *) dh->dh_addr; 843 #endif /* notyet */ 844 845 #define W1 *drq++ = *data++ 846 while (count) { 847 W1; count--; 848 } 849 #undef W1 850 dh->dh_len -= dcount; 851 dh->dh_addr += dcount; 852 } 853 dh->dh_flags |= SBC_DH_DONE; 854 855 /* 856 * XXX -- Read a byte from the SBC to trigger a /BERR. 857 * This seems to be necessary for us to notice that 858 * the target has disconnected. Ick. 06 jun 1996 (sr) 859 */ 860 if (dcount >= MAX_DMA_LEN) { 861 #if 0 862 while ((*ncr_sc->sci_csr & SCI_CSR_ACK) == 0) 863 ; 864 #endif 865 drq = (volatile u_int8_t *) sc->sc_drq_addr; 866 } 867 tmp = *drq; 868 } else { /* Data In */ 869 /* 870 * Get the dest address aligned. 871 */ 872 resid = 873 count = min(dh->dh_len, 4 - (((int) dh->dh_addr) & 0x3)); 874 if (count && count < 4) { 875 data = (u_int8_t *) dh->dh_addr; 876 drq = (volatile u_int8_t *) sc->sc_drq_addr; 877 878 #define R1 *data++ = *drq++ 879 while (count) { 880 R1; count--; 881 } 882 #undef R1 883 dh->dh_addr += resid; 884 dh->dh_len -= resid; 885 } 886 887 /* 888 * Start the transfer. 889 */ 890 while (dh->dh_len) { 891 dcount = count = min(dh->dh_len, MAX_DMA_LEN); 892 long_data = (u_int32_t *) dh->dh_addr; 893 long_drq = (volatile u_int32_t *) sc->sc_drq_addr; 894 895 #define R4 *long_data++ = *long_drq++ 896 while (count >= 64) { 897 R4; R4; R4; R4; R4; R4; R4; R4; 898 R4; R4; R4; R4; R4; R4; R4; R4; /* 64 */ 899 count -= 64; 900 } 901 while (count >= 4) { 902 R4; count -= 4; 903 } 904 #undef R4 905 data = (u_int8_t *) long_data; 906 drq = (volatile u_int8_t *) long_drq; 907 908 #define R1 *data++ = *drq++ 909 while (count) { 910 R1; count--; 911 } 912 #undef R1 913 dh->dh_len -= dcount; 914 dh->dh_addr += dcount; 915 } 916 dh->dh_flags |= SBC_DH_DONE; 917 } 918 919 /* 920 * OK. No bus error occurred above. Clear the nofault flag 921 * so we no longer short-circuit bus errors. 922 */ 923 nofault = (int *) 0; 924 925 #ifdef SBC_DEBUG 926 if (sbc_debug & (SBC_DB_REG | SBC_DB_INTR)) 927 printf("%s: drq intr complete: csr=0x%x, bus_csr=0x%x\n", 928 ncr_sc->sc_dev.dv_xname, *ncr_sc->sci_csr, 929 *ncr_sc->sci_bus_csr); 930 #endif 931 } 932 933 void 934 sbc_dma_alloc(ncr_sc) 935 struct ncr5380_softc *ncr_sc; 936 { 937 struct sbc_softc *sc = (struct sbc_softc *) ncr_sc; 938 struct sci_req *sr = ncr_sc->sc_current; 939 struct scsi_xfer *xs = sr->sr_xs; 940 struct sbc_pdma_handle *dh; 941 int i, xlen; 942 943 #ifdef DIAGNOSTIC 944 if (sr->sr_dma_hand != NULL) 945 panic("sbc_dma_alloc: already have PDMA handle"); 946 #endif 947 948 /* Polled transfers shouldn't allocate a PDMA handle. */ 949 if (sr->sr_flags & SR_IMMED) 950 return; 951 952 xlen = ncr_sc->sc_datalen; 953 954 /* Make sure our caller checked sc_min_dma_len. */ 955 if (xlen < MIN_DMA_LEN) 956 panic("sbc_dma_alloc: len=0x%x\n", xlen); 957 958 /* 959 * Find free PDMA handle. Guaranteed to find one since we 960 * have as many PDMA handles as the driver has processes. 961 * (instances?) 962 */ 963 for (i = 0; i < SCI_OPENINGS; i++) { 964 if ((sc->sc_pdma[i].dh_flags & SBC_DH_BUSY) == 0) 965 goto found; 966 } 967 panic("sbc: no free PDMA handles"); 968 found: 969 dh = &sc->sc_pdma[i]; 970 dh->dh_flags = SBC_DH_BUSY; 971 dh->dh_addr = ncr_sc->sc_dataptr; 972 dh->dh_len = xlen; 973 974 /* Copy the 'write' flag for convenience. */ 975 if (xs->flags & SCSI_DATA_OUT) 976 dh->dh_flags |= SBC_DH_OUT; 977 978 sr->sr_dma_hand = dh; 979 } 980 981 void 982 sbc_dma_free(ncr_sc) 983 struct ncr5380_softc *ncr_sc; 984 { 985 struct sci_req *sr = ncr_sc->sc_current; 986 struct sbc_pdma_handle *dh = sr->sr_dma_hand; 987 988 #ifdef DIAGNOSTIC 989 if (sr->sr_dma_hand == NULL) 990 panic("sbc_dma_free: no DMA handle"); 991 #endif 992 993 if (ncr_sc->sc_state & NCR_DOINGDMA) 994 panic("sbc_dma_free: free while in progress"); 995 996 if (dh->dh_flags & SBC_DH_BUSY) { 997 dh->dh_flags = 0; 998 dh->dh_addr = NULL; 999 dh->dh_len = 0; 1000 } 1001 sr->sr_dma_hand = NULL; 1002 } 1003 1004 void 1005 sbc_dma_poll(ncr_sc) 1006 struct ncr5380_softc *ncr_sc; 1007 { 1008 struct sci_req *sr = ncr_sc->sc_current; 1009 1010 /* 1011 * We shouldn't arrive here; if SR_IMMED is set, then 1012 * dma_alloc() should have refused to allocate a handle 1013 * for the transfer. This forces the polled PDMA code 1014 * to handle the request... 1015 */ 1016 #ifdef SBC_DEBUG 1017 if (sbc_debug & SBC_DB_DMA) 1018 printf("%s: lost DRQ interrupt?\n", ncr_sc->sc_dev.dv_xname); 1019 #endif 1020 sr->sr_flags |= SR_OVERDUE; 1021 } 1022 1023 void 1024 sbc_dma_setup(ncr_sc) 1025 struct ncr5380_softc *ncr_sc; 1026 { 1027 /* Not needed; we don't have real DMA */ 1028 } 1029 1030 void 1031 sbc_dma_start(ncr_sc) 1032 struct ncr5380_softc *ncr_sc; 1033 { 1034 register struct sbc_softc *sc = (struct sbc_softc *) ncr_sc; 1035 struct sci_req *sr = ncr_sc->sc_current; 1036 struct sbc_pdma_handle *dh = sr->sr_dma_hand; 1037 1038 /* 1039 * Match bus phase, clear pending interrupts, set DMA mode, and 1040 * assert data bus (for writing only), then start the transfer. 1041 */ 1042 if (dh->dh_flags & SBC_DH_OUT) { 1043 *ncr_sc->sci_tcmd = PHASE_DATA_OUT; 1044 SCI_CLR_INTR(ncr_sc); 1045 *sc->sc_iflag = 0x80 | (V2IF_SCSIIRQ | V2IF_SCSIDRQ); 1046 *ncr_sc->sci_mode |= SCI_MODE_DMA; 1047 *ncr_sc->sci_icmd = SCI_ICMD_DATA; 1048 *ncr_sc->sci_dma_send = 0; 1049 } else { 1050 *ncr_sc->sci_tcmd = PHASE_DATA_IN; 1051 SCI_CLR_INTR(ncr_sc); 1052 *sc->sc_iflag = 0x80 | (V2IF_SCSIIRQ | V2IF_SCSIDRQ); 1053 *ncr_sc->sci_mode |= SCI_MODE_DMA; 1054 *ncr_sc->sci_icmd = 0; 1055 *ncr_sc->sci_irecv = 0; 1056 } 1057 ncr_sc->sc_state |= NCR_DOINGDMA; 1058 1059 #ifdef SBC_DEBUG 1060 if (sbc_debug & SBC_DB_DMA) 1061 printf("%s: PDMA started, va=%p, len=0x%x\n", 1062 ncr_sc->sc_dev.dv_xname, dh->dh_addr, dh->dh_len); 1063 #endif 1064 } 1065 1066 void 1067 sbc_dma_eop(ncr_sc) 1068 struct ncr5380_softc *ncr_sc; 1069 { 1070 /* Not used; the EOP pin is wired high (GMFH, pp. 389-390) */ 1071 } 1072 1073 void 1074 sbc_dma_stop(ncr_sc) 1075 struct ncr5380_softc *ncr_sc; 1076 { 1077 register struct sbc_softc *sc = (struct sbc_softc *) ncr_sc; 1078 struct sci_req *sr = ncr_sc->sc_current; 1079 struct sbc_pdma_handle *dh = sr->sr_dma_hand; 1080 register int ntrans; 1081 1082 if ((ncr_sc->sc_state & NCR_DOINGDMA) == 0) { 1083 #ifdef SBC_DEBUG 1084 if (sbc_debug & SBC_DB_DMA) 1085 printf("%s: dma_stop: DMA not running\n", 1086 ncr_sc->sc_dev.dv_xname); 1087 #endif 1088 return; 1089 } 1090 ncr_sc->sc_state &= ~NCR_DOINGDMA; 1091 1092 if ((ncr_sc->sc_state & NCR_ABORTING) == 0) { 1093 ntrans = ncr_sc->sc_datalen - dh->dh_len; 1094 1095 #ifdef SBC_DEBUG 1096 if (sbc_debug & SBC_DB_DMA) 1097 printf("%s: dma_stop: ntrans=0x%x\n", 1098 ncr_sc->sc_dev.dv_xname, ntrans); 1099 #endif 1100 1101 if (ntrans > ncr_sc->sc_datalen) 1102 panic("sbc_dma_stop: excess transfer\n"); 1103 1104 /* Adjust data pointer */ 1105 ncr_sc->sc_dataptr += ntrans; 1106 ncr_sc->sc_datalen -= ntrans; 1107 1108 /* Clear any pending interrupts. */ 1109 SCI_CLR_INTR(ncr_sc); 1110 *sc->sc_iflag = 0x80 | V2IF_SCSIIRQ; 1111 } 1112 1113 /* Put SBIC back into PIO mode. */ 1114 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 1115 *ncr_sc->sci_icmd = 0; 1116 1117 #ifdef SBC_DEBUG 1118 if (sbc_debug & SBC_DB_REG) 1119 printf("%s: dma_stop: csr=0x%x, bus_csr=0x%x\n", 1120 ncr_sc->sc_dev.dv_xname, *ncr_sc->sci_csr, 1121 *ncr_sc->sci_bus_csr); 1122 #endif 1123 } 1124
Indexes created Mon Sep 22 13:09:51 GMT 2025