sbc.c revision 1.14
1 /* $NetBSD: sbc.c,v 1.14 1996/11/13 07:02:17 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1996 Scott Reynolds 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the authors may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 4. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgements: 19 * This product includes software developed by Scott Reynolds. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * This file contains only the machine-dependent parts of the mac68k 35 * NCR 5380 SCSI driver. (Autoconfig stuff and PDMA functions.) 36 * The machine-independent parts are in ncr5380sbc.c 37 * 38 * Supported hardware includes: 39 * Macintosh II family 5380-based controller 40 * 41 * Credits, history: 42 * 43 * Scott Reynolds wrote this module, based on work by Allen Briggs 44 * (mac68k), Gordon W. Ross and David Jones (sun3), and Leo Weppelman 45 * (atari). Thanks to Allen for supplying crucial interpretation of the 46 * NetBSD/mac68k 1.1 'ncrscsi' driver. Also, Allen, Gordon, and Jason 47 * Thorpe all helped to refine this code, and were considerable sources 48 * of moral support. 49 */ 50 51 #include <sys/types.h> 52 #include <sys/param.h> 53 #include <sys/systm.h> 54 #include <sys/kernel.h> 55 #include <sys/errno.h> 56 #include <sys/device.h> 57 #include <sys/buf.h> 58 #include <sys/proc.h> 59 #include <sys/user.h> 60 61 #include <scsi/scsi_all.h> 62 #include <scsi/scsi_debug.h> 63 #include <scsi/scsiconf.h> 64 65 #include <dev/ic/ncr5380reg.h> 66 #include <dev/ic/ncr5380var.h> 67 68 #include <machine/cpu.h> 69 #include <machine/viareg.h> 70 71 #include "sbcreg.h" 72 73 /* 74 * Transfers smaller than this are done using PIO 75 * (on assumption they're not worth PDMA overhead) 76 */ 77 #define MIN_DMA_LEN 128 78 79 /* 80 * Transfers larger than 8192 bytes need to be split up 81 * due to the size of the PDMA space. 82 */ 83 #define MAX_DMA_LEN 0x2000 84 85 /* 86 * From Guide to the Macintosh Family Hardware, pp. 137-143 87 * These are offsets from SCSIBase (see pmap_bootstrap.c) 88 */ 89 #define SBC_REG_OFS 0x10000 90 #define SBC_HSK_OFS 0x06000 91 #define SBC_DMA_OFS 0x12000 92 93 #define SBC_DMA_OFS_PB500 0x06000 94 95 #define SBC_REG_OFS_IIFX 0x08000 /* Just guessing... */ 96 #define SBC_HSK_OFS_IIFX 0x0e000 97 #define SBC_DMA_OFS_IIFX 0x0c000 98 99 #ifdef SBC_DEBUG 100 # define SBC_DB_INTR 0x01 101 # define SBC_DB_DMA 0x02 102 # define SBC_DB_REG 0x04 103 # define SBC_DB_BREAK 0x08 104 105 int sbc_debug = 0 /* | SBC_DB_INTR | SBC_DB_DMA */; 106 int sbc_link_flags = 0 /* | SDEV_DB2 */; 107 108 # ifndef DDB 109 # define Debugger() printf("Debug: sbc.c:%d\n", __LINE__) 110 # endif 111 # define SBC_BREAK \ 112 do { if (sbc_debug & SBC_DB_BREAK) Debugger(); } while (0) 113 #else 114 # define SBC_BREAK 115 #endif 116 117 /* 118 * This structure is used to keep track of PDMA requests. 119 */ 120 struct sbc_pdma_handle { 121 int dh_flags; /* flags */ 122 #define SBC_DH_BUSY 0x01 /* This handle is in use */ 123 #define SBC_DH_OUT 0x02 /* PDMA data out (write) */ 124 #define SBC_DH_DONE 0x04 /* PDMA transfer is complete */ 125 u_char *dh_addr; /* data buffer */ 126 int dh_len; /* length of data buffer */ 127 }; 128 129 /* 130 * The first structure member has to be the ncr5380_softc 131 * so we can just cast to go back and forth between them. 132 */ 133 struct sbc_softc { 134 struct ncr5380_softc ncr_sc; 135 volatile struct sbc_regs *sc_regs; 136 volatile vm_offset_t sc_drq_addr; 137 volatile vm_offset_t sc_nodrq_addr; 138 volatile u_int8_t *sc_ienable; 139 volatile u_int8_t *sc_iflag; 140 int sc_options; /* options for this instance. */ 141 struct sbc_pdma_handle sc_pdma[SCI_OPENINGS]; 142 }; 143 144 /* 145 * Options. By default, SCSI interrupts and reselect are disabled. 146 * You may enable either of these features with the `flags' directive 147 * in your kernel's configuration file. 148 * 149 * Alternatively, you can patch your kernel with DDB or some other 150 * mechanism. The sc_options member of the softc is OR'd with 151 * the value in sbc_options. 152 * 153 * The options code is based on the sparc 'si' driver's version of 154 * the same. 155 */ 156 #define SBC_PDMA 0x01 /* Use PDMA for polled transfers */ 157 #define SBC_INTR 0x02 /* Allow SCSI IRQ/DRQ interrupts */ 158 #define SBC_RESELECT 0x04 /* Allow disconnect/reselect */ 159 #define SBC_OPTIONS_MASK (SBC_RESELECT|SBC_INTR|SBC_PDMA) 160 #define SBC_OPTIONS_BITS "\10\3RESELECT\2INTR\1PDMA" 161 int sbc_options = SBC_PDMA; 162 163 static int sbc_match __P((struct device *, void *, void *)); 164 static void sbc_attach __P((struct device *, struct device *, void *)); 165 static void sbc_minphys __P((struct buf *bp)); 166 167 static int sbc_wait_busy __P((struct ncr5380_softc *)); 168 static int sbc_ready __P((struct ncr5380_softc *)); 169 static int sbc_wait_dreq __P((struct ncr5380_softc *)); 170 static int sbc_pdma_in __P((struct ncr5380_softc *, int, int, u_char *)); 171 static int sbc_pdma_out __P((struct ncr5380_softc *, int, int, u_char *)); 172 #ifdef SBC_DEBUG 173 static void decode_5380_intr __P((struct ncr5380_softc *)); 174 #endif 175 176 void sbc_intr_enable __P((struct ncr5380_softc *)); 177 void sbc_intr_disable __P((struct ncr5380_softc *)); 178 void sbc_irq_intr __P((void *)); 179 void sbc_drq_intr __P((void *)); 180 void sbc_dma_alloc __P((struct ncr5380_softc *)); 181 void sbc_dma_free __P((struct ncr5380_softc *)); 182 void sbc_dma_poll __P((struct ncr5380_softc *)); 183 void sbc_dma_setup __P((struct ncr5380_softc *)); 184 void sbc_dma_start __P((struct ncr5380_softc *)); 185 void sbc_dma_eop __P((struct ncr5380_softc *)); 186 void sbc_dma_stop __P((struct ncr5380_softc *)); 187 188 static struct scsi_adapter sbc_ops = { 189 ncr5380_scsi_cmd, /* scsi_cmd() */ 190 sbc_minphys, /* scsi_minphys() */ 191 NULL, /* open_target_lu() */ 192 NULL, /* close_target_lu() */ 193 }; 194 195 /* This is copied from julian's bt driver */ 196 /* "so we have a default dev struct for our link struct." */ 197 static struct scsi_device sbc_dev = { 198 NULL, /* Use default error handler. */ 199 NULL, /* Use default start handler. */ 200 NULL, /* Use default async handler. */ 201 NULL, /* Use default "done" routine. */ 202 }; 203 204 struct cfattach sbc_ca = { 205 sizeof(struct sbc_softc), sbc_match, sbc_attach 206 }; 207 208 struct cfdriver sbc_cd = { 209 NULL, "sbc", DV_DULL 210 }; 211 212 213 static int 214 sbc_match(parent, match, args) 215 struct device *parent; 216 void *match, *args; 217 { 218 if (!mac68k_machine.scsi80) 219 return 0; 220 return 1; 221 } 222 223 static void 224 sbc_attach(parent, self, args) 225 struct device *parent, *self; 226 void *args; 227 { 228 struct sbc_softc *sc = (struct sbc_softc *) self; 229 struct ncr5380_softc *ncr_sc = (struct ncr5380_softc *) sc; 230 char bits[64]; 231 extern vm_offset_t SCSIBase; 232 233 /* Pull in the options flags. */ 234 sc->sc_options = ((ncr_sc->sc_dev.dv_cfdata->cf_flags | sbc_options) 235 & SBC_OPTIONS_MASK); 236 237 /* 238 * Set up offsets to 5380 registers and GLUE I/O space, and turn 239 * off options we know we can't support on certain models. 240 */ 241 switch (current_mac_model->machineid) { 242 case MACH_MACIIFX: /* Note: the IIfx isn't (yet) supported. */ 243 sc->sc_regs = (struct sbc_regs *)(SCSIBase + SBC_REG_OFS_IIFX); 244 sc->sc_drq_addr = (vm_offset_t)(SCSIBase + SBC_HSK_OFS_IIFX); 245 sc->sc_nodrq_addr = (vm_offset_t)(SCSIBase + SBC_DMA_OFS_IIFX); 246 sc->sc_options &= ~(SBC_INTR | SBC_RESELECT); 247 break; 248 case MACH_MACPB500: 249 sc->sc_regs = (struct sbc_regs *)(SCSIBase + SBC_REG_OFS); 250 sc->sc_drq_addr = (vm_offset_t)(SCSIBase + SBC_HSK_OFS); /*??*/ 251 sc->sc_nodrq_addr = (vm_offset_t)(SCSIBase + SBC_DMA_OFS_PB500); 252 sc->sc_options &= ~(SBC_INTR | SBC_RESELECT); 253 break; 254 default: 255 sc->sc_regs = (struct sbc_regs *)(SCSIBase + SBC_REG_OFS); 256 sc->sc_drq_addr = (vm_offset_t)(SCSIBase + SBC_HSK_OFS); 257 sc->sc_nodrq_addr = (vm_offset_t)(SCSIBase + SBC_DMA_OFS); 258 break; 259 } 260 261 /* 262 * Fill in the prototype scsi_link. 263 */ 264 ncr_sc->sc_link.channel = SCSI_CHANNEL_ONLY_ONE; 265 ncr_sc->sc_link.adapter_softc = sc; 266 ncr_sc->sc_link.adapter_target = 7; 267 ncr_sc->sc_link.adapter = &sbc_ops; 268 ncr_sc->sc_link.device = &sbc_dev; 269 270 /* 271 * Initialize fields used by the MI code 272 */ 273 ncr_sc->sci_r0 = &sc->sc_regs->sci_pr0.sci_reg; 274 ncr_sc->sci_r1 = &sc->sc_regs->sci_pr1.sci_reg; 275 ncr_sc->sci_r2 = &sc->sc_regs->sci_pr2.sci_reg; 276 ncr_sc->sci_r3 = &sc->sc_regs->sci_pr3.sci_reg; 277 ncr_sc->sci_r4 = &sc->sc_regs->sci_pr4.sci_reg; 278 ncr_sc->sci_r5 = &sc->sc_regs->sci_pr5.sci_reg; 279 ncr_sc->sci_r6 = &sc->sc_regs->sci_pr6.sci_reg; 280 ncr_sc->sci_r7 = &sc->sc_regs->sci_pr7.sci_reg; 281 282 /* 283 * MD function pointers used by the MI code. 284 */ 285 if (sc->sc_options & SBC_PDMA) { 286 ncr_sc->sc_pio_out = sbc_pdma_out; 287 ncr_sc->sc_pio_in = sbc_pdma_in; 288 } else { 289 ncr_sc->sc_pio_out = ncr5380_pio_out; 290 ncr_sc->sc_pio_in = ncr5380_pio_in; 291 } 292 ncr_sc->sc_dma_alloc = NULL; 293 ncr_sc->sc_dma_free = NULL; 294 ncr_sc->sc_dma_poll = NULL; 295 ncr_sc->sc_intr_on = NULL; 296 ncr_sc->sc_intr_off = NULL; 297 ncr_sc->sc_dma_setup = NULL; 298 ncr_sc->sc_dma_start = NULL; 299 ncr_sc->sc_dma_eop = NULL; 300 ncr_sc->sc_dma_stop = NULL; 301 ncr_sc->sc_flags = 0; 302 ncr_sc->sc_min_dma_len = MIN_DMA_LEN; 303 304 if (sc->sc_options & SBC_INTR) { 305 if (sc->sc_options & SBC_RESELECT) 306 ncr_sc->sc_flags |= NCR5380_PERMIT_RESELECT; 307 ncr_sc->sc_dma_alloc = sbc_dma_alloc; 308 ncr_sc->sc_dma_free = sbc_dma_free; 309 ncr_sc->sc_dma_poll = sbc_dma_poll; 310 ncr_sc->sc_dma_setup = sbc_dma_setup; 311 ncr_sc->sc_dma_start = sbc_dma_start; 312 ncr_sc->sc_dma_eop = sbc_dma_eop; 313 ncr_sc->sc_dma_stop = sbc_dma_stop; 314 mac68k_register_scsi_drq(sbc_drq_intr, ncr_sc); 315 mac68k_register_scsi_irq(sbc_irq_intr, ncr_sc); 316 } else 317 ncr_sc->sc_flags |= NCR5380_FORCE_POLLING; 318 319 /* 320 * Initialize fields used only here in the MD code. 321 */ 322 if (VIA2 == VIA2OFF) { 323 sc->sc_ienable = Via1Base + VIA2 * 0x2000 + vIER; 324 sc->sc_iflag = Via1Base + VIA2 * 0x2000 + vIFR; 325 } else { 326 sc->sc_ienable = Via1Base + VIA2 * 0x2000 + rIER; 327 sc->sc_iflag = Via1Base + VIA2 * 0x2000 + rIFR; 328 } 329 330 if (sc->sc_options) 331 printf(": options=%s", bitmask_snprintf(sc->sc_options, 332 SBC_OPTIONS_BITS, bits, sizeof(bits))); 333 printf("\n"); 334 335 /* Now enable SCSI interrupts through VIA2, if appropriate */ 336 if (sc->sc_options & SBC_INTR) 337 sbc_intr_enable(ncr_sc); 338 339 #ifdef SBC_DEBUG 340 if (sbc_debug) 341 printf("%s: softc=%p regs=%p\n", ncr_sc->sc_dev.dv_xname, 342 sc, sc->sc_regs); 343 ncr_sc->sc_link.flags |= sbc_link_flags; 344 #endif 345 346 /* 347 * Initialize the SCSI controller itself. 348 */ 349 ncr5380_init(ncr_sc); 350 ncr5380_reset_scsibus(ncr_sc); 351 config_found(self, &(ncr_sc->sc_link), scsiprint); 352 } 353 354 static void 355 sbc_minphys(struct buf *bp) 356 { 357 if (bp->b_bcount > MAX_DMA_LEN) 358 bp->b_bcount = MAX_DMA_LEN; 359 return (minphys(bp)); 360 } 361 362 363 /*** 364 * General support for Mac-specific SCSI logic. 365 ***/ 366 367 /* These are used in the following inline functions. */ 368 int sbc_wait_busy_timo = 1000 * 5000; /* X2 = 10 S. */ 369 int sbc_ready_timo = 1000 * 5000; /* X2 = 10 S. */ 370 int sbc_wait_dreq_timo = 1000 * 5000; /* X2 = 10 S. */ 371 372 /* Return zero on success. */ 373 static __inline__ int 374 sbc_wait_busy(sc) 375 struct ncr5380_softc *sc; 376 { 377 register int timo = sbc_wait_busy_timo; 378 for (;;) { 379 if (SCI_BUSY(sc)) { 380 timo = 0; /* return 0 */ 381 break; 382 } 383 if (--timo < 0) 384 break; /* return -1 */ 385 delay(2); 386 } 387 return (timo); 388 } 389 390 static __inline__ int 391 sbc_ready(sc) 392 struct ncr5380_softc *sc; 393 { 394 register int timo = sbc_ready_timo; 395 396 for (;;) { 397 if ((*sc->sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) 398 == (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 399 timo = 0; 400 break; 401 } 402 if (((*sc->sci_csr & SCI_CSR_PHASE_MATCH) == 0) 403 || (SCI_BUSY(sc) == 0)) { 404 timo = -1; 405 break; 406 } 407 if (--timo < 0) 408 break; /* return -1 */ 409 delay(2); 410 } 411 return (timo); 412 } 413 414 static __inline__ int 415 sbc_wait_dreq(sc) 416 struct ncr5380_softc *sc; 417 { 418 register int timo = sbc_wait_dreq_timo; 419 420 for (;;) { 421 if ((*sc->sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) 422 == (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 423 timo = 0; 424 break; 425 } 426 if (--timo < 0) 427 break; /* return -1 */ 428 delay(2); 429 } 430 return (timo); 431 } 432 433 434 /*** 435 * Macintosh SCSI interrupt support routines. 436 ***/ 437 438 void 439 sbc_intr_enable(ncr_sc) 440 struct ncr5380_softc *ncr_sc; 441 { 442 register struct sbc_softc *sc = (struct sbc_softc *) ncr_sc; 443 int s; 444 445 s = splhigh(); 446 *sc->sc_ienable = 0x80 | (V2IF_SCSIIRQ | V2IF_SCSIDRQ); 447 splx(s); 448 } 449 450 void 451 sbc_intr_disable(ncr_sc) 452 struct ncr5380_softc *ncr_sc; 453 { 454 register struct sbc_softc *sc = (struct sbc_softc *) ncr_sc; 455 int s; 456 457 s = splhigh(); 458 *sc->sc_ienable = (V2IF_SCSIIRQ | V2IF_SCSIDRQ); 459 splx(s); 460 } 461 462 void 463 sbc_irq_intr(p) 464 void *p; 465 { 466 register struct ncr5380_softc *ncr_sc = p; 467 register int claimed = 0; 468 469 /* How we ever arrive here without IRQ set is a mystery... */ 470 if (*ncr_sc->sci_csr & SCI_CSR_INT) { 471 #ifdef SBC_DEBUG 472 if (sbc_debug & SBC_DB_INTR) 473 decode_5380_intr(ncr_sc); 474 #endif 475 claimed = ncr5380_intr(ncr_sc); 476 if (!claimed) { 477 if (((*ncr_sc->sci_csr & ~SCI_CSR_PHASE_MATCH) == SCI_CSR_INT) 478 && ((*ncr_sc->sci_bus_csr & ~SCI_BUS_RST) == 0)) 479 SCI_CLR_INTR(ncr_sc); /* RST interrupt */ 480 #ifdef SBC_DEBUG 481 else { 482 printf("%s: spurious intr\n", 483 ncr_sc->sc_dev.dv_xname); 484 SBC_BREAK; 485 } 486 #endif 487 } 488 } 489 } 490 491 #ifdef SBC_DEBUG 492 void 493 decode_5380_intr(ncr_sc) 494 struct ncr5380_softc *ncr_sc; 495 { 496 register u_char csr = *ncr_sc->sci_csr; 497 register u_char bus_csr = *ncr_sc->sci_bus_csr; 498 499 if (((csr & ~(SCI_CSR_PHASE_MATCH | SCI_CSR_ATN)) == SCI_CSR_INT) && 500 ((bus_csr & ~(SCI_BUS_MSG | SCI_BUS_CD | SCI_BUS_IO | SCI_BUS_DBP)) == SCI_BUS_SEL)) { 501 if (csr & SCI_BUS_IO) 502 printf("%s: reselect\n", ncr_sc->sc_dev.dv_xname); 503 else 504 printf("%s: select\n", ncr_sc->sc_dev.dv_xname); 505 } else if (((csr & ~SCI_CSR_ACK) == (SCI_CSR_DONE | SCI_CSR_INT)) && 506 ((bus_csr & (SCI_BUS_RST | SCI_BUS_BSY | SCI_BUS_SEL)) == SCI_BUS_BSY)) 507 printf("%s: dma eop\n", ncr_sc->sc_dev.dv_xname); 508 else if (((csr & ~SCI_CSR_PHASE_MATCH) == SCI_CSR_INT) && 509 ((bus_csr & ~SCI_BUS_RST) == 0)) 510 printf("%s: bus reset\n", ncr_sc->sc_dev.dv_xname); 511 else if (((csr & ~(SCI_CSR_DREQ | SCI_CSR_ATN | SCI_CSR_ACK)) == (SCI_CSR_PERR | SCI_CSR_INT | SCI_CSR_PHASE_MATCH)) && 512 ((bus_csr & (SCI_BUS_RST | SCI_BUS_BSY | SCI_BUS_SEL)) == SCI_BUS_BSY)) 513 printf("%s: parity error\n", ncr_sc->sc_dev.dv_xname); 514 else if (((csr & ~SCI_CSR_ATN) == SCI_CSR_INT) && 515 ((bus_csr & (SCI_BUS_RST | SCI_BUS_BSY | SCI_BUS_REQ | SCI_BUS_SEL)) == (SCI_BUS_BSY | SCI_BUS_REQ))) 516 printf("%s: phase mismatch\n", ncr_sc->sc_dev.dv_xname); 517 else if (((csr & ~SCI_CSR_PHASE_MATCH) == (SCI_CSR_INT | SCI_CSR_DISC)) && 518 (bus_csr == 0)) 519 printf("%s: disconnect\n", ncr_sc->sc_dev.dv_xname); 520 else 521 printf("%s: unknown intr: csr=%x, bus_csr=%x\n", 522 ncr_sc->sc_dev.dv_xname, csr, bus_csr); 523 } 524 #endif 525 526 527 /*** 528 * The following code implements polled PDMA. 529 ***/ 530 531 static int 532 sbc_pdma_out(ncr_sc, phase, count, data) 533 struct ncr5380_softc *ncr_sc; 534 int phase; 535 int count; 536 u_char *data; 537 { 538 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 539 register volatile long *long_data = (long *) sc->sc_drq_addr; 540 register volatile u_char *byte_data = (u_char *) sc->sc_nodrq_addr; 541 register int len = count; 542 543 if (count < ncr_sc->sc_min_dma_len || (sc->sc_options & SBC_PDMA) == 0) 544 return ncr5380_pio_out(ncr_sc, phase, count, data); 545 546 if (sbc_wait_busy(ncr_sc) == 0) { 547 *ncr_sc->sci_mode |= SCI_MODE_DMA; 548 *ncr_sc->sci_icmd |= SCI_ICMD_DATA; 549 *ncr_sc->sci_dma_send = 0; 550 551 #define W1 *byte_data = *data++ 552 #define W4 *long_data = *((long*)data)++ 553 while (len >= 64) { 554 if (sbc_ready(ncr_sc)) 555 goto timeout; 556 W1; 557 if (sbc_ready(ncr_sc)) 558 goto timeout; 559 W1; 560 if (sbc_ready(ncr_sc)) 561 goto timeout; 562 W1; 563 if (sbc_ready(ncr_sc)) 564 goto timeout; 565 W1; 566 if (sbc_ready(ncr_sc)) 567 goto timeout; 568 W4; W4; W4; W4; 569 W4; W4; W4; W4; 570 W4; W4; W4; W4; 571 W4; W4; W4; 572 len -= 64; 573 } 574 while (len) { 575 if (sbc_ready(ncr_sc)) 576 goto timeout; 577 W1; 578 len--; 579 } 580 #undef W1 581 #undef W4 582 if (sbc_wait_dreq(ncr_sc)) 583 printf("%s: timeout waiting for DREQ.\n", 584 ncr_sc->sc_dev.dv_xname); 585 586 *byte_data = 0; 587 588 SCI_CLR_INTR(ncr_sc); 589 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 590 *ncr_sc->sci_icmd = 0; 591 } 592 return count - len; 593 594 timeout: 595 printf("%s: pdma_out: timeout len=%d count=%d\n", 596 ncr_sc->sc_dev.dv_xname, len, count); 597 if ((*ncr_sc->sci_csr & SCI_CSR_PHASE_MATCH) == 0) { 598 *ncr_sc->sci_icmd &= ~SCI_ICMD_DATA; 599 --len; 600 } 601 602 SCI_CLR_INTR(ncr_sc); 603 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 604 *ncr_sc->sci_icmd = 0; 605 return count - len; 606 } 607 608 static int 609 sbc_pdma_in(ncr_sc, phase, count, data) 610 struct ncr5380_softc *ncr_sc; 611 int phase; 612 int count; 613 u_char *data; 614 { 615 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 616 register volatile long *long_data = (long *) sc->sc_drq_addr; 617 register volatile u_char *byte_data = (u_char *) sc->sc_nodrq_addr; 618 register int len = count; 619 620 if (count < ncr_sc->sc_min_dma_len || (sc->sc_options & SBC_PDMA) == 0) 621 return ncr5380_pio_in(ncr_sc, phase, count, data); 622 623 if (sbc_wait_busy(ncr_sc) == 0) { 624 *ncr_sc->sci_mode |= SCI_MODE_DMA; 625 *ncr_sc->sci_icmd |= SCI_ICMD_DATA; 626 *ncr_sc->sci_irecv = 0; 627 628 #define R4 *((long *)data)++ = *long_data 629 #define R1 *data++ = *byte_data 630 while (len >= 1024) { 631 if (sbc_ready(ncr_sc)) 632 goto timeout; 633 R4; R4; R4; R4; R4; R4; R4; R4; 634 R4; R4; R4; R4; R4; R4; R4; R4; 635 R4; R4; R4; R4; R4; R4; R4; R4; 636 R4; R4; R4; R4; R4; R4; R4; R4; /* 128 */ 637 if (sbc_ready(ncr_sc)) 638 goto timeout; 639 R4; R4; R4; R4; R4; R4; R4; R4; 640 R4; R4; R4; R4; R4; R4; R4; R4; 641 R4; R4; R4; R4; R4; R4; R4; R4; 642 R4; R4; R4; R4; R4; R4; R4; R4; /* 256 */ 643 if (sbc_ready(ncr_sc)) 644 goto timeout; 645 R4; R4; R4; R4; R4; R4; R4; R4; 646 R4; R4; R4; R4; R4; R4; R4; R4; 647 R4; R4; R4; R4; R4; R4; R4; R4; 648 R4; R4; R4; R4; R4; R4; R4; R4; /* 384 */ 649 if (sbc_ready(ncr_sc)) 650 goto timeout; 651 R4; R4; R4; R4; R4; R4; R4; R4; 652 R4; R4; R4; R4; R4; R4; R4; R4; 653 R4; R4; R4; R4; R4; R4; R4; R4; 654 R4; R4; R4; R4; R4; R4; R4; R4; /* 512 */ 655 if (sbc_ready(ncr_sc)) 656 goto timeout; 657 R4; R4; R4; R4; R4; R4; R4; R4; 658 R4; R4; R4; R4; R4; R4; R4; R4; 659 R4; R4; R4; R4; R4; R4; R4; R4; 660 R4; R4; R4; R4; R4; R4; R4; R4; /* 640 */ 661 if (sbc_ready(ncr_sc)) 662 goto timeout; 663 R4; R4; R4; R4; R4; R4; R4; R4; 664 R4; R4; R4; R4; R4; R4; R4; R4; 665 R4; R4; R4; R4; R4; R4; R4; R4; 666 R4; R4; R4; R4; R4; R4; R4; R4; /* 768 */ 667 if (sbc_ready(ncr_sc)) 668 goto timeout; 669 R4; R4; R4; R4; R4; R4; R4; R4; 670 R4; R4; R4; R4; R4; R4; R4; R4; 671 R4; R4; R4; R4; R4; R4; R4; R4; 672 R4; R4; R4; R4; R4; R4; R4; R4; /* 896 */ 673 if (sbc_ready(ncr_sc)) 674 goto timeout; 675 R4; R4; R4; R4; R4; R4; R4; R4; 676 R4; R4; R4; R4; R4; R4; R4; R4; 677 R4; R4; R4; R4; R4; R4; R4; R4; 678 R4; R4; R4; R4; R4; R4; R4; R4; /* 1024 */ 679 len -= 1024; 680 } 681 while (len >= 128) { 682 if (sbc_ready(ncr_sc)) 683 goto timeout; 684 R4; R4; R4; R4; R4; R4; R4; R4; 685 R4; R4; R4; R4; R4; R4; R4; R4; 686 R4; R4; R4; R4; R4; R4; R4; R4; 687 R4; R4; R4; R4; R4; R4; R4; R4; /* 128 */ 688 len -= 128; 689 } 690 while (len) { 691 if (sbc_ready(ncr_sc)) 692 goto timeout; 693 R1; 694 len--; 695 } 696 #undef R4 697 #undef R1 698 SCI_CLR_INTR(ncr_sc); 699 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 700 *ncr_sc->sci_icmd = 0; 701 } 702 return count - len; 703 704 timeout: 705 printf("%s: pdma_in: timeout len=%d count=%d\n", 706 ncr_sc->sc_dev.dv_xname, len, count); 707 708 SCI_CLR_INTR(ncr_sc); 709 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 710 *ncr_sc->sci_icmd = 0; 711 return count - len; 712 } 713 714 715 /*** 716 * The following code implements interrupt-driven PDMA. 717 ***/ 718 719 /* 720 * This is the meat of the PDMA transfer. 721 * When we get here, we shove data as fast as the mac can take it. 722 * We depend on several things: 723 * * All macs after the Mac Plus that have a 5380 chip should have a general 724 * logic IC that handshakes data for blind transfers. 725 * * If the SCSI controller finishes sending/receiving data before we do, 726 * the same general logic IC will generate a /BERR for us in short order. 727 * * The fault address for said /BERR minus the base address for the 728 * transfer will be the amount of data that was actually written. 729 * 730 * We use the nofault flag and the setjmp/longjmp in locore.s so we can 731 * detect and handle the bus error for early termination of a command. 732 * This is usually caused by a disconnecting target. 733 */ 734 void 735 sbc_drq_intr(p) 736 void *p; 737 { 738 extern int *nofault, mac68k_buserr_addr; 739 register struct sbc_softc *sc = (struct sbc_softc *) p; 740 register struct ncr5380_softc *ncr_sc = (struct ncr5380_softc *) p; 741 register struct sci_req *sr = ncr_sc->sc_current; 742 register struct sbc_pdma_handle *dh = sr->sr_dma_hand; 743 label_t faultbuf; 744 volatile u_int32_t *long_drq; 745 u_int32_t *long_data; 746 volatile u_int8_t *drq; 747 u_int8_t *data; 748 register int count; 749 int dcount, resid; 750 u_int8_t tmp; 751 752 /* 753 * If we're not ready to xfer data, or have no more, just return. 754 */ 755 if ((*ncr_sc->sci_csr & SCI_CSR_DREQ) == 0 || dh->dh_len == 0) 756 return; 757 758 #ifdef SBC_DEBUG 759 if (sbc_debug & SBC_DB_INTR) 760 printf("%s: drq intr, dh_len=0x%x, dh_flags=0x%x\n", 761 ncr_sc->sc_dev.dv_xname, dh->dh_len, dh->dh_flags); 762 #endif 763 764 /* 765 * Setup for a possible bus error caused by SCSI controller 766 * switching out of DATA-IN/OUT before we're done with the 767 * current transfer. 768 */ 769 nofault = (int *) &faultbuf; 770 771 if (setjmp((label_t *) nofault)) { 772 nofault = (int *) 0; 773 if ((dh->dh_flags & SBC_DH_DONE) == 0) { 774 count = (( (u_long) mac68k_buserr_addr 775 - (u_long) sc->sc_drq_addr)); 776 777 if ((count < 0) || (count > dh->dh_len)) { 778 printf("%s: complete=0x%x (pending 0x%x)\n", 779 ncr_sc->sc_dev.dv_xname, count, dh->dh_len); 780 panic("something is wrong"); 781 } 782 783 dh->dh_addr += count; 784 dh->dh_len -= count; 785 } 786 787 #ifdef SBC_DEBUG 788 if (sbc_debug & SBC_DB_INTR) 789 printf("%s: drq /berr, complete=0x%x (pending 0x%x)\n", 790 ncr_sc->sc_dev.dv_xname, count, dh->dh_len); 791 #endif 792 mac68k_buserr_addr = 0; 793 794 return; 795 } 796 797 if (dh->dh_flags & SBC_DH_OUT) { /* Data Out */ 798 #if notyet /* XXX */ 799 /* 800 * Get the source address aligned. 801 */ 802 resid = 803 count = min(dh->dh_len, 4 - (((int) dh->dh_addr) & 0x3)); 804 if (count && count < 4) { 805 drq = (volatile u_int8_t *) sc->sc_drq_addr; 806 data = (u_int8_t *) dh->dh_addr; 807 808 #define W1 *drq++ = *data++ 809 while (count) { 810 W1; count--; 811 } 812 #undef W1 813 dh->dh_addr += resid; 814 dh->dh_len -= resid; 815 } 816 817 /* 818 * Start the transfer. 819 */ 820 while (dh->dh_len) { 821 dcount = count = min(dh->dh_len, MAX_DMA_LEN); 822 long_drq = (volatile u_int32_t *) sc->sc_drq_addr; 823 long_data = (u_int32_t *) dh->dh_addr; 824 825 #define W4 *long_drq++ = *long_data++ 826 while (count >= 64) { 827 W4; W4; W4; W4; W4; W4; W4; W4; 828 W4; W4; W4; W4; W4; W4; W4; W4; /* 64 */ 829 count -= 64; 830 } 831 while (count >= 4) { 832 W4; count -= 4; 833 } 834 #undef W4 835 data = (u_int8_t *) long_data; 836 drq = (u_int8_t *) long_drq; 837 #else /* notyet */ 838 /* 839 * Start the transfer. 840 */ 841 while (dh->dh_len) { 842 dcount = count = min(dh->dh_len, MAX_DMA_LEN); 843 drq = (volatile u_int8_t *) sc->sc_drq_addr; 844 data = (u_int8_t *) dh->dh_addr; 845 #endif /* notyet */ 846 847 #define W1 *drq++ = *data++ 848 while (count) { 849 W1; count--; 850 } 851 #undef W1 852 dh->dh_len -= dcount; 853 dh->dh_addr += dcount; 854 } 855 dh->dh_flags |= SBC_DH_DONE; 856 857 /* 858 * XXX -- Read a byte from the SBC to trigger a /BERR. 859 * This seems to be necessary for us to notice that 860 * the target has disconnected. Ick. 06 jun 1996 (sr) 861 */ 862 if (dcount >= MAX_DMA_LEN) { 863 #if 0 864 while ((*ncr_sc->sci_csr & SCI_CSR_ACK) == 0) 865 ; 866 #endif 867 drq = (volatile u_int8_t *) sc->sc_drq_addr; 868 } 869 tmp = *drq; 870 } else { /* Data In */ 871 /* 872 * Get the dest address aligned. 873 */ 874 resid = 875 count = min(dh->dh_len, 4 - (((int) dh->dh_addr) & 0x3)); 876 if (count && count < 4) { 877 data = (u_int8_t *) dh->dh_addr; 878 drq = (volatile u_int8_t *) sc->sc_drq_addr; 879 880 #define R1 *data++ = *drq++ 881 while (count) { 882 R1; count--; 883 } 884 #undef R1 885 dh->dh_addr += resid; 886 dh->dh_len -= resid; 887 } 888 889 /* 890 * Start the transfer. 891 */ 892 while (dh->dh_len) { 893 dcount = count = min(dh->dh_len, MAX_DMA_LEN); 894 long_data = (u_int32_t *) dh->dh_addr; 895 long_drq = (volatile u_int32_t *) sc->sc_drq_addr; 896 897 #define R4 *long_data++ = *long_drq++ 898 while (count >= 64) { 899 R4; R4; R4; R4; R4; R4; R4; R4; 900 R4; R4; R4; R4; R4; R4; R4; R4; /* 64 */ 901 count -= 64; 902 } 903 while (count >= 4) { 904 R4; count -= 4; 905 } 906 #undef R4 907 data = (u_int8_t *) long_data; 908 drq = (volatile u_int8_t *) long_drq; 909 910 #define R1 *data++ = *drq++ 911 while (count) { 912 R1; count--; 913 } 914 #undef R1 915 dh->dh_len -= dcount; 916 dh->dh_addr += dcount; 917 } 918 dh->dh_flags |= SBC_DH_DONE; 919 } 920 921 /* 922 * OK. No bus error occurred above. Clear the nofault flag 923 * so we no longer short-circuit bus errors. 924 */ 925 nofault = (int *) 0; 926 927 #ifdef SBC_DEBUG 928 if (sbc_debug & (SBC_DB_REG | SBC_DB_INTR)) 929 printf("%s: drq intr complete: csr=0x%x, bus_csr=0x%x\n", 930 ncr_sc->sc_dev.dv_xname, *ncr_sc->sci_csr, 931 *ncr_sc->sci_bus_csr); 932 #endif 933 } 934 935 void 936 sbc_dma_alloc(ncr_sc) 937 struct ncr5380_softc *ncr_sc; 938 { 939 struct sbc_softc *sc = (struct sbc_softc *) ncr_sc; 940 struct sci_req *sr = ncr_sc->sc_current; 941 struct scsi_xfer *xs = sr->sr_xs; 942 struct sbc_pdma_handle *dh; 943 int i, xlen; 944 945 #ifdef DIAGNOSTIC 946 if (sr->sr_dma_hand != NULL) 947 panic("sbc_dma_alloc: already have PDMA handle"); 948 #endif 949 950 /* Polled transfers shouldn't allocate a PDMA handle. */ 951 if (sr->sr_flags & SR_IMMED) 952 return; 953 954 xlen = ncr_sc->sc_datalen; 955 956 /* Make sure our caller checked sc_min_dma_len. */ 957 if (xlen < MIN_DMA_LEN) 958 panic("sbc_dma_alloc: len=0x%x\n", xlen); 959 960 /* 961 * Find free PDMA handle. Guaranteed to find one since we 962 * have as many PDMA handles as the driver has processes. 963 * (instances?) 964 */ 965 for (i = 0; i < SCI_OPENINGS; i++) { 966 if ((sc->sc_pdma[i].dh_flags & SBC_DH_BUSY) == 0) 967 goto found; 968 } 969 panic("sbc: no free PDMA handles"); 970 found: 971 dh = &sc->sc_pdma[i]; 972 dh->dh_flags = SBC_DH_BUSY; 973 dh->dh_addr = ncr_sc->sc_dataptr; 974 dh->dh_len = xlen; 975 976 /* Copy the 'write' flag for convenience. */ 977 if (xs->flags & SCSI_DATA_OUT) 978 dh->dh_flags |= SBC_DH_OUT; 979 980 sr->sr_dma_hand = dh; 981 } 982 983 void 984 sbc_dma_free(ncr_sc) 985 struct ncr5380_softc *ncr_sc; 986 { 987 struct sci_req *sr = ncr_sc->sc_current; 988 struct sbc_pdma_handle *dh = sr->sr_dma_hand; 989 990 #ifdef DIAGNOSTIC 991 if (sr->sr_dma_hand == NULL) 992 panic("sbc_dma_free: no DMA handle"); 993 #endif 994 995 if (ncr_sc->sc_state & NCR_DOINGDMA) 996 panic("sbc_dma_free: free while in progress"); 997 998 if (dh->dh_flags & SBC_DH_BUSY) { 999 dh->dh_flags = 0; 1000 dh->dh_addr = NULL; 1001 dh->dh_len = 0; 1002 } 1003 sr->sr_dma_hand = NULL; 1004 } 1005 1006 void 1007 sbc_dma_poll(ncr_sc) 1008 struct ncr5380_softc *ncr_sc; 1009 { 1010 struct sci_req *sr = ncr_sc->sc_current; 1011 1012 /* 1013 * We shouldn't arrive here; if SR_IMMED is set, then 1014 * dma_alloc() should have refused to allocate a handle 1015 * for the transfer. This forces the polled PDMA code 1016 * to handle the request... 1017 */ 1018 #ifdef SBC_DEBUG 1019 if (sbc_debug & SBC_DB_DMA) 1020 printf("%s: lost DRQ interrupt?\n", ncr_sc->sc_dev.dv_xname); 1021 #endif 1022 sr->sr_flags |= SR_OVERDUE; 1023 } 1024 1025 void 1026 sbc_dma_setup(ncr_sc) 1027 struct ncr5380_softc *ncr_sc; 1028 { 1029 /* Not needed; we don't have real DMA */ 1030 } 1031 1032 void 1033 sbc_dma_start(ncr_sc) 1034 struct ncr5380_softc *ncr_sc; 1035 { 1036 register struct sbc_softc *sc = (struct sbc_softc *) ncr_sc; 1037 struct sci_req *sr = ncr_sc->sc_current; 1038 struct sbc_pdma_handle *dh = sr->sr_dma_hand; 1039 1040 /* 1041 * Match bus phase, clear pending interrupts, set DMA mode, and 1042 * assert data bus (for writing only), then start the transfer. 1043 */ 1044 if (dh->dh_flags & SBC_DH_OUT) { 1045 *ncr_sc->sci_tcmd = PHASE_DATA_OUT; 1046 SCI_CLR_INTR(ncr_sc); 1047 *sc->sc_iflag = 0x80 | (V2IF_SCSIIRQ | V2IF_SCSIDRQ); 1048 *ncr_sc->sci_mode |= SCI_MODE_DMA; 1049 *ncr_sc->sci_icmd = SCI_ICMD_DATA; 1050 *ncr_sc->sci_dma_send = 0; 1051 } else { 1052 *ncr_sc->sci_tcmd = PHASE_DATA_IN; 1053 SCI_CLR_INTR(ncr_sc); 1054 *sc->sc_iflag = 0x80 | (V2IF_SCSIIRQ | V2IF_SCSIDRQ); 1055 *ncr_sc->sci_mode |= SCI_MODE_DMA; 1056 *ncr_sc->sci_icmd = 0; 1057 *ncr_sc->sci_irecv = 0; 1058 } 1059 ncr_sc->sc_state |= NCR_DOINGDMA; 1060 1061 #ifdef SBC_DEBUG 1062 if (sbc_debug & SBC_DB_DMA) 1063 printf("%s: PDMA started, va=%p, len=0x%x\n", 1064 ncr_sc->sc_dev.dv_xname, dh->dh_addr, dh->dh_len); 1065 #endif 1066 } 1067 1068 void 1069 sbc_dma_eop(ncr_sc) 1070 struct ncr5380_softc *ncr_sc; 1071 { 1072 /* Not used; the EOP pin is wired high (GMFH, pp. 389-390) */ 1073 } 1074 1075 void 1076 sbc_dma_stop(ncr_sc) 1077 struct ncr5380_softc *ncr_sc; 1078 { 1079 register struct sbc_softc *sc = (struct sbc_softc *) ncr_sc; 1080 struct sci_req *sr = ncr_sc->sc_current; 1081 struct sbc_pdma_handle *dh = sr->sr_dma_hand; 1082 register int ntrans; 1083 1084 if ((ncr_sc->sc_state & NCR_DOINGDMA) == 0) { 1085 #ifdef SBC_DEBUG 1086 if (sbc_debug & SBC_DB_DMA) 1087 printf("%s: dma_stop: DMA not running\n", 1088 ncr_sc->sc_dev.dv_xname); 1089 #endif 1090 return; 1091 } 1092 ncr_sc->sc_state &= ~NCR_DOINGDMA; 1093 1094 if ((ncr_sc->sc_state & NCR_ABORTING) == 0) { 1095 ntrans = ncr_sc->sc_datalen - dh->dh_len; 1096 1097 #ifdef SBC_DEBUG 1098 if (sbc_debug & SBC_DB_DMA) 1099 printf("%s: dma_stop: ntrans=0x%x\n", 1100 ncr_sc->sc_dev.dv_xname, ntrans); 1101 #endif 1102 1103 if (ntrans > ncr_sc->sc_datalen) 1104 panic("sbc_dma_stop: excess transfer\n"); 1105 1106 /* Adjust data pointer */ 1107 ncr_sc->sc_dataptr += ntrans; 1108 ncr_sc->sc_datalen -= ntrans; 1109 1110 /* Clear any pending interrupts. */ 1111 SCI_CLR_INTR(ncr_sc); 1112 *sc->sc_iflag = 0x80 | V2IF_SCSIIRQ; 1113 } 1114 1115 /* Put SBIC back into PIO mode. */ 1116 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 1117 *ncr_sc->sci_icmd = 0; 1118 1119 #ifdef SBC_DEBUG 1120 if (sbc_debug & SBC_DB_REG) 1121 printf("%s: dma_stop: csr=0x%x, bus_csr=0x%x\n", 1122 ncr_sc->sc_dev.dv_xname, *ncr_sc->sci_csr, 1123 *ncr_sc->sci_bus_csr); 1124 #endif 1125 } 1126
Indexes created Mon Sep 22 21:09:42 GMT 2025