sbc.c revision 1.18
1 /* $NetBSD: sbc.c,v 1.18 1997/01/20 04:27:49 scottr Exp $ */ 2 3 /* 4 * Copyright (c) 1996 Scott Reynolds 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the authors may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 4. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgements: 19 * This product includes software developed by Scott Reynolds. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * This file contains only the machine-dependent parts of the mac68k 35 * NCR 5380 SCSI driver. (Autoconfig stuff and PDMA functions.) 36 * The machine-independent parts are in ncr5380sbc.c 37 * 38 * Supported hardware includes: 39 * Macintosh II family 5380-based controller 40 * 41 * Credits, history: 42 * 43 * Scott Reynolds wrote this module, based on work by Allen Briggs 44 * (mac68k), Gordon W. Ross and David Jones (sun3), and Leo Weppelman 45 * (atari). Thanks to Allen for supplying crucial interpretation of the 46 * NetBSD/mac68k 1.1 'ncrscsi' driver. Also, Allen, Gordon, and Jason 47 * Thorpe all helped to refine this code, and were considerable sources 48 * of moral support. 49 */ 50 51 #include <sys/types.h> 52 #include <sys/param.h> 53 #include <sys/systm.h> 54 #include <sys/kernel.h> 55 #include <sys/errno.h> 56 #include <sys/device.h> 57 #include <sys/buf.h> 58 #include <sys/proc.h> 59 #include <sys/user.h> 60 61 #include <scsi/scsi_all.h> 62 #include <scsi/scsi_debug.h> 63 #include <scsi/scsiconf.h> 64 65 #include <dev/ic/ncr5380reg.h> 66 #include <dev/ic/ncr5380var.h> 67 68 #include <machine/cpu.h> 69 #include <machine/viareg.h> 70 71 #include "sbcreg.h" 72 73 /* 74 * Transfers smaller than this are done using PIO 75 * (on assumption they're not worth PDMA overhead) 76 */ 77 #define MIN_DMA_LEN 128 78 79 /* 80 * Transfers larger than 8192 bytes need to be split up 81 * due to the size of the PDMA space. 82 */ 83 #define MAX_DMA_LEN 0x2000 84 85 /* 86 * From Guide to the Macintosh Family Hardware, pp. 137-143 87 * These are offsets from SCSIBase (see pmap_bootstrap.c) 88 */ 89 #define SBC_REG_OFS 0x10000 90 #define SBC_DMA_OFS 0x12000 91 #define SBC_HSK_OFS 0x06000 92 93 #define SBC_DMA_OFS_PB500 0x06000 94 95 #define SBC_REG_OFS_IIFX 0x08000 /* Just guessing... */ 96 #define SBC_DMA_OFS_IIFX 0x0c000 97 #define SBC_HSK_OFS_IIFX 0x0e000 98 99 #define SBC_REG_OFS_DUO2 0x00000 100 #define SBC_DMA_OFS_DUO2 0x02000 101 #define SBC_HSK_OFS_DUO2 0x04000 102 103 #ifdef SBC_DEBUG 104 # define SBC_DB_INTR 0x01 105 # define SBC_DB_DMA 0x02 106 # define SBC_DB_REG 0x04 107 # define SBC_DB_BREAK 0x08 108 109 int sbc_debug = 0 /* | SBC_DB_INTR | SBC_DB_DMA */; 110 int sbc_link_flags = 0 /* | SDEV_DB2 */; 111 112 # ifndef DDB 113 # define Debugger() printf("Debug: sbc.c:%d\n", __LINE__) 114 # endif 115 # define SBC_BREAK \ 116 do { if (sbc_debug & SBC_DB_BREAK) Debugger(); } while (0) 117 #else 118 # define SBC_BREAK 119 #endif 120 121 /* 122 * This structure is used to keep track of PDMA requests. 123 */ 124 struct sbc_pdma_handle { 125 int dh_flags; /* flags */ 126 #define SBC_DH_BUSY 0x01 /* This handle is in use */ 127 #define SBC_DH_OUT 0x02 /* PDMA data out (write) */ 128 #define SBC_DH_DONE 0x04 /* PDMA transfer is complete */ 129 u_char *dh_addr; /* data buffer */ 130 int dh_len; /* length of data buffer */ 131 }; 132 133 /* 134 * The first structure member has to be the ncr5380_softc 135 * so we can just cast to go back and forth between them. 136 */ 137 struct sbc_softc { 138 struct ncr5380_softc ncr_sc; 139 volatile struct sbc_regs *sc_regs; 140 volatile vm_offset_t sc_drq_addr; 141 volatile vm_offset_t sc_nodrq_addr; 142 volatile u_int8_t *sc_ienable; 143 volatile u_int8_t *sc_iflag; 144 int sc_options; /* options for this instance. */ 145 struct sbc_pdma_handle sc_pdma[SCI_OPENINGS]; 146 }; 147 148 /* 149 * Options. By default, SCSI interrupts and reselect are disabled. 150 * You may enable either of these features with the `flags' directive 151 * in your kernel's configuration file. 152 * 153 * Alternatively, you can patch your kernel with DDB or some other 154 * mechanism. The sc_options member of the softc is OR'd with 155 * the value in sbc_options. 156 * 157 * The options code is based on the sparc 'si' driver's version of 158 * the same. 159 */ 160 #define SBC_PDMA 0x01 /* Use PDMA for polled transfers */ 161 #define SBC_INTR 0x02 /* Allow SCSI IRQ/DRQ interrupts */ 162 #define SBC_RESELECT 0x04 /* Allow disconnect/reselect */ 163 #define SBC_OPTIONS_MASK (SBC_RESELECT|SBC_INTR|SBC_PDMA) 164 #define SBC_OPTIONS_BITS "\10\3RESELECT\2INTR\1PDMA" 165 int sbc_options = SBC_PDMA; 166 167 static int sbc_match __P((struct device *, struct cfdata *, void *)); 168 static void sbc_attach __P((struct device *, struct device *, void *)); 169 static void sbc_minphys __P((struct buf *bp)); 170 171 static int sbc_wait_busy __P((struct ncr5380_softc *)); 172 static int sbc_ready __P((struct ncr5380_softc *)); 173 static int sbc_wait_dreq __P((struct ncr5380_softc *)); 174 static int sbc_pdma_in __P((struct ncr5380_softc *, int, int, u_char *)); 175 static int sbc_pdma_out __P((struct ncr5380_softc *, int, int, u_char *)); 176 #ifdef SBC_DEBUG 177 static void decode_5380_intr __P((struct ncr5380_softc *)); 178 #endif 179 180 void sbc_intr_enable __P((struct ncr5380_softc *)); 181 void sbc_intr_disable __P((struct ncr5380_softc *)); 182 void sbc_irq_intr __P((void *)); 183 void sbc_drq_intr __P((void *)); 184 void sbc_dma_alloc __P((struct ncr5380_softc *)); 185 void sbc_dma_free __P((struct ncr5380_softc *)); 186 void sbc_dma_poll __P((struct ncr5380_softc *)); 187 void sbc_dma_setup __P((struct ncr5380_softc *)); 188 void sbc_dma_start __P((struct ncr5380_softc *)); 189 void sbc_dma_eop __P((struct ncr5380_softc *)); 190 void sbc_dma_stop __P((struct ncr5380_softc *)); 191 192 static struct scsi_adapter sbc_ops = { 193 ncr5380_scsi_cmd, /* scsi_cmd() */ 194 sbc_minphys, /* scsi_minphys() */ 195 NULL, /* open_target_lu() */ 196 NULL, /* close_target_lu() */ 197 }; 198 199 /* This is copied from julian's bt driver */ 200 /* "so we have a default dev struct for our link struct." */ 201 static struct scsi_device sbc_dev = { 202 NULL, /* Use default error handler. */ 203 NULL, /* Use default start handler. */ 204 NULL, /* Use default async handler. */ 205 NULL, /* Use default "done" routine. */ 206 }; 207 208 struct cfattach sbc_ca = { 209 sizeof(struct sbc_softc), sbc_match, sbc_attach 210 }; 211 212 struct cfdriver sbc_cd = { 213 NULL, "sbc", DV_DULL 214 }; 215 216 217 static int 218 sbc_match(parent, cf, args) 219 struct device *parent; 220 struct cfdata *cf; 221 void *args; 222 { 223 switch (current_mac_model->machineid) { 224 case MACH_MACIIFX: /* Note: the IIfx isn't (yet) supported. */ 225 break; 226 case MACH_MACPB210: 227 case MACH_MACPB230: 228 case MACH_MACPB250: 229 case MACH_MACPB270: 230 case MACH_MACPB280: 231 case MACH_MACPB280C: 232 if (cf->cf_unit == 1) 233 return 1; 234 /*FALLTHROUGH*/ 235 default: 236 if (cf->cf_unit == 0 && mac68k_machine.scsi80) 237 return 1; 238 } 239 return 0; 240 } 241 242 static void 243 sbc_attach(parent, self, args) 244 struct device *parent, *self; 245 void *args; 246 { 247 struct sbc_softc *sc = (struct sbc_softc *) self; 248 struct ncr5380_softc *ncr_sc = (struct ncr5380_softc *) sc; 249 char bits[64]; 250 extern vm_offset_t SCSIBase; 251 252 /* Pull in the options flags. */ 253 sc->sc_options = ((ncr_sc->sc_dev.dv_cfdata->cf_flags | sbc_options) 254 & SBC_OPTIONS_MASK); 255 256 /* 257 * Set up offsets to 5380 registers and GLUE I/O space, and turn 258 * off options we know we can't support on certain models. 259 */ 260 switch (current_mac_model->machineid) { 261 case MACH_MACIIFX: /* Note: the IIfx isn't (yet) supported. */ 262 sc->sc_regs = (struct sbc_regs *)(SCSIBase + SBC_REG_OFS_IIFX); 263 sc->sc_drq_addr = (vm_offset_t)(SCSIBase + SBC_HSK_OFS_IIFX); 264 sc->sc_nodrq_addr = (vm_offset_t)(SCSIBase + SBC_DMA_OFS_IIFX); 265 sc->sc_options &= ~(SBC_INTR | SBC_RESELECT); 266 break; 267 case MACH_MACPB500: 268 sc->sc_regs = (struct sbc_regs *)(SCSIBase + SBC_REG_OFS); 269 sc->sc_drq_addr = (vm_offset_t)(SCSIBase + SBC_HSK_OFS); /*??*/ 270 sc->sc_nodrq_addr = (vm_offset_t)(SCSIBase + SBC_DMA_OFS_PB500); 271 sc->sc_options &= ~(SBC_INTR | SBC_RESELECT); 272 break; 273 case MACH_MACPB210: 274 case MACH_MACPB230: 275 case MACH_MACPB250: 276 case MACH_MACPB270: 277 case MACH_MACPB280: 278 case MACH_MACPB280C: 279 if (ncr_sc->sc_dev.dv_unit == 1) { 280 sc->sc_regs = (struct sbc_regs *)(0xfee00000 + SBC_REG_OFS_DUO2); 281 sc->sc_drq_addr = (vm_offset_t)(0xfee00000 + SBC_HSK_OFS_DUO2); 282 sc->sc_nodrq_addr = (vm_offset_t)(0xfee00000 + SBC_DMA_OFS_DUO2); 283 break; 284 } 285 /*FALLTHROUGH*/ 286 default: 287 sc->sc_regs = (struct sbc_regs *)(SCSIBase + SBC_REG_OFS); 288 sc->sc_drq_addr = (vm_offset_t)(SCSIBase + SBC_HSK_OFS); 289 sc->sc_nodrq_addr = (vm_offset_t)(SCSIBase + SBC_DMA_OFS); 290 break; 291 } 292 293 /* 294 * Fill in the prototype scsi_link. 295 */ 296 ncr_sc->sc_link.channel = SCSI_CHANNEL_ONLY_ONE; 297 ncr_sc->sc_link.adapter_softc = sc; 298 ncr_sc->sc_link.adapter_target = 7; 299 ncr_sc->sc_link.adapter = &sbc_ops; 300 ncr_sc->sc_link.device = &sbc_dev; 301 302 /* 303 * Initialize fields used by the MI code 304 */ 305 ncr_sc->sci_r0 = &sc->sc_regs->sci_pr0.sci_reg; 306 ncr_sc->sci_r1 = &sc->sc_regs->sci_pr1.sci_reg; 307 ncr_sc->sci_r2 = &sc->sc_regs->sci_pr2.sci_reg; 308 ncr_sc->sci_r3 = &sc->sc_regs->sci_pr3.sci_reg; 309 ncr_sc->sci_r4 = &sc->sc_regs->sci_pr4.sci_reg; 310 ncr_sc->sci_r5 = &sc->sc_regs->sci_pr5.sci_reg; 311 ncr_sc->sci_r6 = &sc->sc_regs->sci_pr6.sci_reg; 312 ncr_sc->sci_r7 = &sc->sc_regs->sci_pr7.sci_reg; 313 314 /* 315 * MD function pointers used by the MI code. 316 */ 317 if (sc->sc_options & SBC_PDMA) { 318 ncr_sc->sc_pio_out = sbc_pdma_out; 319 ncr_sc->sc_pio_in = sbc_pdma_in; 320 } else { 321 ncr_sc->sc_pio_out = ncr5380_pio_out; 322 ncr_sc->sc_pio_in = ncr5380_pio_in; 323 } 324 ncr_sc->sc_dma_alloc = NULL; 325 ncr_sc->sc_dma_free = NULL; 326 ncr_sc->sc_dma_poll = NULL; 327 ncr_sc->sc_intr_on = NULL; 328 ncr_sc->sc_intr_off = NULL; 329 ncr_sc->sc_dma_setup = NULL; 330 ncr_sc->sc_dma_start = NULL; 331 ncr_sc->sc_dma_eop = NULL; 332 ncr_sc->sc_dma_stop = NULL; 333 ncr_sc->sc_flags = 0; 334 ncr_sc->sc_min_dma_len = MIN_DMA_LEN; 335 336 if (sc->sc_options & SBC_INTR) { 337 if (sc->sc_options & SBC_RESELECT) 338 ncr_sc->sc_flags |= NCR5380_PERMIT_RESELECT; 339 ncr_sc->sc_dma_alloc = sbc_dma_alloc; 340 ncr_sc->sc_dma_free = sbc_dma_free; 341 ncr_sc->sc_dma_poll = sbc_dma_poll; 342 ncr_sc->sc_dma_setup = sbc_dma_setup; 343 ncr_sc->sc_dma_start = sbc_dma_start; 344 ncr_sc->sc_dma_eop = sbc_dma_eop; 345 ncr_sc->sc_dma_stop = sbc_dma_stop; 346 mac68k_register_scsi_drq(sbc_drq_intr, ncr_sc); 347 mac68k_register_scsi_irq(sbc_irq_intr, ncr_sc); 348 } else 349 ncr_sc->sc_flags |= NCR5380_FORCE_POLLING; 350 351 /* 352 * Initialize fields used only here in the MD code. 353 */ 354 if (VIA2 == VIA2OFF) { 355 sc->sc_ienable = Via1Base + VIA2 * 0x2000 + vIER; 356 sc->sc_iflag = Via1Base + VIA2 * 0x2000 + vIFR; 357 } else { 358 sc->sc_ienable = Via1Base + VIA2 * 0x2000 + rIER; 359 sc->sc_iflag = Via1Base + VIA2 * 0x2000 + rIFR; 360 } 361 362 if (sc->sc_options) 363 printf(": options=%s", bitmask_snprintf(sc->sc_options, 364 SBC_OPTIONS_BITS, bits, sizeof(bits))); 365 printf("\n"); 366 367 /* Now enable SCSI interrupts through VIA2, if appropriate */ 368 if (sc->sc_options & SBC_INTR) 369 sbc_intr_enable(ncr_sc); 370 371 #ifdef SBC_DEBUG 372 if (sbc_debug) 373 printf("%s: softc=%p regs=%p\n", ncr_sc->sc_dev.dv_xname, 374 sc, sc->sc_regs); 375 ncr_sc->sc_link.flags |= sbc_link_flags; 376 #endif 377 378 /* 379 * Initialize the SCSI controller itself. 380 */ 381 ncr5380_init(ncr_sc); 382 ncr5380_reset_scsibus(ncr_sc); 383 config_found(self, &(ncr_sc->sc_link), scsiprint); 384 } 385 386 static void 387 sbc_minphys(struct buf *bp) 388 { 389 if (bp->b_bcount > MAX_DMA_LEN) 390 bp->b_bcount = MAX_DMA_LEN; 391 return (minphys(bp)); 392 } 393 394 395 /*** 396 * General support for Mac-specific SCSI logic. 397 ***/ 398 399 /* These are used in the following inline functions. */ 400 int sbc_wait_busy_timo = 1000 * 5000; /* X2 = 10 S. */ 401 int sbc_ready_timo = 1000 * 5000; /* X2 = 10 S. */ 402 int sbc_wait_dreq_timo = 1000 * 5000; /* X2 = 10 S. */ 403 404 /* Return zero on success. */ 405 static __inline__ int 406 sbc_wait_busy(sc) 407 struct ncr5380_softc *sc; 408 { 409 register int timo = sbc_wait_busy_timo; 410 for (;;) { 411 if (SCI_BUSY(sc)) { 412 timo = 0; /* return 0 */ 413 break; 414 } 415 if (--timo < 0) 416 break; /* return -1 */ 417 delay(2); 418 } 419 return (timo); 420 } 421 422 static __inline__ int 423 sbc_ready(sc) 424 struct ncr5380_softc *sc; 425 { 426 register int timo = sbc_ready_timo; 427 428 for (;;) { 429 if ((*sc->sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) 430 == (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 431 timo = 0; 432 break; 433 } 434 if (((*sc->sci_csr & SCI_CSR_PHASE_MATCH) == 0) 435 || (SCI_BUSY(sc) == 0)) { 436 timo = -1; 437 break; 438 } 439 if (--timo < 0) 440 break; /* return -1 */ 441 delay(2); 442 } 443 return (timo); 444 } 445 446 static __inline__ int 447 sbc_wait_dreq(sc) 448 struct ncr5380_softc *sc; 449 { 450 register int timo = sbc_wait_dreq_timo; 451 452 for (;;) { 453 if ((*sc->sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) 454 == (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 455 timo = 0; 456 break; 457 } 458 if (--timo < 0) 459 break; /* return -1 */ 460 delay(2); 461 } 462 return (timo); 463 } 464 465 466 /*** 467 * Macintosh SCSI interrupt support routines. 468 ***/ 469 470 void 471 sbc_intr_enable(ncr_sc) 472 struct ncr5380_softc *ncr_sc; 473 { 474 register struct sbc_softc *sc = (struct sbc_softc *) ncr_sc; 475 int s; 476 477 s = splhigh(); 478 *sc->sc_ienable = 0x80 | (V2IF_SCSIIRQ | V2IF_SCSIDRQ); 479 splx(s); 480 } 481 482 void 483 sbc_intr_disable(ncr_sc) 484 struct ncr5380_softc *ncr_sc; 485 { 486 register struct sbc_softc *sc = (struct sbc_softc *) ncr_sc; 487 int s; 488 489 s = splhigh(); 490 *sc->sc_ienable = (V2IF_SCSIIRQ | V2IF_SCSIDRQ); 491 splx(s); 492 } 493 494 void 495 sbc_irq_intr(p) 496 void *p; 497 { 498 register struct ncr5380_softc *ncr_sc = p; 499 register int claimed = 0; 500 501 /* How we ever arrive here without IRQ set is a mystery... */ 502 if (*ncr_sc->sci_csr & SCI_CSR_INT) { 503 #ifdef SBC_DEBUG 504 if (sbc_debug & SBC_DB_INTR) 505 decode_5380_intr(ncr_sc); 506 #endif 507 claimed = ncr5380_intr(ncr_sc); 508 if (!claimed) { 509 if (((*ncr_sc->sci_csr & ~SCI_CSR_PHASE_MATCH) == SCI_CSR_INT) 510 && ((*ncr_sc->sci_bus_csr & ~SCI_BUS_RST) == 0)) 511 SCI_CLR_INTR(ncr_sc); /* RST interrupt */ 512 #ifdef SBC_DEBUG 513 else { 514 printf("%s: spurious intr\n", 515 ncr_sc->sc_dev.dv_xname); 516 SBC_BREAK; 517 } 518 #endif 519 } 520 } 521 } 522 523 #ifdef SBC_DEBUG 524 void 525 decode_5380_intr(ncr_sc) 526 struct ncr5380_softc *ncr_sc; 527 { 528 register u_char csr = *ncr_sc->sci_csr; 529 register u_char bus_csr = *ncr_sc->sci_bus_csr; 530 531 if (((csr & ~(SCI_CSR_PHASE_MATCH | SCI_CSR_ATN)) == SCI_CSR_INT) && 532 ((bus_csr & ~(SCI_BUS_MSG | SCI_BUS_CD | SCI_BUS_IO | SCI_BUS_DBP)) == SCI_BUS_SEL)) { 533 if (csr & SCI_BUS_IO) 534 printf("%s: reselect\n", ncr_sc->sc_dev.dv_xname); 535 else 536 printf("%s: select\n", ncr_sc->sc_dev.dv_xname); 537 } else if (((csr & ~SCI_CSR_ACK) == (SCI_CSR_DONE | SCI_CSR_INT)) && 538 ((bus_csr & (SCI_BUS_RST | SCI_BUS_BSY | SCI_BUS_SEL)) == SCI_BUS_BSY)) 539 printf("%s: dma eop\n", ncr_sc->sc_dev.dv_xname); 540 else if (((csr & ~SCI_CSR_PHASE_MATCH) == SCI_CSR_INT) && 541 ((bus_csr & ~SCI_BUS_RST) == 0)) 542 printf("%s: bus reset\n", ncr_sc->sc_dev.dv_xname); 543 else if (((csr & ~(SCI_CSR_DREQ | SCI_CSR_ATN | SCI_CSR_ACK)) == (SCI_CSR_PERR | SCI_CSR_INT | SCI_CSR_PHASE_MATCH)) && 544 ((bus_csr & (SCI_BUS_RST | SCI_BUS_BSY | SCI_BUS_SEL)) == SCI_BUS_BSY)) 545 printf("%s: parity error\n", ncr_sc->sc_dev.dv_xname); 546 else if (((csr & ~SCI_CSR_ATN) == SCI_CSR_INT) && 547 ((bus_csr & (SCI_BUS_RST | SCI_BUS_BSY | SCI_BUS_REQ | SCI_BUS_SEL)) == (SCI_BUS_BSY | SCI_BUS_REQ))) 548 printf("%s: phase mismatch\n", ncr_sc->sc_dev.dv_xname); 549 else if (((csr & ~SCI_CSR_PHASE_MATCH) == (SCI_CSR_INT | SCI_CSR_DISC)) && 550 (bus_csr == 0)) 551 printf("%s: disconnect\n", ncr_sc->sc_dev.dv_xname); 552 else 553 printf("%s: unknown intr: csr=%x, bus_csr=%x\n", 554 ncr_sc->sc_dev.dv_xname, csr, bus_csr); 555 } 556 #endif 557 558 559 /*** 560 * The following code implements polled PDMA. 561 ***/ 562 563 static int 564 sbc_pdma_out(ncr_sc, phase, count, data) 565 struct ncr5380_softc *ncr_sc; 566 int phase; 567 int count; 568 u_char *data; 569 { 570 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 571 register volatile long *long_data = (long *) sc->sc_drq_addr; 572 register volatile u_char *byte_data = (u_char *) sc->sc_nodrq_addr; 573 register int len = count; 574 575 if (count < ncr_sc->sc_min_dma_len || (sc->sc_options & SBC_PDMA) == 0) 576 return ncr5380_pio_out(ncr_sc, phase, count, data); 577 578 if (sbc_wait_busy(ncr_sc) == 0) { 579 *ncr_sc->sci_mode |= SCI_MODE_DMA; 580 *ncr_sc->sci_icmd |= SCI_ICMD_DATA; 581 *ncr_sc->sci_dma_send = 0; 582 583 #define W1 *byte_data = *data++ 584 #define W4 *long_data = *((long*)data)++ 585 while (len >= 64) { 586 if (sbc_ready(ncr_sc)) 587 goto timeout; 588 W1; 589 if (sbc_ready(ncr_sc)) 590 goto timeout; 591 W1; 592 if (sbc_ready(ncr_sc)) 593 goto timeout; 594 W1; 595 if (sbc_ready(ncr_sc)) 596 goto timeout; 597 W1; 598 if (sbc_ready(ncr_sc)) 599 goto timeout; 600 W4; W4; W4; W4; 601 W4; W4; W4; W4; 602 W4; W4; W4; W4; 603 W4; W4; W4; 604 len -= 64; 605 } 606 while (len) { 607 if (sbc_ready(ncr_sc)) 608 goto timeout; 609 W1; 610 len--; 611 } 612 #undef W1 613 #undef W4 614 if (sbc_wait_dreq(ncr_sc)) 615 printf("%s: timeout waiting for DREQ.\n", 616 ncr_sc->sc_dev.dv_xname); 617 618 *byte_data = 0; 619 620 SCI_CLR_INTR(ncr_sc); 621 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 622 *ncr_sc->sci_icmd = 0; 623 } 624 return count - len; 625 626 timeout: 627 printf("%s: pdma_out: timeout len=%d count=%d\n", 628 ncr_sc->sc_dev.dv_xname, len, count); 629 if ((*ncr_sc->sci_csr & SCI_CSR_PHASE_MATCH) == 0) { 630 *ncr_sc->sci_icmd &= ~SCI_ICMD_DATA; 631 --len; 632 } 633 634 SCI_CLR_INTR(ncr_sc); 635 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 636 *ncr_sc->sci_icmd = 0; 637 return count - len; 638 } 639 640 static int 641 sbc_pdma_in(ncr_sc, phase, count, data) 642 struct ncr5380_softc *ncr_sc; 643 int phase; 644 int count; 645 u_char *data; 646 { 647 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 648 register volatile long *long_data = (long *) sc->sc_drq_addr; 649 register volatile u_char *byte_data = (u_char *) sc->sc_nodrq_addr; 650 register int len = count; 651 652 if (count < ncr_sc->sc_min_dma_len || (sc->sc_options & SBC_PDMA) == 0) 653 return ncr5380_pio_in(ncr_sc, phase, count, data); 654 655 if (sbc_wait_busy(ncr_sc) == 0) { 656 *ncr_sc->sci_mode |= SCI_MODE_DMA; 657 *ncr_sc->sci_icmd |= SCI_ICMD_DATA; 658 *ncr_sc->sci_irecv = 0; 659 660 #define R4 *((long *)data)++ = *long_data 661 #define R1 *data++ = *byte_data 662 while (len >= 1024) { 663 if (sbc_ready(ncr_sc)) 664 goto timeout; 665 R4; R4; R4; R4; R4; R4; R4; R4; 666 R4; R4; R4; R4; R4; R4; R4; R4; 667 R4; R4; R4; R4; R4; R4; R4; R4; 668 R4; R4; R4; R4; R4; R4; R4; R4; /* 128 */ 669 if (sbc_ready(ncr_sc)) 670 goto timeout; 671 R4; R4; R4; R4; R4; R4; R4; R4; 672 R4; R4; R4; R4; R4; R4; R4; R4; 673 R4; R4; R4; R4; R4; R4; R4; R4; 674 R4; R4; R4; R4; R4; R4; R4; R4; /* 256 */ 675 if (sbc_ready(ncr_sc)) 676 goto timeout; 677 R4; R4; R4; R4; R4; R4; R4; R4; 678 R4; R4; R4; R4; R4; R4; R4; R4; 679 R4; R4; R4; R4; R4; R4; R4; R4; 680 R4; R4; R4; R4; R4; R4; R4; R4; /* 384 */ 681 if (sbc_ready(ncr_sc)) 682 goto timeout; 683 R4; R4; R4; R4; R4; R4; R4; R4; 684 R4; R4; R4; R4; R4; R4; R4; R4; 685 R4; R4; R4; R4; R4; R4; R4; R4; 686 R4; R4; R4; R4; R4; R4; R4; R4; /* 512 */ 687 if (sbc_ready(ncr_sc)) 688 goto timeout; 689 R4; R4; R4; R4; R4; R4; R4; R4; 690 R4; R4; R4; R4; R4; R4; R4; R4; 691 R4; R4; R4; R4; R4; R4; R4; R4; 692 R4; R4; R4; R4; R4; R4; R4; R4; /* 640 */ 693 if (sbc_ready(ncr_sc)) 694 goto timeout; 695 R4; R4; R4; R4; R4; R4; R4; R4; 696 R4; R4; R4; R4; R4; R4; R4; R4; 697 R4; R4; R4; R4; R4; R4; R4; R4; 698 R4; R4; R4; R4; R4; R4; R4; R4; /* 768 */ 699 if (sbc_ready(ncr_sc)) 700 goto timeout; 701 R4; R4; R4; R4; R4; R4; R4; R4; 702 R4; R4; R4; R4; R4; R4; R4; R4; 703 R4; R4; R4; R4; R4; R4; R4; R4; 704 R4; R4; R4; R4; R4; R4; R4; R4; /* 896 */ 705 if (sbc_ready(ncr_sc)) 706 goto timeout; 707 R4; R4; R4; R4; R4; R4; R4; R4; 708 R4; R4; R4; R4; R4; R4; R4; R4; 709 R4; R4; R4; R4; R4; R4; R4; R4; 710 R4; R4; R4; R4; R4; R4; R4; R4; /* 1024 */ 711 len -= 1024; 712 } 713 while (len >= 128) { 714 if (sbc_ready(ncr_sc)) 715 goto timeout; 716 R4; R4; R4; R4; R4; R4; R4; R4; 717 R4; R4; R4; R4; R4; R4; R4; R4; 718 R4; R4; R4; R4; R4; R4; R4; R4; 719 R4; R4; R4; R4; R4; R4; R4; R4; /* 128 */ 720 len -= 128; 721 } 722 while (len) { 723 if (sbc_ready(ncr_sc)) 724 goto timeout; 725 R1; 726 len--; 727 } 728 #undef R4 729 #undef R1 730 SCI_CLR_INTR(ncr_sc); 731 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 732 *ncr_sc->sci_icmd = 0; 733 } 734 return count - len; 735 736 timeout: 737 printf("%s: pdma_in: timeout len=%d count=%d\n", 738 ncr_sc->sc_dev.dv_xname, len, count); 739 740 SCI_CLR_INTR(ncr_sc); 741 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 742 *ncr_sc->sci_icmd = 0; 743 return count - len; 744 } 745 746 747 /*** 748 * The following code implements interrupt-driven PDMA. 749 ***/ 750 751 /* 752 * This is the meat of the PDMA transfer. 753 * When we get here, we shove data as fast as the mac can take it. 754 * We depend on several things: 755 * * All macs after the Mac Plus that have a 5380 chip should have a general 756 * logic IC that handshakes data for blind transfers. 757 * * If the SCSI controller finishes sending/receiving data before we do, 758 * the same general logic IC will generate a /BERR for us in short order. 759 * * The fault address for said /BERR minus the base address for the 760 * transfer will be the amount of data that was actually written. 761 * 762 * We use the nofault flag and the setjmp/longjmp in locore.s so we can 763 * detect and handle the bus error for early termination of a command. 764 * This is usually caused by a disconnecting target. 765 */ 766 void 767 sbc_drq_intr(p) 768 void *p; 769 { 770 extern int *nofault, mac68k_buserr_addr; 771 register struct sbc_softc *sc = (struct sbc_softc *) p; 772 register struct ncr5380_softc *ncr_sc = (struct ncr5380_softc *) p; 773 register struct sci_req *sr = ncr_sc->sc_current; 774 register struct sbc_pdma_handle *dh = sr->sr_dma_hand; 775 label_t faultbuf; 776 volatile u_int32_t *long_drq; 777 u_int32_t *long_data; 778 volatile u_int8_t *drq; 779 u_int8_t *data; 780 register int count; 781 int dcount, resid; 782 #ifdef SBC_WRITE_HACK 783 u_int8_t tmp; 784 #endif 785 786 /* 787 * If we're not ready to xfer data, or have no more, just return. 788 */ 789 if ((*ncr_sc->sci_csr & SCI_CSR_DREQ) == 0 || dh->dh_len == 0) 790 return; 791 792 #ifdef SBC_DEBUG 793 if (sbc_debug & SBC_DB_INTR) 794 printf("%s: drq intr, dh_len=0x%x, dh_flags=0x%x\n", 795 ncr_sc->sc_dev.dv_xname, dh->dh_len, dh->dh_flags); 796 #endif 797 798 /* 799 * Setup for a possible bus error caused by SCSI controller 800 * switching out of DATA-IN/OUT before we're done with the 801 * current transfer. 802 */ 803 nofault = (int *) &faultbuf; 804 805 if (setjmp((label_t *) nofault)) { 806 nofault = (int *) 0; 807 if ((dh->dh_flags & SBC_DH_DONE) == 0) { 808 count = (( (u_long) mac68k_buserr_addr 809 - (u_long) sc->sc_drq_addr)); 810 811 if ((count < 0) || (count > dh->dh_len)) { 812 printf("%s: complete=0x%x (pending 0x%x)\n", 813 ncr_sc->sc_dev.dv_xname, count, dh->dh_len); 814 panic("something is wrong"); 815 } 816 817 dh->dh_addr += count; 818 dh->dh_len -= count; 819 } else 820 count = 0; 821 822 #ifdef SBC_DEBUG 823 if (sbc_debug & SBC_DB_INTR) 824 printf("%s: drq /berr, complete=0x%x (pending 0x%x)\n", 825 ncr_sc->sc_dev.dv_xname, count, dh->dh_len); 826 #endif 827 mac68k_buserr_addr = 0; 828 829 return; 830 } 831 832 if (dh->dh_flags & SBC_DH_OUT) { /* Data Out */ 833 #if notyet /* XXX */ 834 /* 835 * Get the source address aligned. 836 */ 837 resid = 838 count = min(dh->dh_len, 4 - (((int) dh->dh_addr) & 0x3)); 839 if (count && count < 4) { 840 drq = (volatile u_int8_t *) sc->sc_drq_addr; 841 data = (u_int8_t *) dh->dh_addr; 842 843 #define W1 *drq++ = *data++ 844 while (count) { 845 W1; count--; 846 } 847 #undef W1 848 dh->dh_addr += resid; 849 dh->dh_len -= resid; 850 } 851 852 /* 853 * Start the transfer. 854 */ 855 while (dh->dh_len) { 856 dcount = count = min(dh->dh_len, MAX_DMA_LEN); 857 long_drq = (volatile u_int32_t *) sc->sc_drq_addr; 858 long_data = (u_int32_t *) dh->dh_addr; 859 860 #define W4 *long_drq++ = *long_data++ 861 while (count >= 64) { 862 W4; W4; W4; W4; W4; W4; W4; W4; 863 W4; W4; W4; W4; W4; W4; W4; W4; /* 64 */ 864 count -= 64; 865 } 866 while (count >= 4) { 867 W4; count -= 4; 868 } 869 #undef W4 870 data = (u_int8_t *) long_data; 871 drq = (u_int8_t *) long_drq; 872 #else /* notyet */ 873 /* 874 * Start the transfer. 875 */ 876 while (dh->dh_len) { 877 dcount = count = min(dh->dh_len, MAX_DMA_LEN); 878 drq = (volatile u_int8_t *) sc->sc_drq_addr; 879 data = (u_int8_t *) dh->dh_addr; 880 #endif /* notyet */ 881 882 #define W1 *drq++ = *data++ 883 while (count) { 884 W1; count--; 885 } 886 #undef W1 887 dh->dh_len -= dcount; 888 dh->dh_addr += dcount; 889 } 890 dh->dh_flags |= SBC_DH_DONE; 891 892 #ifdef SBC_WRITE_HACK 893 /* 894 * XXX -- Read a byte from the SBC to trigger a /BERR. 895 * This seems to be necessary for us to notice that 896 * the target has disconnected. Ick. 06 jun 1996 (sr) 897 */ 898 if (dcount >= MAX_DMA_LEN) { 899 #if 0 900 while ((*ncr_sc->sci_csr & SCI_CSR_ACK) == 0) 901 ; 902 #endif 903 drq = (volatile u_int8_t *) sc->sc_drq_addr; 904 } 905 tmp = *drq; 906 #endif 907 } else { /* Data In */ 908 /* 909 * Get the dest address aligned. 910 */ 911 resid = 912 count = min(dh->dh_len, 4 - (((int) dh->dh_addr) & 0x3)); 913 if (count && count < 4) { 914 data = (u_int8_t *) dh->dh_addr; 915 drq = (volatile u_int8_t *) sc->sc_drq_addr; 916 917 #define R1 *data++ = *drq++ 918 while (count) { 919 R1; count--; 920 } 921 #undef R1 922 dh->dh_addr += resid; 923 dh->dh_len -= resid; 924 } 925 926 /* 927 * Start the transfer. 928 */ 929 while (dh->dh_len) { 930 dcount = count = min(dh->dh_len, MAX_DMA_LEN); 931 long_data = (u_int32_t *) dh->dh_addr; 932 long_drq = (volatile u_int32_t *) sc->sc_drq_addr; 933 934 #define R4 *long_data++ = *long_drq++ 935 while (count >= 64) { 936 R4; R4; R4; R4; R4; R4; R4; R4; 937 R4; R4; R4; R4; R4; R4; R4; R4; /* 64 */ 938 count -= 64; 939 } 940 while (count >= 4) { 941 R4; count -= 4; 942 } 943 #undef R4 944 data = (u_int8_t *) long_data; 945 drq = (volatile u_int8_t *) long_drq; 946 947 #define R1 *data++ = *drq++ 948 while (count) { 949 R1; count--; 950 } 951 #undef R1 952 dh->dh_len -= dcount; 953 dh->dh_addr += dcount; 954 } 955 dh->dh_flags |= SBC_DH_DONE; 956 } 957 958 /* 959 * OK. No bus error occurred above. Clear the nofault flag 960 * so we no longer short-circuit bus errors. 961 */ 962 nofault = (int *) 0; 963 964 #ifdef SBC_DEBUG 965 if (sbc_debug & (SBC_DB_REG | SBC_DB_INTR)) 966 printf("%s: drq intr complete: csr=0x%x, bus_csr=0x%x\n", 967 ncr_sc->sc_dev.dv_xname, *ncr_sc->sci_csr, 968 *ncr_sc->sci_bus_csr); 969 #endif 970 } 971 972 void 973 sbc_dma_alloc(ncr_sc) 974 struct ncr5380_softc *ncr_sc; 975 { 976 struct sbc_softc *sc = (struct sbc_softc *) ncr_sc; 977 struct sci_req *sr = ncr_sc->sc_current; 978 struct scsi_xfer *xs = sr->sr_xs; 979 struct sbc_pdma_handle *dh; 980 int i, xlen; 981 982 #ifdef DIAGNOSTIC 983 if (sr->sr_dma_hand != NULL) 984 panic("sbc_dma_alloc: already have PDMA handle"); 985 #endif 986 987 /* Polled transfers shouldn't allocate a PDMA handle. */ 988 if (sr->sr_flags & SR_IMMED) 989 return; 990 991 xlen = ncr_sc->sc_datalen; 992 993 /* Make sure our caller checked sc_min_dma_len. */ 994 if (xlen < MIN_DMA_LEN) 995 panic("sbc_dma_alloc: len=0x%x\n", xlen); 996 997 /* 998 * Find free PDMA handle. Guaranteed to find one since we 999 * have as many PDMA handles as the driver has processes. 1000 * (instances?) 1001 */ 1002 for (i = 0; i < SCI_OPENINGS; i++) { 1003 if ((sc->sc_pdma[i].dh_flags & SBC_DH_BUSY) == 0) 1004 goto found; 1005 } 1006 panic("sbc: no free PDMA handles"); 1007 found: 1008 dh = &sc->sc_pdma[i]; 1009 dh->dh_flags = SBC_DH_BUSY; 1010 dh->dh_addr = ncr_sc->sc_dataptr; 1011 dh->dh_len = xlen; 1012 1013 /* Copy the 'write' flag for convenience. */ 1014 if (xs->flags & SCSI_DATA_OUT) 1015 dh->dh_flags |= SBC_DH_OUT; 1016 1017 sr->sr_dma_hand = dh; 1018 } 1019 1020 void 1021 sbc_dma_free(ncr_sc) 1022 struct ncr5380_softc *ncr_sc; 1023 { 1024 struct sci_req *sr = ncr_sc->sc_current; 1025 struct sbc_pdma_handle *dh = sr->sr_dma_hand; 1026 1027 #ifdef DIAGNOSTIC 1028 if (sr->sr_dma_hand == NULL) 1029 panic("sbc_dma_free: no DMA handle"); 1030 #endif 1031 1032 if (ncr_sc->sc_state & NCR_DOINGDMA) 1033 panic("sbc_dma_free: free while in progress"); 1034 1035 if (dh->dh_flags & SBC_DH_BUSY) { 1036 dh->dh_flags = 0; 1037 dh->dh_addr = NULL; 1038 dh->dh_len = 0; 1039 } 1040 sr->sr_dma_hand = NULL; 1041 } 1042 1043 void 1044 sbc_dma_poll(ncr_sc) 1045 struct ncr5380_softc *ncr_sc; 1046 { 1047 struct sci_req *sr = ncr_sc->sc_current; 1048 1049 /* 1050 * We shouldn't arrive here; if SR_IMMED is set, then 1051 * dma_alloc() should have refused to allocate a handle 1052 * for the transfer. This forces the polled PDMA code 1053 * to handle the request... 1054 */ 1055 #ifdef SBC_DEBUG 1056 if (sbc_debug & SBC_DB_DMA) 1057 printf("%s: lost DRQ interrupt?\n", ncr_sc->sc_dev.dv_xname); 1058 #endif 1059 sr->sr_flags |= SR_OVERDUE; 1060 } 1061 1062 void 1063 sbc_dma_setup(ncr_sc) 1064 struct ncr5380_softc *ncr_sc; 1065 { 1066 /* Not needed; we don't have real DMA */ 1067 } 1068 1069 void 1070 sbc_dma_start(ncr_sc) 1071 struct ncr5380_softc *ncr_sc; 1072 { 1073 register struct sbc_softc *sc = (struct sbc_softc *) ncr_sc; 1074 struct sci_req *sr = ncr_sc->sc_current; 1075 struct sbc_pdma_handle *dh = sr->sr_dma_hand; 1076 1077 /* 1078 * Match bus phase, clear pending interrupts, set DMA mode, and 1079 * assert data bus (for writing only), then start the transfer. 1080 */ 1081 if (dh->dh_flags & SBC_DH_OUT) { 1082 *ncr_sc->sci_tcmd = PHASE_DATA_OUT; 1083 SCI_CLR_INTR(ncr_sc); 1084 *sc->sc_iflag = 0x80 | (V2IF_SCSIIRQ | V2IF_SCSIDRQ); 1085 *ncr_sc->sci_mode |= SCI_MODE_DMA; 1086 *ncr_sc->sci_icmd = SCI_ICMD_DATA; 1087 *ncr_sc->sci_dma_send = 0; 1088 } else { 1089 *ncr_sc->sci_tcmd = PHASE_DATA_IN; 1090 SCI_CLR_INTR(ncr_sc); 1091 *sc->sc_iflag = 0x80 | (V2IF_SCSIIRQ | V2IF_SCSIDRQ); 1092 *ncr_sc->sci_mode |= SCI_MODE_DMA; 1093 *ncr_sc->sci_icmd = 0; 1094 *ncr_sc->sci_irecv = 0; 1095 } 1096 ncr_sc->sc_state |= NCR_DOINGDMA; 1097 1098 #ifdef SBC_DEBUG 1099 if (sbc_debug & SBC_DB_DMA) 1100 printf("%s: PDMA started, va=%p, len=0x%x\n", 1101 ncr_sc->sc_dev.dv_xname, dh->dh_addr, dh->dh_len); 1102 #endif 1103 } 1104 1105 void 1106 sbc_dma_eop(ncr_sc) 1107 struct ncr5380_softc *ncr_sc; 1108 { 1109 /* Not used; the EOP pin is wired high (GMFH, pp. 389-390) */ 1110 } 1111 1112 void 1113 sbc_dma_stop(ncr_sc) 1114 struct ncr5380_softc *ncr_sc; 1115 { 1116 register struct sbc_softc *sc = (struct sbc_softc *) ncr_sc; 1117 struct sci_req *sr = ncr_sc->sc_current; 1118 struct sbc_pdma_handle *dh = sr->sr_dma_hand; 1119 register int ntrans; 1120 1121 if ((ncr_sc->sc_state & NCR_DOINGDMA) == 0) { 1122 #ifdef SBC_DEBUG 1123 if (sbc_debug & SBC_DB_DMA) 1124 printf("%s: dma_stop: DMA not running\n", 1125 ncr_sc->sc_dev.dv_xname); 1126 #endif 1127 return; 1128 } 1129 ncr_sc->sc_state &= ~NCR_DOINGDMA; 1130 1131 if ((ncr_sc->sc_state & NCR_ABORTING) == 0) { 1132 ntrans = ncr_sc->sc_datalen - dh->dh_len; 1133 1134 #ifdef SBC_DEBUG 1135 if (sbc_debug & SBC_DB_DMA) 1136 printf("%s: dma_stop: ntrans=0x%x\n", 1137 ncr_sc->sc_dev.dv_xname, ntrans); 1138 #endif 1139 1140 if (ntrans > ncr_sc->sc_datalen) 1141 panic("sbc_dma_stop: excess transfer\n"); 1142 1143 /* Adjust data pointer */ 1144 ncr_sc->sc_dataptr += ntrans; 1145 ncr_sc->sc_datalen -= ntrans; 1146 1147 /* Clear any pending interrupts. */ 1148 SCI_CLR_INTR(ncr_sc); 1149 *sc->sc_iflag = 0x80 | V2IF_SCSIIRQ; 1150 } 1151 1152 /* Put SBIC back into PIO mode. */ 1153 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 1154 *ncr_sc->sci_icmd = 0; 1155 1156 #ifdef SBC_DEBUG 1157 if (sbc_debug & SBC_DB_REG) 1158 printf("%s: dma_stop: csr=0x%x, bus_csr=0x%x\n", 1159 ncr_sc->sc_dev.dv_xname, *ncr_sc->sci_csr, 1160 *ncr_sc->sci_bus_csr); 1161 #endif 1162 } 1163
Indexes created Tue Sep 23 14:10:03 GMT 2025