sbc.c revision 1.21
1 /* $NetBSD: sbc.c,v 1.21 1997/02/28 07:47:01 scottr Exp $ */ 2 3 /* 4 * Copyright (C) 1996 Scott Reynolds. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Scott Reynolds for 17 * the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * This file contains only the machine-dependent parts of the mac68k 35 * NCR 5380 SCSI driver. (Autoconfig stuff and PDMA functions.) 36 * The machine-independent parts are in ncr5380sbc.c 37 * 38 * Supported hardware includes: 39 * Macintosh II family 5380-based controller 40 * 41 * Credits, history: 42 * 43 * Scott Reynolds wrote this module, based on work by Allen Briggs 44 * (mac68k), Gordon W. Ross and David Jones (sun3), and Leo Weppelman 45 * (atari). Thanks to Allen for supplying crucial interpretation of the 46 * NetBSD/mac68k 1.1 'ncrscsi' driver. Also, Allen, Gordon, and Jason 47 * Thorpe all helped to refine this code, and were considerable sources 48 * of moral support. 49 */ 50 51 #include <sys/types.h> 52 #include <sys/param.h> 53 #include <sys/systm.h> 54 #include <sys/kernel.h> 55 #include <sys/errno.h> 56 #include <sys/device.h> 57 #include <sys/buf.h> 58 #include <sys/proc.h> 59 #include <sys/user.h> 60 61 #include <scsi/scsi_all.h> 62 #include <scsi/scsi_debug.h> 63 #include <scsi/scsiconf.h> 64 65 #include <dev/ic/ncr5380reg.h> 66 #include <dev/ic/ncr5380var.h> 67 68 #include <machine/cpu.h> 69 #include <machine/viareg.h> 70 71 #include "sbcreg.h" 72 73 /* 74 * Transfers smaller than this are done using PIO 75 * (on assumption they're not worth PDMA overhead) 76 */ 77 #define MIN_DMA_LEN 128 78 79 /* 80 * Transfers larger than 8192 bytes need to be split up 81 * due to the size of the PDMA space. 82 */ 83 #define MAX_DMA_LEN 0x2000 84 85 /* 86 * From Guide to the Macintosh Family Hardware, pp. 137-143 87 * These are offsets from SCSIBase (see pmap_bootstrap.c) 88 */ 89 #define SBC_REG_OFS 0x10000 90 #define SBC_DMA_OFS 0x12000 91 #define SBC_HSK_OFS 0x06000 92 93 #define SBC_DMA_OFS_PB500 0x06000 94 95 #define SBC_REG_OFS_IIFX 0x08000 /* Just guessing... */ 96 #define SBC_DMA_OFS_IIFX 0x0c000 97 #define SBC_HSK_OFS_IIFX 0x0e000 98 99 #define SBC_REG_OFS_DUO2 0x00000 100 #define SBC_DMA_OFS_DUO2 0x02000 101 #define SBC_HSK_OFS_DUO2 0x04000 102 103 #ifdef SBC_DEBUG 104 # define SBC_DB_INTR 0x01 105 # define SBC_DB_DMA 0x02 106 # define SBC_DB_REG 0x04 107 # define SBC_DB_BREAK 0x08 108 109 int sbc_debug = 0 /* | SBC_DB_INTR | SBC_DB_DMA */; 110 int sbc_link_flags = 0 /* | SDEV_DB2 */; 111 112 # ifndef DDB 113 # define Debugger() printf("Debug: sbc.c:%d\n", __LINE__) 114 # endif 115 # define SBC_BREAK \ 116 do { if (sbc_debug & SBC_DB_BREAK) Debugger(); } while (0) 117 #else 118 # define SBC_BREAK 119 #endif 120 121 /* 122 * This structure is used to keep track of PDMA requests. 123 */ 124 struct sbc_pdma_handle { 125 int dh_flags; /* flags */ 126 #define SBC_DH_BUSY 0x01 /* This handle is in use */ 127 #define SBC_DH_OUT 0x02 /* PDMA data out (write) */ 128 #define SBC_DH_DONE 0x04 /* PDMA transfer is complete */ 129 u_char *dh_addr; /* data buffer */ 130 int dh_len; /* length of data buffer */ 131 }; 132 133 /* 134 * The first structure member has to be the ncr5380_softc 135 * so we can just cast to go back and forth between them. 136 */ 137 struct sbc_softc { 138 struct ncr5380_softc ncr_sc; 139 volatile struct sbc_regs *sc_regs; 140 volatile vm_offset_t sc_drq_addr; 141 volatile vm_offset_t sc_nodrq_addr; 142 volatile u_int8_t *sc_ienable; 143 volatile u_int8_t *sc_iflag; 144 int sc_options; /* options for this instance. */ 145 struct sbc_pdma_handle sc_pdma[SCI_OPENINGS]; 146 }; 147 148 /* 149 * Options. By default, SCSI interrupts and reselect are disabled. 150 * You may enable either of these features with the `flags' directive 151 * in your kernel's configuration file. 152 * 153 * Alternatively, you can patch your kernel with DDB or some other 154 * mechanism. The sc_options member of the softc is OR'd with 155 * the value in sbc_options. 156 * 157 * The options code is based on the sparc 'si' driver's version of 158 * the same. 159 */ 160 #define SBC_PDMA 0x01 /* Use PDMA for polled transfers */ 161 #define SBC_INTR 0x02 /* Allow SCSI IRQ/DRQ interrupts */ 162 #define SBC_RESELECT 0x04 /* Allow disconnect/reselect */ 163 #define SBC_OPTIONS_MASK (SBC_RESELECT|SBC_INTR|SBC_PDMA) 164 #define SBC_OPTIONS_BITS "\10\3RESELECT\2INTR\1PDMA" 165 int sbc_options = SBC_PDMA; 166 167 static int sbc_match __P((struct device *, struct cfdata *, void *)); 168 static void sbc_attach __P((struct device *, struct device *, void *)); 169 static void sbc_minphys __P((struct buf *bp)); 170 171 static int sbc_wait_busy __P((struct ncr5380_softc *)); 172 static int sbc_ready __P((struct ncr5380_softc *)); 173 static int sbc_wait_dreq __P((struct ncr5380_softc *)); 174 static int sbc_pdma_in __P((struct ncr5380_softc *, int, int, u_char *)); 175 static int sbc_pdma_out __P((struct ncr5380_softc *, int, int, u_char *)); 176 #ifdef SBC_DEBUG 177 static void decode_5380_intr __P((struct ncr5380_softc *)); 178 #endif 179 180 void sbc_intr_enable __P((struct ncr5380_softc *)); 181 void sbc_intr_disable __P((struct ncr5380_softc *)); 182 void sbc_irq_intr __P((void *)); 183 void sbc_drq_intr __P((void *)); 184 void sbc_dma_alloc __P((struct ncr5380_softc *)); 185 void sbc_dma_free __P((struct ncr5380_softc *)); 186 void sbc_dma_poll __P((struct ncr5380_softc *)); 187 void sbc_dma_setup __P((struct ncr5380_softc *)); 188 void sbc_dma_start __P((struct ncr5380_softc *)); 189 void sbc_dma_eop __P((struct ncr5380_softc *)); 190 void sbc_dma_stop __P((struct ncr5380_softc *)); 191 192 static struct scsi_adapter sbc_ops = { 193 ncr5380_scsi_cmd, /* scsi_cmd() */ 194 sbc_minphys, /* scsi_minphys() */ 195 NULL, /* open_target_lu() */ 196 NULL, /* close_target_lu() */ 197 }; 198 199 /* This is copied from julian's bt driver */ 200 /* "so we have a default dev struct for our link struct." */ 201 static struct scsi_device sbc_dev = { 202 NULL, /* Use default error handler. */ 203 NULL, /* Use default start handler. */ 204 NULL, /* Use default async handler. */ 205 NULL, /* Use default "done" routine. */ 206 }; 207 208 struct cfattach sbc_ca = { 209 sizeof(struct sbc_softc), sbc_match, sbc_attach 210 }; 211 212 struct cfdriver sbc_cd = { 213 NULL, "sbc", DV_DULL 214 }; 215 216 217 static int 218 sbc_match(parent, cf, args) 219 struct device *parent; 220 struct cfdata *cf; 221 void *args; 222 { 223 switch (current_mac_model->machineid) { 224 case MACH_MACIIFX: /* Note: the IIfx isn't (yet) supported. */ 225 break; 226 case MACH_MACPB210: 227 case MACH_MACPB230: 228 case MACH_MACPB250: 229 case MACH_MACPB270: 230 case MACH_MACPB280: 231 case MACH_MACPB280C: 232 if (cf->cf_unit == 1) 233 return 1; 234 /*FALLTHROUGH*/ 235 default: 236 if (cf->cf_unit == 0 && mac68k_machine.scsi80) 237 return 1; 238 } 239 return 0; 240 } 241 242 static void 243 sbc_attach(parent, self, args) 244 struct device *parent, *self; 245 void *args; 246 { 247 struct sbc_softc *sc = (struct sbc_softc *) self; 248 struct ncr5380_softc *ncr_sc = (struct ncr5380_softc *) sc; 249 char bits[64]; 250 extern vm_offset_t SCSIBase; 251 252 /* Pull in the options flags. */ 253 sc->sc_options = ((ncr_sc->sc_dev.dv_cfdata->cf_flags | sbc_options) 254 & SBC_OPTIONS_MASK); 255 256 /* 257 * Set up offsets to 5380 registers and GLUE I/O space, and turn 258 * off options we know we can't support on certain models. 259 */ 260 switch (current_mac_model->machineid) { 261 case MACH_MACIIFX: /* Note: the IIfx isn't (yet) supported. */ 262 sc->sc_regs = (struct sbc_regs *)(SCSIBase + SBC_REG_OFS_IIFX); 263 sc->sc_drq_addr = (vm_offset_t)(SCSIBase + SBC_HSK_OFS_IIFX); 264 sc->sc_nodrq_addr = (vm_offset_t)(SCSIBase + SBC_DMA_OFS_IIFX); 265 sc->sc_options &= ~(SBC_INTR | SBC_RESELECT); 266 break; 267 case MACH_MACPB500: 268 sc->sc_regs = (struct sbc_regs *)(SCSIBase + SBC_REG_OFS); 269 sc->sc_drq_addr = (vm_offset_t)(SCSIBase + SBC_HSK_OFS); /*??*/ 270 sc->sc_nodrq_addr = (vm_offset_t)(SCSIBase + SBC_DMA_OFS_PB500); 271 sc->sc_options &= ~(SBC_INTR | SBC_RESELECT); 272 break; 273 case MACH_MACPB210: 274 case MACH_MACPB230: 275 case MACH_MACPB250: 276 case MACH_MACPB270: 277 case MACH_MACPB280: 278 case MACH_MACPB280C: 279 if (ncr_sc->sc_dev.dv_unit == 1) { 280 sc->sc_regs = (struct sbc_regs *)(0xfee00000 + SBC_REG_OFS_DUO2); 281 sc->sc_drq_addr = (vm_offset_t)(0xfee00000 + SBC_HSK_OFS_DUO2); 282 sc->sc_nodrq_addr = (vm_offset_t)(0xfee00000 + SBC_DMA_OFS_DUO2); 283 break; 284 } 285 /*FALLTHROUGH*/ 286 default: 287 sc->sc_regs = (struct sbc_regs *)(SCSIBase + SBC_REG_OFS); 288 sc->sc_drq_addr = (vm_offset_t)(SCSIBase + SBC_HSK_OFS); 289 sc->sc_nodrq_addr = (vm_offset_t)(SCSIBase + SBC_DMA_OFS); 290 break; 291 } 292 293 /* 294 * Fill in the prototype scsi_link. 295 */ 296 ncr_sc->sc_link.channel = SCSI_CHANNEL_ONLY_ONE; 297 ncr_sc->sc_link.adapter_softc = sc; 298 ncr_sc->sc_link.adapter_target = 7; 299 ncr_sc->sc_link.adapter = &sbc_ops; 300 ncr_sc->sc_link.device = &sbc_dev; 301 302 /* 303 * Initialize fields used by the MI code 304 */ 305 ncr_sc->sci_r0 = &sc->sc_regs->sci_pr0.sci_reg; 306 ncr_sc->sci_r1 = &sc->sc_regs->sci_pr1.sci_reg; 307 ncr_sc->sci_r2 = &sc->sc_regs->sci_pr2.sci_reg; 308 ncr_sc->sci_r3 = &sc->sc_regs->sci_pr3.sci_reg; 309 ncr_sc->sci_r4 = &sc->sc_regs->sci_pr4.sci_reg; 310 ncr_sc->sci_r5 = &sc->sc_regs->sci_pr5.sci_reg; 311 ncr_sc->sci_r6 = &sc->sc_regs->sci_pr6.sci_reg; 312 ncr_sc->sci_r7 = &sc->sc_regs->sci_pr7.sci_reg; 313 314 /* 315 * MD function pointers used by the MI code. 316 */ 317 if (sc->sc_options & SBC_PDMA) { 318 ncr_sc->sc_pio_out = sbc_pdma_out; 319 ncr_sc->sc_pio_in = sbc_pdma_in; 320 } else { 321 ncr_sc->sc_pio_out = ncr5380_pio_out; 322 ncr_sc->sc_pio_in = ncr5380_pio_in; 323 } 324 ncr_sc->sc_dma_alloc = NULL; 325 ncr_sc->sc_dma_free = NULL; 326 ncr_sc->sc_dma_poll = NULL; 327 ncr_sc->sc_intr_on = NULL; 328 ncr_sc->sc_intr_off = NULL; 329 ncr_sc->sc_dma_setup = NULL; 330 ncr_sc->sc_dma_start = NULL; 331 ncr_sc->sc_dma_eop = NULL; 332 ncr_sc->sc_dma_stop = NULL; 333 ncr_sc->sc_flags = 0; 334 ncr_sc->sc_min_dma_len = MIN_DMA_LEN; 335 336 if (sc->sc_options & SBC_INTR) { 337 ncr_sc->sc_dma_alloc = sbc_dma_alloc; 338 ncr_sc->sc_dma_free = sbc_dma_free; 339 ncr_sc->sc_dma_poll = sbc_dma_poll; 340 ncr_sc->sc_dma_setup = sbc_dma_setup; 341 ncr_sc->sc_dma_start = sbc_dma_start; 342 ncr_sc->sc_dma_eop = sbc_dma_eop; 343 ncr_sc->sc_dma_stop = sbc_dma_stop; 344 via2_register_irq(VIA2_SCSIDRQ, sbc_drq_intr, ncr_sc); 345 via2_register_irq(VIA2_SCSIIRQ, sbc_irq_intr, ncr_sc); 346 } else 347 ncr_sc->sc_flags |= NCR5380_FORCE_POLLING; 348 349 if ((sc->sc_options & SBC_RESELECT) == 0) 350 ncr_sc->sc_no_disconnect = 0xff; 351 352 /* 353 * Initialize fields used only here in the MD code. 354 */ 355 if (VIA2 == VIA2OFF) { 356 sc->sc_ienable = Via1Base + VIA2 * 0x2000 + vIER; 357 sc->sc_iflag = Via1Base + VIA2 * 0x2000 + vIFR; 358 } else { 359 sc->sc_ienable = Via1Base + VIA2 * 0x2000 + rIER; 360 sc->sc_iflag = Via1Base + VIA2 * 0x2000 + rIFR; 361 } 362 363 if (sc->sc_options) 364 printf(": options=%s", bitmask_snprintf(sc->sc_options, 365 SBC_OPTIONS_BITS, bits, sizeof(bits))); 366 printf("\n"); 367 368 /* Now enable SCSI interrupts through VIA2, if appropriate */ 369 if (sc->sc_options & SBC_INTR) 370 sbc_intr_enable(ncr_sc); 371 372 #ifdef SBC_DEBUG 373 if (sbc_debug) 374 printf("%s: softc=%p regs=%p\n", ncr_sc->sc_dev.dv_xname, 375 sc, sc->sc_regs); 376 ncr_sc->sc_link.flags |= sbc_link_flags; 377 #endif 378 379 /* 380 * Initialize the SCSI controller itself. 381 */ 382 ncr5380_init(ncr_sc); 383 ncr5380_reset_scsibus(ncr_sc); 384 config_found(self, &(ncr_sc->sc_link), scsiprint); 385 } 386 387 static void 388 sbc_minphys(struct buf *bp) 389 { 390 if (bp->b_bcount > MAX_DMA_LEN) 391 bp->b_bcount = MAX_DMA_LEN; 392 return (minphys(bp)); 393 } 394 395 396 /*** 397 * General support for Mac-specific SCSI logic. 398 ***/ 399 400 /* These are used in the following inline functions. */ 401 int sbc_wait_busy_timo = 1000 * 5000; /* X2 = 10 S. */ 402 int sbc_ready_timo = 1000 * 5000; /* X2 = 10 S. */ 403 int sbc_wait_dreq_timo = 1000 * 5000; /* X2 = 10 S. */ 404 405 /* Return zero on success. */ 406 static __inline__ int 407 sbc_wait_busy(sc) 408 struct ncr5380_softc *sc; 409 { 410 register int timo = sbc_wait_busy_timo; 411 for (;;) { 412 if (SCI_BUSY(sc)) { 413 timo = 0; /* return 0 */ 414 break; 415 } 416 if (--timo < 0) 417 break; /* return -1 */ 418 delay(2); 419 } 420 return (timo); 421 } 422 423 static __inline__ int 424 sbc_ready(sc) 425 struct ncr5380_softc *sc; 426 { 427 register int timo = sbc_ready_timo; 428 429 for (;;) { 430 if ((*sc->sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) 431 == (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 432 timo = 0; 433 break; 434 } 435 if (((*sc->sci_csr & SCI_CSR_PHASE_MATCH) == 0) 436 || (SCI_BUSY(sc) == 0)) { 437 timo = -1; 438 break; 439 } 440 if (--timo < 0) 441 break; /* return -1 */ 442 delay(2); 443 } 444 return (timo); 445 } 446 447 static __inline__ int 448 sbc_wait_dreq(sc) 449 struct ncr5380_softc *sc; 450 { 451 register int timo = sbc_wait_dreq_timo; 452 453 for (;;) { 454 if ((*sc->sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) 455 == (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 456 timo = 0; 457 break; 458 } 459 if (--timo < 0) 460 break; /* return -1 */ 461 delay(2); 462 } 463 return (timo); 464 } 465 466 467 /*** 468 * Macintosh SCSI interrupt support routines. 469 ***/ 470 471 void 472 sbc_intr_enable(ncr_sc) 473 struct ncr5380_softc *ncr_sc; 474 { 475 register struct sbc_softc *sc = (struct sbc_softc *) ncr_sc; 476 int s; 477 478 s = splhigh(); 479 *sc->sc_ienable = 0x80 | (V2IF_SCSIIRQ | V2IF_SCSIDRQ); 480 splx(s); 481 } 482 483 void 484 sbc_intr_disable(ncr_sc) 485 struct ncr5380_softc *ncr_sc; 486 { 487 register struct sbc_softc *sc = (struct sbc_softc *) ncr_sc; 488 int s; 489 490 s = splhigh(); 491 *sc->sc_ienable = (V2IF_SCSIIRQ | V2IF_SCSIDRQ); 492 splx(s); 493 } 494 495 void 496 sbc_irq_intr(p) 497 void *p; 498 { 499 register struct ncr5380_softc *ncr_sc = p; 500 register int claimed = 0; 501 502 /* How we ever arrive here without IRQ set is a mystery... */ 503 if (*ncr_sc->sci_csr & SCI_CSR_INT) { 504 #ifdef SBC_DEBUG 505 if (sbc_debug & SBC_DB_INTR) 506 decode_5380_intr(ncr_sc); 507 #endif 508 claimed = ncr5380_intr(ncr_sc); 509 if (!claimed) { 510 if (((*ncr_sc->sci_csr & ~SCI_CSR_PHASE_MATCH) == SCI_CSR_INT) 511 && ((*ncr_sc->sci_bus_csr & ~SCI_BUS_RST) == 0)) 512 SCI_CLR_INTR(ncr_sc); /* RST interrupt */ 513 #ifdef SBC_DEBUG 514 else { 515 printf("%s: spurious intr\n", 516 ncr_sc->sc_dev.dv_xname); 517 SBC_BREAK; 518 } 519 #endif 520 } 521 } 522 } 523 524 #ifdef SBC_DEBUG 525 void 526 decode_5380_intr(ncr_sc) 527 struct ncr5380_softc *ncr_sc; 528 { 529 register u_char csr = *ncr_sc->sci_csr; 530 register u_char bus_csr = *ncr_sc->sci_bus_csr; 531 532 if (((csr & ~(SCI_CSR_PHASE_MATCH | SCI_CSR_ATN)) == SCI_CSR_INT) && 533 ((bus_csr & ~(SCI_BUS_MSG | SCI_BUS_CD | SCI_BUS_IO | SCI_BUS_DBP)) == SCI_BUS_SEL)) { 534 if (csr & SCI_BUS_IO) 535 printf("%s: reselect\n", ncr_sc->sc_dev.dv_xname); 536 else 537 printf("%s: select\n", ncr_sc->sc_dev.dv_xname); 538 } else if (((csr & ~SCI_CSR_ACK) == (SCI_CSR_DONE | SCI_CSR_INT)) && 539 ((bus_csr & (SCI_BUS_RST | SCI_BUS_BSY | SCI_BUS_SEL)) == SCI_BUS_BSY)) 540 printf("%s: dma eop\n", ncr_sc->sc_dev.dv_xname); 541 else if (((csr & ~SCI_CSR_PHASE_MATCH) == SCI_CSR_INT) && 542 ((bus_csr & ~SCI_BUS_RST) == 0)) 543 printf("%s: bus reset\n", ncr_sc->sc_dev.dv_xname); 544 else if (((csr & ~(SCI_CSR_DREQ | SCI_CSR_ATN | SCI_CSR_ACK)) == (SCI_CSR_PERR | SCI_CSR_INT | SCI_CSR_PHASE_MATCH)) && 545 ((bus_csr & (SCI_BUS_RST | SCI_BUS_BSY | SCI_BUS_SEL)) == SCI_BUS_BSY)) 546 printf("%s: parity error\n", ncr_sc->sc_dev.dv_xname); 547 else if (((csr & ~SCI_CSR_ATN) == SCI_CSR_INT) && 548 ((bus_csr & (SCI_BUS_RST | SCI_BUS_BSY | SCI_BUS_REQ | SCI_BUS_SEL)) == (SCI_BUS_BSY | SCI_BUS_REQ))) 549 printf("%s: phase mismatch\n", ncr_sc->sc_dev.dv_xname); 550 else if (((csr & ~SCI_CSR_PHASE_MATCH) == (SCI_CSR_INT | SCI_CSR_DISC)) && 551 (bus_csr == 0)) 552 printf("%s: disconnect\n", ncr_sc->sc_dev.dv_xname); 553 else 554 printf("%s: unknown intr: csr=%x, bus_csr=%x\n", 555 ncr_sc->sc_dev.dv_xname, csr, bus_csr); 556 } 557 #endif 558 559 560 /*** 561 * The following code implements polled PDMA. 562 ***/ 563 564 static int 565 sbc_pdma_out(ncr_sc, phase, count, data) 566 struct ncr5380_softc *ncr_sc; 567 int phase; 568 int count; 569 u_char *data; 570 { 571 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 572 register volatile long *long_data = (long *) sc->sc_drq_addr; 573 register volatile u_char *byte_data = (u_char *) sc->sc_nodrq_addr; 574 register int len = count; 575 576 if (count < ncr_sc->sc_min_dma_len || (sc->sc_options & SBC_PDMA) == 0) 577 return ncr5380_pio_out(ncr_sc, phase, count, data); 578 579 if (sbc_wait_busy(ncr_sc) == 0) { 580 *ncr_sc->sci_mode |= SCI_MODE_DMA; 581 *ncr_sc->sci_icmd |= SCI_ICMD_DATA; 582 *ncr_sc->sci_dma_send = 0; 583 584 #define W1 *byte_data = *data++ 585 #define W4 *long_data = *((long*)data)++ 586 while (len >= 64) { 587 if (sbc_ready(ncr_sc)) 588 goto timeout; 589 W1; 590 if (sbc_ready(ncr_sc)) 591 goto timeout; 592 W1; 593 if (sbc_ready(ncr_sc)) 594 goto timeout; 595 W1; 596 if (sbc_ready(ncr_sc)) 597 goto timeout; 598 W1; 599 if (sbc_ready(ncr_sc)) 600 goto timeout; 601 W4; W4; W4; W4; 602 W4; W4; W4; W4; 603 W4; W4; W4; W4; 604 W4; W4; W4; 605 len -= 64; 606 } 607 while (len) { 608 if (sbc_ready(ncr_sc)) 609 goto timeout; 610 W1; 611 len--; 612 } 613 #undef W1 614 #undef W4 615 if (sbc_wait_dreq(ncr_sc)) 616 printf("%s: timeout waiting for DREQ.\n", 617 ncr_sc->sc_dev.dv_xname); 618 619 *byte_data = 0; 620 621 SCI_CLR_INTR(ncr_sc); 622 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 623 *ncr_sc->sci_icmd = 0; 624 } 625 return count - len; 626 627 timeout: 628 printf("%s: pdma_out: timeout len=%d count=%d\n", 629 ncr_sc->sc_dev.dv_xname, len, count); 630 if ((*ncr_sc->sci_csr & SCI_CSR_PHASE_MATCH) == 0) { 631 *ncr_sc->sci_icmd &= ~SCI_ICMD_DATA; 632 --len; 633 } 634 635 SCI_CLR_INTR(ncr_sc); 636 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 637 *ncr_sc->sci_icmd = 0; 638 return count - len; 639 } 640 641 static int 642 sbc_pdma_in(ncr_sc, phase, count, data) 643 struct ncr5380_softc *ncr_sc; 644 int phase; 645 int count; 646 u_char *data; 647 { 648 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 649 register volatile long *long_data = (long *) sc->sc_drq_addr; 650 register volatile u_char *byte_data = (u_char *) sc->sc_nodrq_addr; 651 register int len = count; 652 653 if (count < ncr_sc->sc_min_dma_len || (sc->sc_options & SBC_PDMA) == 0) 654 return ncr5380_pio_in(ncr_sc, phase, count, data); 655 656 if (sbc_wait_busy(ncr_sc) == 0) { 657 *ncr_sc->sci_mode |= SCI_MODE_DMA; 658 *ncr_sc->sci_icmd |= SCI_ICMD_DATA; 659 *ncr_sc->sci_irecv = 0; 660 661 #define R4 *((long *)data)++ = *long_data 662 #define R1 *data++ = *byte_data 663 while (len >= 1024) { 664 if (sbc_ready(ncr_sc)) 665 goto timeout; 666 R4; R4; R4; R4; R4; R4; R4; R4; 667 R4; R4; R4; R4; R4; R4; R4; R4; 668 R4; R4; R4; R4; R4; R4; R4; R4; 669 R4; R4; R4; R4; R4; R4; R4; R4; /* 128 */ 670 if (sbc_ready(ncr_sc)) 671 goto timeout; 672 R4; R4; R4; R4; R4; R4; R4; R4; 673 R4; R4; R4; R4; R4; R4; R4; R4; 674 R4; R4; R4; R4; R4; R4; R4; R4; 675 R4; R4; R4; R4; R4; R4; R4; R4; /* 256 */ 676 if (sbc_ready(ncr_sc)) 677 goto timeout; 678 R4; R4; R4; R4; R4; R4; R4; R4; 679 R4; R4; R4; R4; R4; R4; R4; R4; 680 R4; R4; R4; R4; R4; R4; R4; R4; 681 R4; R4; R4; R4; R4; R4; R4; R4; /* 384 */ 682 if (sbc_ready(ncr_sc)) 683 goto timeout; 684 R4; R4; R4; R4; R4; R4; R4; R4; 685 R4; R4; R4; R4; R4; R4; R4; R4; 686 R4; R4; R4; R4; R4; R4; R4; R4; 687 R4; R4; R4; R4; R4; R4; R4; R4; /* 512 */ 688 if (sbc_ready(ncr_sc)) 689 goto timeout; 690 R4; R4; R4; R4; R4; R4; R4; R4; 691 R4; R4; R4; R4; R4; R4; R4; R4; 692 R4; R4; R4; R4; R4; R4; R4; R4; 693 R4; R4; R4; R4; R4; R4; R4; R4; /* 640 */ 694 if (sbc_ready(ncr_sc)) 695 goto timeout; 696 R4; R4; R4; R4; R4; R4; R4; R4; 697 R4; R4; R4; R4; R4; R4; R4; R4; 698 R4; R4; R4; R4; R4; R4; R4; R4; 699 R4; R4; R4; R4; R4; R4; R4; R4; /* 768 */ 700 if (sbc_ready(ncr_sc)) 701 goto timeout; 702 R4; R4; R4; R4; R4; R4; R4; R4; 703 R4; R4; R4; R4; R4; R4; R4; R4; 704 R4; R4; R4; R4; R4; R4; R4; R4; 705 R4; R4; R4; R4; R4; R4; R4; R4; /* 896 */ 706 if (sbc_ready(ncr_sc)) 707 goto timeout; 708 R4; R4; R4; R4; R4; R4; R4; R4; 709 R4; R4; R4; R4; R4; R4; R4; R4; 710 R4; R4; R4; R4; R4; R4; R4; R4; 711 R4; R4; R4; R4; R4; R4; R4; R4; /* 1024 */ 712 len -= 1024; 713 } 714 while (len >= 128) { 715 if (sbc_ready(ncr_sc)) 716 goto timeout; 717 R4; R4; R4; R4; R4; R4; R4; R4; 718 R4; R4; R4; R4; R4; R4; R4; R4; 719 R4; R4; R4; R4; R4; R4; R4; R4; 720 R4; R4; R4; R4; R4; R4; R4; R4; /* 128 */ 721 len -= 128; 722 } 723 while (len) { 724 if (sbc_ready(ncr_sc)) 725 goto timeout; 726 R1; 727 len--; 728 } 729 #undef R4 730 #undef R1 731 SCI_CLR_INTR(ncr_sc); 732 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 733 *ncr_sc->sci_icmd = 0; 734 } 735 return count - len; 736 737 timeout: 738 printf("%s: pdma_in: timeout len=%d count=%d\n", 739 ncr_sc->sc_dev.dv_xname, len, count); 740 741 SCI_CLR_INTR(ncr_sc); 742 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 743 *ncr_sc->sci_icmd = 0; 744 return count - len; 745 } 746 747 748 /*** 749 * The following code implements interrupt-driven PDMA. 750 ***/ 751 752 /* 753 * This is the meat of the PDMA transfer. 754 * When we get here, we shove data as fast as the mac can take it. 755 * We depend on several things: 756 * * All macs after the Mac Plus that have a 5380 chip should have a general 757 * logic IC that handshakes data for blind transfers. 758 * * If the SCSI controller finishes sending/receiving data before we do, 759 * the same general logic IC will generate a /BERR for us in short order. 760 * * The fault address for said /BERR minus the base address for the 761 * transfer will be the amount of data that was actually written. 762 * 763 * We use the nofault flag and the setjmp/longjmp in locore.s so we can 764 * detect and handle the bus error for early termination of a command. 765 * This is usually caused by a disconnecting target. 766 */ 767 void 768 sbc_drq_intr(p) 769 void *p; 770 { 771 extern int *nofault, mac68k_buserr_addr; 772 register struct sbc_softc *sc = (struct sbc_softc *) p; 773 register struct ncr5380_softc *ncr_sc = (struct ncr5380_softc *) p; 774 register struct sci_req *sr = ncr_sc->sc_current; 775 register struct sbc_pdma_handle *dh = sr->sr_dma_hand; 776 label_t faultbuf; 777 volatile u_int32_t *long_drq; 778 u_int32_t *long_data; 779 volatile u_int8_t *drq; 780 u_int8_t *data; 781 register int count; 782 int dcount, resid; 783 #ifdef SBC_WRITE_HACK 784 u_int8_t tmp; 785 #endif 786 787 /* 788 * If we're not ready to xfer data, or have no more, just return. 789 */ 790 if ((*ncr_sc->sci_csr & SCI_CSR_DREQ) == 0 || dh->dh_len == 0) 791 return; 792 793 #ifdef SBC_DEBUG 794 if (sbc_debug & SBC_DB_INTR) 795 printf("%s: drq intr, dh_len=0x%x, dh_flags=0x%x\n", 796 ncr_sc->sc_dev.dv_xname, dh->dh_len, dh->dh_flags); 797 #endif 798 799 /* 800 * Setup for a possible bus error caused by SCSI controller 801 * switching out of DATA-IN/OUT before we're done with the 802 * current transfer. 803 */ 804 nofault = (int *) &faultbuf; 805 806 if (setjmp((label_t *) nofault)) { 807 nofault = (int *) 0; 808 if ((dh->dh_flags & SBC_DH_DONE) == 0) { 809 count = (( (u_long) mac68k_buserr_addr 810 - (u_long) sc->sc_drq_addr)); 811 812 if ((count < 0) || (count > dh->dh_len)) { 813 printf("%s: complete=0x%x (pending 0x%x)\n", 814 ncr_sc->sc_dev.dv_xname, count, dh->dh_len); 815 panic("something is wrong"); 816 } 817 818 dh->dh_addr += count; 819 dh->dh_len -= count; 820 } else 821 count = 0; 822 823 #ifdef SBC_DEBUG 824 if (sbc_debug & SBC_DB_INTR) 825 printf("%s: drq /berr, complete=0x%x (pending 0x%x)\n", 826 ncr_sc->sc_dev.dv_xname, count, dh->dh_len); 827 #endif 828 mac68k_buserr_addr = 0; 829 830 return; 831 } 832 833 if (dh->dh_flags & SBC_DH_OUT) { /* Data Out */ 834 #if notyet /* XXX */ 835 /* 836 * Get the source address aligned. 837 */ 838 resid = 839 count = min(dh->dh_len, 4 - (((int) dh->dh_addr) & 0x3)); 840 if (count && count < 4) { 841 drq = (volatile u_int8_t *) sc->sc_drq_addr; 842 data = (u_int8_t *) dh->dh_addr; 843 844 #define W1 *drq++ = *data++ 845 while (count) { 846 W1; count--; 847 } 848 #undef W1 849 dh->dh_addr += resid; 850 dh->dh_len -= resid; 851 } 852 853 /* 854 * Start the transfer. 855 */ 856 while (dh->dh_len) { 857 dcount = count = min(dh->dh_len, MAX_DMA_LEN); 858 long_drq = (volatile u_int32_t *) sc->sc_drq_addr; 859 long_data = (u_int32_t *) dh->dh_addr; 860 861 #define W4 *long_drq++ = *long_data++ 862 while (count >= 64) { 863 W4; W4; W4; W4; W4; W4; W4; W4; 864 W4; W4; W4; W4; W4; W4; W4; W4; /* 64 */ 865 count -= 64; 866 } 867 while (count >= 4) { 868 W4; count -= 4; 869 } 870 #undef W4 871 data = (u_int8_t *) long_data; 872 drq = (u_int8_t *) long_drq; 873 #else /* notyet */ 874 /* 875 * Start the transfer. 876 */ 877 while (dh->dh_len) { 878 dcount = count = min(dh->dh_len, MAX_DMA_LEN); 879 drq = (volatile u_int8_t *) sc->sc_drq_addr; 880 data = (u_int8_t *) dh->dh_addr; 881 #endif /* notyet */ 882 883 #define W1 *drq++ = *data++ 884 while (count) { 885 W1; count--; 886 } 887 #undef W1 888 dh->dh_len -= dcount; 889 dh->dh_addr += dcount; 890 } 891 dh->dh_flags |= SBC_DH_DONE; 892 893 #ifdef SBC_WRITE_HACK 894 /* 895 * XXX -- Read a byte from the SBC to trigger a /BERR. 896 * This seems to be necessary for us to notice that 897 * the target has disconnected. Ick. 06 jun 1996 (sr) 898 */ 899 if (dcount >= MAX_DMA_LEN) { 900 #if 0 901 while ((*ncr_sc->sci_csr & SCI_CSR_ACK) == 0) 902 ; 903 #endif 904 drq = (volatile u_int8_t *) sc->sc_drq_addr; 905 } 906 tmp = *drq; 907 #endif 908 } else { /* Data In */ 909 /* 910 * Get the dest address aligned. 911 */ 912 resid = 913 count = min(dh->dh_len, 4 - (((int) dh->dh_addr) & 0x3)); 914 if (count && count < 4) { 915 data = (u_int8_t *) dh->dh_addr; 916 drq = (volatile u_int8_t *) sc->sc_drq_addr; 917 918 #define R1 *data++ = *drq++ 919 while (count) { 920 R1; count--; 921 } 922 #undef R1 923 dh->dh_addr += resid; 924 dh->dh_len -= resid; 925 } 926 927 /* 928 * Start the transfer. 929 */ 930 while (dh->dh_len) { 931 dcount = count = min(dh->dh_len, MAX_DMA_LEN); 932 long_data = (u_int32_t *) dh->dh_addr; 933 long_drq = (volatile u_int32_t *) sc->sc_drq_addr; 934 935 #define R4 *long_data++ = *long_drq++ 936 while (count >= 64) { 937 R4; R4; R4; R4; R4; R4; R4; R4; 938 R4; R4; R4; R4; R4; R4; R4; R4; /* 64 */ 939 count -= 64; 940 } 941 while (count >= 4) { 942 R4; count -= 4; 943 } 944 #undef R4 945 data = (u_int8_t *) long_data; 946 drq = (volatile u_int8_t *) long_drq; 947 948 #define R1 *data++ = *drq++ 949 while (count) { 950 R1; count--; 951 } 952 #undef R1 953 dh->dh_len -= dcount; 954 dh->dh_addr += dcount; 955 } 956 dh->dh_flags |= SBC_DH_DONE; 957 } 958 959 /* 960 * OK. No bus error occurred above. Clear the nofault flag 961 * so we no longer short-circuit bus errors. 962 */ 963 nofault = (int *) 0; 964 965 #ifdef SBC_DEBUG 966 if (sbc_debug & (SBC_DB_REG | SBC_DB_INTR)) 967 printf("%s: drq intr complete: csr=0x%x, bus_csr=0x%x\n", 968 ncr_sc->sc_dev.dv_xname, *ncr_sc->sci_csr, 969 *ncr_sc->sci_bus_csr); 970 #endif 971 } 972 973 void 974 sbc_dma_alloc(ncr_sc) 975 struct ncr5380_softc *ncr_sc; 976 { 977 struct sbc_softc *sc = (struct sbc_softc *) ncr_sc; 978 struct sci_req *sr = ncr_sc->sc_current; 979 struct scsi_xfer *xs = sr->sr_xs; 980 struct sbc_pdma_handle *dh; 981 int i, xlen; 982 983 #ifdef DIAGNOSTIC 984 if (sr->sr_dma_hand != NULL) 985 panic("sbc_dma_alloc: already have PDMA handle"); 986 #endif 987 988 /* Polled transfers shouldn't allocate a PDMA handle. */ 989 if (sr->sr_flags & SR_IMMED) 990 return; 991 992 xlen = ncr_sc->sc_datalen; 993 994 /* Make sure our caller checked sc_min_dma_len. */ 995 if (xlen < MIN_DMA_LEN) 996 panic("sbc_dma_alloc: len=0x%x\n", xlen); 997 998 /* 999 * Find free PDMA handle. Guaranteed to find one since we 1000 * have as many PDMA handles as the driver has processes. 1001 * (instances?) 1002 */ 1003 for (i = 0; i < SCI_OPENINGS; i++) { 1004 if ((sc->sc_pdma[i].dh_flags & SBC_DH_BUSY) == 0) 1005 goto found; 1006 } 1007 panic("sbc: no free PDMA handles"); 1008 found: 1009 dh = &sc->sc_pdma[i]; 1010 dh->dh_flags = SBC_DH_BUSY; 1011 dh->dh_addr = ncr_sc->sc_dataptr; 1012 dh->dh_len = xlen; 1013 1014 /* Copy the 'write' flag for convenience. */ 1015 if (xs->flags & SCSI_DATA_OUT) 1016 dh->dh_flags |= SBC_DH_OUT; 1017 1018 sr->sr_dma_hand = dh; 1019 } 1020 1021 void 1022 sbc_dma_free(ncr_sc) 1023 struct ncr5380_softc *ncr_sc; 1024 { 1025 struct sci_req *sr = ncr_sc->sc_current; 1026 struct sbc_pdma_handle *dh = sr->sr_dma_hand; 1027 1028 #ifdef DIAGNOSTIC 1029 if (sr->sr_dma_hand == NULL) 1030 panic("sbc_dma_free: no DMA handle"); 1031 #endif 1032 1033 if (ncr_sc->sc_state & NCR_DOINGDMA) 1034 panic("sbc_dma_free: free while in progress"); 1035 1036 if (dh->dh_flags & SBC_DH_BUSY) { 1037 dh->dh_flags = 0; 1038 dh->dh_addr = NULL; 1039 dh->dh_len = 0; 1040 } 1041 sr->sr_dma_hand = NULL; 1042 } 1043 1044 void 1045 sbc_dma_poll(ncr_sc) 1046 struct ncr5380_softc *ncr_sc; 1047 { 1048 struct sci_req *sr = ncr_sc->sc_current; 1049 1050 /* 1051 * We shouldn't arrive here; if SR_IMMED is set, then 1052 * dma_alloc() should have refused to allocate a handle 1053 * for the transfer. This forces the polled PDMA code 1054 * to handle the request... 1055 */ 1056 #ifdef SBC_DEBUG 1057 if (sbc_debug & SBC_DB_DMA) 1058 printf("%s: lost DRQ interrupt?\n", ncr_sc->sc_dev.dv_xname); 1059 #endif 1060 sr->sr_flags |= SR_OVERDUE; 1061 } 1062 1063 void 1064 sbc_dma_setup(ncr_sc) 1065 struct ncr5380_softc *ncr_sc; 1066 { 1067 /* Not needed; we don't have real DMA */ 1068 } 1069 1070 void 1071 sbc_dma_start(ncr_sc) 1072 struct ncr5380_softc *ncr_sc; 1073 { 1074 register struct sbc_softc *sc = (struct sbc_softc *) ncr_sc; 1075 struct sci_req *sr = ncr_sc->sc_current; 1076 struct sbc_pdma_handle *dh = sr->sr_dma_hand; 1077 1078 /* 1079 * Match bus phase, clear pending interrupts, set DMA mode, and 1080 * assert data bus (for writing only), then start the transfer. 1081 */ 1082 if (dh->dh_flags & SBC_DH_OUT) { 1083 *ncr_sc->sci_tcmd = PHASE_DATA_OUT; 1084 SCI_CLR_INTR(ncr_sc); 1085 *sc->sc_iflag = 0x80 | (V2IF_SCSIIRQ | V2IF_SCSIDRQ); 1086 *ncr_sc->sci_mode |= SCI_MODE_DMA; 1087 *ncr_sc->sci_icmd = SCI_ICMD_DATA; 1088 *ncr_sc->sci_dma_send = 0; 1089 } else { 1090 *ncr_sc->sci_tcmd = PHASE_DATA_IN; 1091 SCI_CLR_INTR(ncr_sc); 1092 *sc->sc_iflag = 0x80 | (V2IF_SCSIIRQ | V2IF_SCSIDRQ); 1093 *ncr_sc->sci_mode |= SCI_MODE_DMA; 1094 *ncr_sc->sci_icmd = 0; 1095 *ncr_sc->sci_irecv = 0; 1096 } 1097 ncr_sc->sc_state |= NCR_DOINGDMA; 1098 1099 #ifdef SBC_DEBUG 1100 if (sbc_debug & SBC_DB_DMA) 1101 printf("%s: PDMA started, va=%p, len=0x%x\n", 1102 ncr_sc->sc_dev.dv_xname, dh->dh_addr, dh->dh_len); 1103 #endif 1104 } 1105 1106 void 1107 sbc_dma_eop(ncr_sc) 1108 struct ncr5380_softc *ncr_sc; 1109 { 1110 /* Not used; the EOP pin is wired high (GMFH, pp. 389-390) */ 1111 } 1112 1113 void 1114 sbc_dma_stop(ncr_sc) 1115 struct ncr5380_softc *ncr_sc; 1116 { 1117 register struct sbc_softc *sc = (struct sbc_softc *) ncr_sc; 1118 struct sci_req *sr = ncr_sc->sc_current; 1119 struct sbc_pdma_handle *dh = sr->sr_dma_hand; 1120 register int ntrans; 1121 1122 if ((ncr_sc->sc_state & NCR_DOINGDMA) == 0) { 1123 #ifdef SBC_DEBUG 1124 if (sbc_debug & SBC_DB_DMA) 1125 printf("%s: dma_stop: DMA not running\n", 1126 ncr_sc->sc_dev.dv_xname); 1127 #endif 1128 return; 1129 } 1130 ncr_sc->sc_state &= ~NCR_DOINGDMA; 1131 1132 if ((ncr_sc->sc_state & NCR_ABORTING) == 0) { 1133 ntrans = ncr_sc->sc_datalen - dh->dh_len; 1134 1135 #ifdef SBC_DEBUG 1136 if (sbc_debug & SBC_DB_DMA) 1137 printf("%s: dma_stop: ntrans=0x%x\n", 1138 ncr_sc->sc_dev.dv_xname, ntrans); 1139 #endif 1140 1141 if (ntrans > ncr_sc->sc_datalen) 1142 panic("sbc_dma_stop: excess transfer\n"); 1143 1144 /* Adjust data pointer */ 1145 ncr_sc->sc_dataptr += ntrans; 1146 ncr_sc->sc_datalen -= ntrans; 1147 1148 /* Clear any pending interrupts. */ 1149 SCI_CLR_INTR(ncr_sc); 1150 *sc->sc_iflag = 0x80 | V2IF_SCSIIRQ; 1151 } 1152 1153 /* Put SBIC back into PIO mode. */ 1154 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 1155 *ncr_sc->sci_icmd = 0; 1156 1157 #ifdef SBC_DEBUG 1158 if (sbc_debug & SBC_DB_REG) 1159 printf("%s: dma_stop: csr=0x%x, bus_csr=0x%x\n", 1160 ncr_sc->sc_dev.dv_xname, *ncr_sc->sci_csr, 1161 *ncr_sc->sci_bus_csr); 1162 #endif 1163 } 1164
Indexes created Thu Oct 02 14:10:14 GMT 2025