sbc.c revision 1.22
1 /* $NetBSD: sbc.c,v 1.22 1997/03/01 20:18:58 scottr Exp $ */ 2 3 /* 4 * Copyright (C) 1996 Scott Reynolds. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Scott Reynolds for 17 * the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * This file contains only the machine-dependent parts of the mac68k 35 * NCR 5380 SCSI driver. (Autoconfig stuff and PDMA functions.) 36 * The machine-independent parts are in ncr5380sbc.c 37 * 38 * Supported hardware includes: 39 * Macintosh II family 5380-based controller 40 * 41 * Credits, history: 42 * 43 * Scott Reynolds wrote this module, based on work by Allen Briggs 44 * (mac68k), Gordon W. Ross and David Jones (sun3), and Leo Weppelman 45 * (atari). Thanks to Allen for supplying crucial interpretation of the 46 * NetBSD/mac68k 1.1 'ncrscsi' driver. Also, Allen, Gordon, and Jason 47 * Thorpe all helped to refine this code, and were considerable sources 48 * of moral support. 49 */ 50 51 #include <sys/types.h> 52 #include <sys/param.h> 53 #include <sys/systm.h> 54 #include <sys/kernel.h> 55 #include <sys/errno.h> 56 #include <sys/device.h> 57 #include <sys/buf.h> 58 #include <sys/proc.h> 59 #include <sys/user.h> 60 61 #include <scsi/scsi_all.h> 62 #include <scsi/scsi_debug.h> 63 #include <scsi/scsiconf.h> 64 65 #include <dev/ic/ncr5380reg.h> 66 #include <dev/ic/ncr5380var.h> 67 68 #include <machine/cpu.h> 69 #include <machine/viareg.h> 70 71 #include "sbcreg.h" 72 #include "sbcvar.h" 73 74 int sbc_debug = 0 /* | SBC_DB_INTR | SBC_DB_DMA */; 75 int sbc_link_flags = 0 /* | SDEV_DB2 */; 76 int sbc_options = SBC_PDMA; 77 78 static void sbc_minphys __P((struct buf *bp)); 79 80 struct scsi_adapter sbc_ops = { 81 ncr5380_scsi_cmd, /* scsi_cmd() */ 82 sbc_minphys, /* scsi_minphys() */ 83 NULL, /* open_target_lu() */ 84 NULL, /* close_target_lu() */ 85 }; 86 87 /* This is copied from julian's bt driver */ 88 /* "so we have a default dev struct for our link struct." */ 89 struct scsi_device sbc_dev = { 90 NULL, /* Use default error handler. */ 91 NULL, /* Use default start handler. */ 92 NULL, /* Use default async handler. */ 93 NULL, /* Use default "done" routine. */ 94 }; 95 96 struct cfdriver sbc_cd = { 97 NULL, "sbc", DV_DULL 98 }; 99 100 static int sbc_wait_busy __P((struct ncr5380_softc *)); 101 static int sbc_ready __P((struct ncr5380_softc *)); 102 static int sbc_wait_dreq __P((struct ncr5380_softc *)); 103 104 static void 105 sbc_minphys(struct buf *bp) 106 { 107 if (bp->b_bcount > MAX_DMA_LEN) 108 bp->b_bcount = MAX_DMA_LEN; 109 return (minphys(bp)); 110 } 111 112 113 /*** 114 * General support for Mac-specific SCSI logic. 115 ***/ 116 117 /* These are used in the following inline functions. */ 118 int sbc_wait_busy_timo = 1000 * 5000; /* X2 = 10 S. */ 119 int sbc_ready_timo = 1000 * 5000; /* X2 = 10 S. */ 120 int sbc_wait_dreq_timo = 1000 * 5000; /* X2 = 10 S. */ 121 122 /* Return zero on success. */ 123 static __inline__ int 124 sbc_wait_busy(sc) 125 struct ncr5380_softc *sc; 126 { 127 register int timo = sbc_wait_busy_timo; 128 for (;;) { 129 if (SCI_BUSY(sc)) { 130 timo = 0; /* return 0 */ 131 break; 132 } 133 if (--timo < 0) 134 break; /* return -1 */ 135 delay(2); 136 } 137 return (timo); 138 } 139 140 static __inline__ int 141 sbc_ready(sc) 142 struct ncr5380_softc *sc; 143 { 144 register int timo = sbc_ready_timo; 145 146 for (;;) { 147 if ((*sc->sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) 148 == (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 149 timo = 0; 150 break; 151 } 152 if (((*sc->sci_csr & SCI_CSR_PHASE_MATCH) == 0) 153 || (SCI_BUSY(sc) == 0)) { 154 timo = -1; 155 break; 156 } 157 if (--timo < 0) 158 break; /* return -1 */ 159 delay(2); 160 } 161 return (timo); 162 } 163 164 static __inline__ int 165 sbc_wait_dreq(sc) 166 struct ncr5380_softc *sc; 167 { 168 register int timo = sbc_wait_dreq_timo; 169 170 for (;;) { 171 if ((*sc->sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) 172 == (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 173 timo = 0; 174 break; 175 } 176 if (--timo < 0) 177 break; /* return -1 */ 178 delay(2); 179 } 180 return (timo); 181 } 182 183 void 184 sbc_irq_intr(p) 185 void *p; 186 { 187 register struct ncr5380_softc *ncr_sc = p; 188 register int claimed = 0; 189 190 /* How we ever arrive here without IRQ set is a mystery... */ 191 if (*ncr_sc->sci_csr & SCI_CSR_INT) { 192 #ifdef SBC_DEBUG 193 if (sbc_debug & SBC_DB_INTR) 194 decode_5380_intr(ncr_sc); 195 #endif 196 claimed = ncr5380_intr(ncr_sc); 197 if (!claimed) { 198 if (((*ncr_sc->sci_csr & ~SCI_CSR_PHASE_MATCH) == SCI_CSR_INT) 199 && ((*ncr_sc->sci_bus_csr & ~SCI_BUS_RST) == 0)) 200 SCI_CLR_INTR(ncr_sc); /* RST interrupt */ 201 #ifdef SBC_DEBUG 202 else { 203 printf("%s: spurious intr\n", 204 ncr_sc->sc_dev.dv_xname); 205 SBC_BREAK; 206 } 207 #endif 208 } 209 } 210 } 211 212 #ifdef SBC_DEBUG 213 void 214 decode_5380_intr(ncr_sc) 215 struct ncr5380_softc *ncr_sc; 216 { 217 register u_char csr = *ncr_sc->sci_csr; 218 register u_char bus_csr = *ncr_sc->sci_bus_csr; 219 220 if (((csr & ~(SCI_CSR_PHASE_MATCH | SCI_CSR_ATN)) == SCI_CSR_INT) && 221 ((bus_csr & ~(SCI_BUS_MSG | SCI_BUS_CD | SCI_BUS_IO | SCI_BUS_DBP)) == SCI_BUS_SEL)) { 222 if (csr & SCI_BUS_IO) 223 printf("%s: reselect\n", ncr_sc->sc_dev.dv_xname); 224 else 225 printf("%s: select\n", ncr_sc->sc_dev.dv_xname); 226 } else if (((csr & ~SCI_CSR_ACK) == (SCI_CSR_DONE | SCI_CSR_INT)) && 227 ((bus_csr & (SCI_BUS_RST | SCI_BUS_BSY | SCI_BUS_SEL)) == SCI_BUS_BSY)) 228 printf("%s: dma eop\n", ncr_sc->sc_dev.dv_xname); 229 else if (((csr & ~SCI_CSR_PHASE_MATCH) == SCI_CSR_INT) && 230 ((bus_csr & ~SCI_BUS_RST) == 0)) 231 printf("%s: bus reset\n", ncr_sc->sc_dev.dv_xname); 232 else if (((csr & ~(SCI_CSR_DREQ | SCI_CSR_ATN | SCI_CSR_ACK)) == (SCI_CSR_PERR | SCI_CSR_INT | SCI_CSR_PHASE_MATCH)) && 233 ((bus_csr & (SCI_BUS_RST | SCI_BUS_BSY | SCI_BUS_SEL)) == SCI_BUS_BSY)) 234 printf("%s: parity error\n", ncr_sc->sc_dev.dv_xname); 235 else if (((csr & ~SCI_CSR_ATN) == SCI_CSR_INT) && 236 ((bus_csr & (SCI_BUS_RST | SCI_BUS_BSY | SCI_BUS_REQ | SCI_BUS_SEL)) == (SCI_BUS_BSY | SCI_BUS_REQ))) 237 printf("%s: phase mismatch\n", ncr_sc->sc_dev.dv_xname); 238 else if (((csr & ~SCI_CSR_PHASE_MATCH) == (SCI_CSR_INT | SCI_CSR_DISC)) && 239 (bus_csr == 0)) 240 printf("%s: disconnect\n", ncr_sc->sc_dev.dv_xname); 241 else 242 printf("%s: unknown intr: csr=%x, bus_csr=%x\n", 243 ncr_sc->sc_dev.dv_xname, csr, bus_csr); 244 } 245 #endif 246 247 248 /*** 249 * The following code implements polled PDMA. 250 ***/ 251 252 int 253 sbc_pdma_out(ncr_sc, phase, count, data) 254 struct ncr5380_softc *ncr_sc; 255 int phase; 256 int count; 257 u_char *data; 258 { 259 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 260 register volatile long *long_data = (long *) sc->sc_drq_addr; 261 register volatile u_char *byte_data = (u_char *) sc->sc_nodrq_addr; 262 register int len = count; 263 264 if (count < ncr_sc->sc_min_dma_len || (sc->sc_options & SBC_PDMA) == 0) 265 return ncr5380_pio_out(ncr_sc, phase, count, data); 266 267 if (sbc_wait_busy(ncr_sc) == 0) { 268 *ncr_sc->sci_mode |= SCI_MODE_DMA; 269 *ncr_sc->sci_icmd |= SCI_ICMD_DATA; 270 *ncr_sc->sci_dma_send = 0; 271 272 #define W1 *byte_data = *data++ 273 #define W4 *long_data = *((long*)data)++ 274 while (len >= 64) { 275 if (sbc_ready(ncr_sc)) 276 goto timeout; 277 W1; 278 if (sbc_ready(ncr_sc)) 279 goto timeout; 280 W1; 281 if (sbc_ready(ncr_sc)) 282 goto timeout; 283 W1; 284 if (sbc_ready(ncr_sc)) 285 goto timeout; 286 W1; 287 if (sbc_ready(ncr_sc)) 288 goto timeout; 289 W4; W4; W4; W4; 290 W4; W4; W4; W4; 291 W4; W4; W4; W4; 292 W4; W4; W4; 293 len -= 64; 294 } 295 while (len) { 296 if (sbc_ready(ncr_sc)) 297 goto timeout; 298 W1; 299 len--; 300 } 301 #undef W1 302 #undef W4 303 if (sbc_wait_dreq(ncr_sc)) 304 printf("%s: timeout waiting for DREQ.\n", 305 ncr_sc->sc_dev.dv_xname); 306 307 *byte_data = 0; 308 309 SCI_CLR_INTR(ncr_sc); 310 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 311 *ncr_sc->sci_icmd = 0; 312 } 313 return count - len; 314 315 timeout: 316 printf("%s: pdma_out: timeout len=%d count=%d\n", 317 ncr_sc->sc_dev.dv_xname, len, count); 318 if ((*ncr_sc->sci_csr & SCI_CSR_PHASE_MATCH) == 0) { 319 *ncr_sc->sci_icmd &= ~SCI_ICMD_DATA; 320 --len; 321 } 322 323 SCI_CLR_INTR(ncr_sc); 324 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 325 *ncr_sc->sci_icmd = 0; 326 return count - len; 327 } 328 329 int 330 sbc_pdma_in(ncr_sc, phase, count, data) 331 struct ncr5380_softc *ncr_sc; 332 int phase; 333 int count; 334 u_char *data; 335 { 336 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 337 register volatile long *long_data = (long *) sc->sc_drq_addr; 338 register volatile u_char *byte_data = (u_char *) sc->sc_nodrq_addr; 339 register int len = count; 340 341 if (count < ncr_sc->sc_min_dma_len || (sc->sc_options & SBC_PDMA) == 0) 342 return ncr5380_pio_in(ncr_sc, phase, count, data); 343 344 if (sbc_wait_busy(ncr_sc) == 0) { 345 *ncr_sc->sci_mode |= SCI_MODE_DMA; 346 *ncr_sc->sci_icmd |= SCI_ICMD_DATA; 347 *ncr_sc->sci_irecv = 0; 348 349 #define R4 *((long *)data)++ = *long_data 350 #define R1 *data++ = *byte_data 351 while (len >= 1024) { 352 if (sbc_ready(ncr_sc)) 353 goto timeout; 354 R4; R4; R4; R4; R4; R4; R4; R4; 355 R4; R4; R4; R4; R4; R4; R4; R4; 356 R4; R4; R4; R4; R4; R4; R4; R4; 357 R4; R4; R4; R4; R4; R4; R4; R4; /* 128 */ 358 if (sbc_ready(ncr_sc)) 359 goto timeout; 360 R4; R4; R4; R4; R4; R4; R4; R4; 361 R4; R4; R4; R4; R4; R4; R4; R4; 362 R4; R4; R4; R4; R4; R4; R4; R4; 363 R4; R4; R4; R4; R4; R4; R4; R4; /* 256 */ 364 if (sbc_ready(ncr_sc)) 365 goto timeout; 366 R4; R4; R4; R4; R4; R4; R4; R4; 367 R4; R4; R4; R4; R4; R4; R4; R4; 368 R4; R4; R4; R4; R4; R4; R4; R4; 369 R4; R4; R4; R4; R4; R4; R4; R4; /* 384 */ 370 if (sbc_ready(ncr_sc)) 371 goto timeout; 372 R4; R4; R4; R4; R4; R4; R4; R4; 373 R4; R4; R4; R4; R4; R4; R4; R4; 374 R4; R4; R4; R4; R4; R4; R4; R4; 375 R4; R4; R4; R4; R4; R4; R4; R4; /* 512 */ 376 if (sbc_ready(ncr_sc)) 377 goto timeout; 378 R4; R4; R4; R4; R4; R4; R4; R4; 379 R4; R4; R4; R4; R4; R4; R4; R4; 380 R4; R4; R4; R4; R4; R4; R4; R4; 381 R4; R4; R4; R4; R4; R4; R4; R4; /* 640 */ 382 if (sbc_ready(ncr_sc)) 383 goto timeout; 384 R4; R4; R4; R4; R4; R4; R4; R4; 385 R4; R4; R4; R4; R4; R4; R4; R4; 386 R4; R4; R4; R4; R4; R4; R4; R4; 387 R4; R4; R4; R4; R4; R4; R4; R4; /* 768 */ 388 if (sbc_ready(ncr_sc)) 389 goto timeout; 390 R4; R4; R4; R4; R4; R4; R4; R4; 391 R4; R4; R4; R4; R4; R4; R4; R4; 392 R4; R4; R4; R4; R4; R4; R4; R4; 393 R4; R4; R4; R4; R4; R4; R4; R4; /* 896 */ 394 if (sbc_ready(ncr_sc)) 395 goto timeout; 396 R4; R4; R4; R4; R4; R4; R4; R4; 397 R4; R4; R4; R4; R4; R4; R4; R4; 398 R4; R4; R4; R4; R4; R4; R4; R4; 399 R4; R4; R4; R4; R4; R4; R4; R4; /* 1024 */ 400 len -= 1024; 401 } 402 while (len >= 128) { 403 if (sbc_ready(ncr_sc)) 404 goto timeout; 405 R4; R4; R4; R4; R4; R4; R4; R4; 406 R4; R4; R4; R4; R4; R4; R4; R4; 407 R4; R4; R4; R4; R4; R4; R4; R4; 408 R4; R4; R4; R4; R4; R4; R4; R4; /* 128 */ 409 len -= 128; 410 } 411 while (len) { 412 if (sbc_ready(ncr_sc)) 413 goto timeout; 414 R1; 415 len--; 416 } 417 #undef R4 418 #undef R1 419 SCI_CLR_INTR(ncr_sc); 420 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 421 *ncr_sc->sci_icmd = 0; 422 } 423 return count - len; 424 425 timeout: 426 printf("%s: pdma_in: timeout len=%d count=%d\n", 427 ncr_sc->sc_dev.dv_xname, len, count); 428 429 SCI_CLR_INTR(ncr_sc); 430 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 431 *ncr_sc->sci_icmd = 0; 432 return count - len; 433 } 434 435 436 /*** 437 * The following code implements interrupt-driven PDMA. 438 ***/ 439 440 /* 441 * This is the meat of the PDMA transfer. 442 * When we get here, we shove data as fast as the mac can take it. 443 * We depend on several things: 444 * * All macs after the Mac Plus that have a 5380 chip should have a general 445 * logic IC that handshakes data for blind transfers. 446 * * If the SCSI controller finishes sending/receiving data before we do, 447 * the same general logic IC will generate a /BERR for us in short order. 448 * * The fault address for said /BERR minus the base address for the 449 * transfer will be the amount of data that was actually written. 450 * 451 * We use the nofault flag and the setjmp/longjmp in locore.s so we can 452 * detect and handle the bus error for early termination of a command. 453 * This is usually caused by a disconnecting target. 454 */ 455 void 456 sbc_drq_intr(p) 457 void *p; 458 { 459 extern int *nofault, mac68k_buserr_addr; 460 register struct sbc_softc *sc = (struct sbc_softc *) p; 461 register struct ncr5380_softc *ncr_sc = (struct ncr5380_softc *) p; 462 register struct sci_req *sr = ncr_sc->sc_current; 463 register struct sbc_pdma_handle *dh = sr->sr_dma_hand; 464 label_t faultbuf; 465 volatile u_int32_t *long_drq; 466 u_int32_t *long_data; 467 volatile u_int8_t *drq; 468 u_int8_t *data; 469 register int count; 470 int dcount, resid; 471 #ifdef SBC_WRITE_HACK 472 u_int8_t tmp; 473 #endif 474 475 /* 476 * If we're not ready to xfer data, or have no more, just return. 477 */ 478 if ((*ncr_sc->sci_csr & SCI_CSR_DREQ) == 0 || dh->dh_len == 0) 479 return; 480 481 #ifdef SBC_DEBUG 482 if (sbc_debug & SBC_DB_INTR) 483 printf("%s: drq intr, dh_len=0x%x, dh_flags=0x%x\n", 484 ncr_sc->sc_dev.dv_xname, dh->dh_len, dh->dh_flags); 485 #endif 486 487 /* 488 * Setup for a possible bus error caused by SCSI controller 489 * switching out of DATA-IN/OUT before we're done with the 490 * current transfer. 491 */ 492 nofault = (int *) &faultbuf; 493 494 if (setjmp((label_t *) nofault)) { 495 nofault = (int *) 0; 496 if ((dh->dh_flags & SBC_DH_DONE) == 0) { 497 count = (( (u_long) mac68k_buserr_addr 498 - (u_long) sc->sc_drq_addr)); 499 500 if ((count < 0) || (count > dh->dh_len)) { 501 printf("%s: complete=0x%x (pending 0x%x)\n", 502 ncr_sc->sc_dev.dv_xname, count, dh->dh_len); 503 panic("something is wrong"); 504 } 505 506 dh->dh_addr += count; 507 dh->dh_len -= count; 508 } else 509 count = 0; 510 511 #ifdef SBC_DEBUG 512 if (sbc_debug & SBC_DB_INTR) 513 printf("%s: drq /berr, complete=0x%x (pending 0x%x)\n", 514 ncr_sc->sc_dev.dv_xname, count, dh->dh_len); 515 #endif 516 mac68k_buserr_addr = 0; 517 518 return; 519 } 520 521 if (dh->dh_flags & SBC_DH_OUT) { /* Data Out */ 522 #if notyet /* XXX */ 523 /* 524 * Get the source address aligned. 525 */ 526 resid = 527 count = min(dh->dh_len, 4 - (((int) dh->dh_addr) & 0x3)); 528 if (count && count < 4) { 529 drq = (volatile u_int8_t *) sc->sc_drq_addr; 530 data = (u_int8_t *) dh->dh_addr; 531 532 #define W1 *drq++ = *data++ 533 while (count) { 534 W1; count--; 535 } 536 #undef W1 537 dh->dh_addr += resid; 538 dh->dh_len -= resid; 539 } 540 541 /* 542 * Start the transfer. 543 */ 544 while (dh->dh_len) { 545 dcount = count = min(dh->dh_len, MAX_DMA_LEN); 546 long_drq = (volatile u_int32_t *) sc->sc_drq_addr; 547 long_data = (u_int32_t *) dh->dh_addr; 548 549 #define W4 *long_drq++ = *long_data++ 550 while (count >= 64) { 551 W4; W4; W4; W4; W4; W4; W4; W4; 552 W4; W4; W4; W4; W4; W4; W4; W4; /* 64 */ 553 count -= 64; 554 } 555 while (count >= 4) { 556 W4; count -= 4; 557 } 558 #undef W4 559 data = (u_int8_t *) long_data; 560 drq = (u_int8_t *) long_drq; 561 #else /* notyet */ 562 /* 563 * Start the transfer. 564 */ 565 while (dh->dh_len) { 566 dcount = count = min(dh->dh_len, MAX_DMA_LEN); 567 drq = (volatile u_int8_t *) sc->sc_drq_addr; 568 data = (u_int8_t *) dh->dh_addr; 569 #endif /* notyet */ 570 571 #define W1 *drq++ = *data++ 572 while (count) { 573 W1; count--; 574 } 575 #undef W1 576 dh->dh_len -= dcount; 577 dh->dh_addr += dcount; 578 } 579 dh->dh_flags |= SBC_DH_DONE; 580 581 #ifdef SBC_WRITE_HACK 582 /* 583 * XXX -- Read a byte from the SBC to trigger a /BERR. 584 * This seems to be necessary for us to notice that 585 * the target has disconnected. Ick. 06 jun 1996 (sr) 586 */ 587 if (dcount >= MAX_DMA_LEN) { 588 #if 0 589 while ((*ncr_sc->sci_csr & SCI_CSR_ACK) == 0) 590 ; 591 #endif 592 drq = (volatile u_int8_t *) sc->sc_drq_addr; 593 } 594 tmp = *drq; 595 #endif 596 } else { /* Data In */ 597 /* 598 * Get the dest address aligned. 599 */ 600 resid = 601 count = min(dh->dh_len, 4 - (((int) dh->dh_addr) & 0x3)); 602 if (count && count < 4) { 603 data = (u_int8_t *) dh->dh_addr; 604 drq = (volatile u_int8_t *) sc->sc_drq_addr; 605 606 #define R1 *data++ = *drq++ 607 while (count) { 608 R1; count--; 609 } 610 #undef R1 611 dh->dh_addr += resid; 612 dh->dh_len -= resid; 613 } 614 615 /* 616 * Start the transfer. 617 */ 618 while (dh->dh_len) { 619 dcount = count = min(dh->dh_len, MAX_DMA_LEN); 620 long_data = (u_int32_t *) dh->dh_addr; 621 long_drq = (volatile u_int32_t *) sc->sc_drq_addr; 622 623 #define R4 *long_data++ = *long_drq++ 624 while (count >= 64) { 625 R4; R4; R4; R4; R4; R4; R4; R4; 626 R4; R4; R4; R4; R4; R4; R4; R4; /* 64 */ 627 count -= 64; 628 } 629 while (count >= 4) { 630 R4; count -= 4; 631 } 632 #undef R4 633 data = (u_int8_t *) long_data; 634 drq = (volatile u_int8_t *) long_drq; 635 636 #define R1 *data++ = *drq++ 637 while (count) { 638 R1; count--; 639 } 640 #undef R1 641 dh->dh_len -= dcount; 642 dh->dh_addr += dcount; 643 } 644 dh->dh_flags |= SBC_DH_DONE; 645 } 646 647 /* 648 * OK. No bus error occurred above. Clear the nofault flag 649 * so we no longer short-circuit bus errors. 650 */ 651 nofault = (int *) 0; 652 653 #ifdef SBC_DEBUG 654 if (sbc_debug & (SBC_DB_REG | SBC_DB_INTR)) 655 printf("%s: drq intr complete: csr=0x%x, bus_csr=0x%x\n", 656 ncr_sc->sc_dev.dv_xname, *ncr_sc->sci_csr, 657 *ncr_sc->sci_bus_csr); 658 #endif 659 } 660 661 void 662 sbc_dma_alloc(ncr_sc) 663 struct ncr5380_softc *ncr_sc; 664 { 665 struct sbc_softc *sc = (struct sbc_softc *) ncr_sc; 666 struct sci_req *sr = ncr_sc->sc_current; 667 struct scsi_xfer *xs = sr->sr_xs; 668 struct sbc_pdma_handle *dh; 669 int i, xlen; 670 671 #ifdef DIAGNOSTIC 672 if (sr->sr_dma_hand != NULL) 673 panic("sbc_dma_alloc: already have PDMA handle"); 674 #endif 675 676 /* Polled transfers shouldn't allocate a PDMA handle. */ 677 if (sr->sr_flags & SR_IMMED) 678 return; 679 680 xlen = ncr_sc->sc_datalen; 681 682 /* Make sure our caller checked sc_min_dma_len. */ 683 if (xlen < MIN_DMA_LEN) 684 panic("sbc_dma_alloc: len=0x%x\n", xlen); 685 686 /* 687 * Find free PDMA handle. Guaranteed to find one since we 688 * have as many PDMA handles as the driver has processes. 689 * (instances?) 690 */ 691 for (i = 0; i < SCI_OPENINGS; i++) { 692 if ((sc->sc_pdma[i].dh_flags & SBC_DH_BUSY) == 0) 693 goto found; 694 } 695 panic("sbc: no free PDMA handles"); 696 found: 697 dh = &sc->sc_pdma[i]; 698 dh->dh_flags = SBC_DH_BUSY; 699 dh->dh_addr = ncr_sc->sc_dataptr; 700 dh->dh_len = xlen; 701 702 /* Copy the 'write' flag for convenience. */ 703 if (xs->flags & SCSI_DATA_OUT) 704 dh->dh_flags |= SBC_DH_OUT; 705 706 sr->sr_dma_hand = dh; 707 } 708 709 void 710 sbc_dma_free(ncr_sc) 711 struct ncr5380_softc *ncr_sc; 712 { 713 struct sci_req *sr = ncr_sc->sc_current; 714 struct sbc_pdma_handle *dh = sr->sr_dma_hand; 715 716 #ifdef DIAGNOSTIC 717 if (sr->sr_dma_hand == NULL) 718 panic("sbc_dma_free: no DMA handle"); 719 #endif 720 721 if (ncr_sc->sc_state & NCR_DOINGDMA) 722 panic("sbc_dma_free: free while in progress"); 723 724 if (dh->dh_flags & SBC_DH_BUSY) { 725 dh->dh_flags = 0; 726 dh->dh_addr = NULL; 727 dh->dh_len = 0; 728 } 729 sr->sr_dma_hand = NULL; 730 } 731 732 void 733 sbc_dma_poll(ncr_sc) 734 struct ncr5380_softc *ncr_sc; 735 { 736 struct sci_req *sr = ncr_sc->sc_current; 737 738 /* 739 * We shouldn't arrive here; if SR_IMMED is set, then 740 * dma_alloc() should have refused to allocate a handle 741 * for the transfer. This forces the polled PDMA code 742 * to handle the request... 743 */ 744 #ifdef SBC_DEBUG 745 if (sbc_debug & SBC_DB_DMA) 746 printf("%s: lost DRQ interrupt?\n", ncr_sc->sc_dev.dv_xname); 747 #endif 748 sr->sr_flags |= SR_OVERDUE; 749 } 750 751 void 752 sbc_dma_setup(ncr_sc) 753 struct ncr5380_softc *ncr_sc; 754 { 755 /* Not needed; we don't have real DMA */ 756 } 757 758 void 759 sbc_dma_start(ncr_sc) 760 struct ncr5380_softc *ncr_sc; 761 { 762 register struct sbc_softc *sc = (struct sbc_softc *) ncr_sc; 763 struct sci_req *sr = ncr_sc->sc_current; 764 struct sbc_pdma_handle *dh = sr->sr_dma_hand; 765 766 /* 767 * Match bus phase, clear pending interrupts, set DMA mode, and 768 * assert data bus (for writing only), then start the transfer. 769 */ 770 if (dh->dh_flags & SBC_DH_OUT) { 771 *ncr_sc->sci_tcmd = PHASE_DATA_OUT; 772 SCI_CLR_INTR(ncr_sc); 773 if (sc->sc_clrintr) 774 (*sc->sc_clrintr)(ncr_sc); 775 *ncr_sc->sci_mode |= SCI_MODE_DMA; 776 *ncr_sc->sci_icmd = SCI_ICMD_DATA; 777 *ncr_sc->sci_dma_send = 0; 778 } else { 779 *ncr_sc->sci_tcmd = PHASE_DATA_IN; 780 SCI_CLR_INTR(ncr_sc); 781 if (sc->sc_clrintr) 782 (*sc->sc_clrintr)(ncr_sc); 783 *ncr_sc->sci_mode |= SCI_MODE_DMA; 784 *ncr_sc->sci_icmd = 0; 785 *ncr_sc->sci_irecv = 0; 786 } 787 ncr_sc->sc_state |= NCR_DOINGDMA; 788 789 #ifdef SBC_DEBUG 790 if (sbc_debug & SBC_DB_DMA) 791 printf("%s: PDMA started, va=%p, len=0x%x\n", 792 ncr_sc->sc_dev.dv_xname, dh->dh_addr, dh->dh_len); 793 #endif 794 } 795 796 void 797 sbc_dma_eop(ncr_sc) 798 struct ncr5380_softc *ncr_sc; 799 { 800 /* Not used; the EOP pin is wired high (GMFH, pp. 389-390) */ 801 } 802 803 void 804 sbc_dma_stop(ncr_sc) 805 struct ncr5380_softc *ncr_sc; 806 { 807 register struct sbc_softc *sc = (struct sbc_softc *) ncr_sc; 808 struct sci_req *sr = ncr_sc->sc_current; 809 struct sbc_pdma_handle *dh = sr->sr_dma_hand; 810 register int ntrans; 811 812 if ((ncr_sc->sc_state & NCR_DOINGDMA) == 0) { 813 #ifdef SBC_DEBUG 814 if (sbc_debug & SBC_DB_DMA) 815 printf("%s: dma_stop: DMA not running\n", 816 ncr_sc->sc_dev.dv_xname); 817 #endif 818 return; 819 } 820 ncr_sc->sc_state &= ~NCR_DOINGDMA; 821 822 if ((ncr_sc->sc_state & NCR_ABORTING) == 0) { 823 ntrans = ncr_sc->sc_datalen - dh->dh_len; 824 825 #ifdef SBC_DEBUG 826 if (sbc_debug & SBC_DB_DMA) 827 printf("%s: dma_stop: ntrans=0x%x\n", 828 ncr_sc->sc_dev.dv_xname, ntrans); 829 #endif 830 831 if (ntrans > ncr_sc->sc_datalen) 832 panic("sbc_dma_stop: excess transfer\n"); 833 834 /* Adjust data pointer */ 835 ncr_sc->sc_dataptr += ntrans; 836 ncr_sc->sc_datalen -= ntrans; 837 838 /* Clear any pending interrupts. */ 839 SCI_CLR_INTR(ncr_sc); 840 if (sc->sc_clrintr) 841 (*sc->sc_clrintr)(ncr_sc); 842 } 843 844 /* Put SBIC back into PIO mode. */ 845 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 846 *ncr_sc->sci_icmd = 0; 847 848 #ifdef SBC_DEBUG 849 if (sbc_debug & SBC_DB_REG) 850 printf("%s: dma_stop: csr=0x%x, bus_csr=0x%x\n", 851 ncr_sc->sc_dev.dv_xname, *ncr_sc->sci_csr, 852 *ncr_sc->sci_bus_csr); 853 #endif 854 } 855
Indexes created Mon Sep 22 21:09:42 GMT 2025