sbc.c revision 1.23
1 /* $NetBSD: sbc.c,v 1.23 1997/04/07 05:48:35 scottr Exp $ */ 2 3 /* 4 * Copyright (C) 1996 Scott Reynolds. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Scott Reynolds for 17 * the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * This file contains only the machine-dependent parts of the mac68k 35 * NCR 5380 SCSI driver. (Autoconfig stuff and PDMA functions.) 36 * The machine-independent parts are in ncr5380sbc.c 37 * 38 * Supported hardware includes: 39 * Macintosh II family 5380-based controller 40 * 41 * Credits, history: 42 * 43 * Scott Reynolds wrote this module, based on work by Allen Briggs 44 * (mac68k), Gordon W. Ross and David Jones (sun3), and Leo Weppelman 45 * (atari). Thanks to Allen for supplying crucial interpretation of the 46 * NetBSD/mac68k 1.1 'ncrscsi' driver. Also, Allen, Gordon, and Jason 47 * Thorpe all helped to refine this code, and were considerable sources 48 * of moral support. 49 */ 50 51 #include <sys/types.h> 52 #include <sys/param.h> 53 #include <sys/systm.h> 54 #include <sys/kernel.h> 55 #include <sys/errno.h> 56 #include <sys/device.h> 57 #include <sys/buf.h> 58 #include <sys/proc.h> 59 #include <sys/user.h> 60 61 #include <scsi/scsi_all.h> 62 #include <scsi/scsi_debug.h> 63 #include <scsi/scsiconf.h> 64 65 #include <dev/ic/ncr5380reg.h> 66 #include <dev/ic/ncr5380var.h> 67 68 #include <machine/cpu.h> 69 #include <machine/viareg.h> 70 71 #include "sbcreg.h" 72 #include "sbcvar.h" 73 74 int sbc_debug = 0 /* | SBC_DB_INTR | SBC_DB_DMA */; 75 int sbc_link_flags = 0 /* | SDEV_DB2 */; 76 int sbc_options = SBC_PDMA; 77 78 static void sbc_minphys __P((struct buf *bp)); 79 80 struct scsi_adapter sbc_ops = { 81 ncr5380_scsi_cmd, /* scsi_cmd() */ 82 sbc_minphys, /* scsi_minphys() */ 83 NULL, /* open_target_lu() */ 84 NULL, /* close_target_lu() */ 85 }; 86 87 /* This is copied from julian's bt driver */ 88 /* "so we have a default dev struct for our link struct." */ 89 struct scsi_device sbc_dev = { 90 NULL, /* Use default error handler. */ 91 NULL, /* Use default start handler. */ 92 NULL, /* Use default async handler. */ 93 NULL, /* Use default "done" routine. */ 94 }; 95 96 struct cfdriver sbc_cd = { 97 NULL, "sbc", DV_DULL 98 }; 99 100 static int sbc_ready __P((struct ncr5380_softc *)); 101 static void sbc_wait_not_req __P((struct ncr5380_softc *)); 102 103 static void 104 sbc_minphys(struct buf *bp) 105 { 106 if (bp->b_bcount > MAX_DMA_LEN) 107 bp->b_bcount = MAX_DMA_LEN; 108 return (minphys(bp)); 109 } 110 111 112 /*** 113 * General support for Mac-specific SCSI logic. 114 ***/ 115 116 void 117 sbc_irq_intr(p) 118 void *p; 119 { 120 struct ncr5380_softc *ncr_sc = p; 121 int claimed = 0; 122 123 /* How we ever arrive here without IRQ set is a mystery... */ 124 if (*ncr_sc->sci_csr & SCI_CSR_INT) { 125 #ifdef SBC_DEBUG 126 if (sbc_debug & SBC_DB_INTR) 127 decode_5380_intr(ncr_sc); 128 #endif 129 claimed = ncr5380_intr(ncr_sc); 130 if (!claimed) { 131 if (((*ncr_sc->sci_csr & ~SCI_CSR_PHASE_MATCH) == SCI_CSR_INT) 132 && ((*ncr_sc->sci_bus_csr & ~SCI_BUS_RST) == 0)) 133 SCI_CLR_INTR(ncr_sc); /* RST interrupt */ 134 #ifdef SBC_DEBUG 135 else { 136 printf("%s: spurious intr\n", 137 ncr_sc->sc_dev.dv_xname); 138 SBC_BREAK; 139 } 140 #endif 141 } 142 } 143 } 144 145 #ifdef SBC_DEBUG 146 void 147 decode_5380_intr(ncr_sc) 148 struct ncr5380_softc *ncr_sc; 149 { 150 u_char csr = *ncr_sc->sci_csr; 151 u_char bus_csr = *ncr_sc->sci_bus_csr; 152 153 if (((csr & ~(SCI_CSR_PHASE_MATCH | SCI_CSR_ATN)) == SCI_CSR_INT) && 154 ((bus_csr & ~(SCI_BUS_MSG | SCI_BUS_CD | SCI_BUS_IO | SCI_BUS_DBP)) == SCI_BUS_SEL)) { 155 if (csr & SCI_BUS_IO) 156 printf("%s: reselect\n", ncr_sc->sc_dev.dv_xname); 157 else 158 printf("%s: select\n", ncr_sc->sc_dev.dv_xname); 159 } else if (((csr & ~SCI_CSR_ACK) == (SCI_CSR_DONE | SCI_CSR_INT)) && 160 ((bus_csr & (SCI_BUS_RST | SCI_BUS_BSY | SCI_BUS_SEL)) == SCI_BUS_BSY)) 161 printf("%s: dma eop\n", ncr_sc->sc_dev.dv_xname); 162 else if (((csr & ~SCI_CSR_PHASE_MATCH) == SCI_CSR_INT) && 163 ((bus_csr & ~SCI_BUS_RST) == 0)) 164 printf("%s: bus reset\n", ncr_sc->sc_dev.dv_xname); 165 else if (((csr & ~(SCI_CSR_DREQ | SCI_CSR_ATN | SCI_CSR_ACK)) == (SCI_CSR_PERR | SCI_CSR_INT | SCI_CSR_PHASE_MATCH)) && 166 ((bus_csr & (SCI_BUS_RST | SCI_BUS_BSY | SCI_BUS_SEL)) == SCI_BUS_BSY)) 167 printf("%s: parity error\n", ncr_sc->sc_dev.dv_xname); 168 else if (((csr & ~SCI_CSR_ATN) == SCI_CSR_INT) && 169 ((bus_csr & (SCI_BUS_RST | SCI_BUS_BSY | SCI_BUS_REQ | SCI_BUS_SEL)) == (SCI_BUS_BSY | SCI_BUS_REQ))) 170 printf("%s: phase mismatch\n", ncr_sc->sc_dev.dv_xname); 171 else if (((csr & ~SCI_CSR_PHASE_MATCH) == (SCI_CSR_INT | SCI_CSR_DISC)) && 172 (bus_csr == 0)) 173 printf("%s: disconnect\n", ncr_sc->sc_dev.dv_xname); 174 else 175 printf("%s: unknown intr: csr=%x, bus_csr=%x\n", 176 ncr_sc->sc_dev.dv_xname, csr, bus_csr); 177 } 178 #endif 179 180 181 /*** 182 * The following code implements polled PDMA. 183 ***/ 184 185 #define TIMEOUT 5000000 /* x 2 usec = 10 sec */ 186 187 static __inline__ int 188 sbc_ready(sc) 189 struct ncr5380_softc *sc; 190 { 191 int i = TIMEOUT; 192 193 for (;;) { 194 if ((*sc->sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) == 195 (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) 196 return 1; 197 if (((*sc->sci_csr & SCI_CSR_PHASE_MATCH) == 0) || 198 (SCI_BUSY(sc) == 0)) 199 return 0; 200 if (--i < 0) 201 break; 202 delay(2); 203 } 204 205 printf("%s: ready timeout\n", sc->sc_dev.dv_xname); 206 return 0; 207 } 208 209 static __inline__ void 210 sbc_wait_not_req(sc) 211 struct ncr5380_softc *sc; 212 { 213 int i = TIMEOUT; 214 215 for (;;) { 216 if ((*sc->sci_bus_csr & SCI_BUS_REQ) == 0 || 217 (*sc->sci_csr & SCI_CSR_PHASE_MATCH) == 0 || 218 SCI_BUSY(sc) == 0) { 219 return; 220 } 221 if (--i < 0) 222 break; 223 delay(2); 224 } 225 printf("%s: pdma not_req timeout\n", sc->sc_dev.dv_xname); 226 } 227 228 int 229 sbc_pdma_in(ncr_sc, phase, datalen, data) 230 struct ncr5380_softc *ncr_sc; 231 int phase, datalen; 232 u_char *data; 233 { 234 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 235 volatile long *long_data = (long *)sc->sc_drq_addr; 236 volatile u_char *byte_data = (u_char *)sc->sc_nodrq_addr; 237 int resid, s; 238 239 s = splbio(); 240 *ncr_sc->sci_mode |= SCI_MODE_DMA; 241 *ncr_sc->sci_irecv = 0; 242 243 #define R4 *((long *)data)++ = *long_data 244 #define R1 *data++ = *byte_data 245 for (resid = datalen; resid >= 128; resid -= 128) { 246 if (sbc_ready(ncr_sc) == 0) 247 goto interrupt; 248 R4; R4; R4; R4; R4; R4; R4; R4; 249 R4; R4; R4; R4; R4; R4; R4; R4; 250 R4; R4; R4; R4; R4; R4; R4; R4; 251 R4; R4; R4; R4; R4; R4; R4; R4; 252 } 253 while (resid) { 254 if (sbc_ready(ncr_sc) == 0) 255 goto interrupt; 256 R1; 257 resid--; 258 } 259 #undef R4 260 #undef R1 261 262 sbc_wait_not_req(ncr_sc); 263 interrupt: 264 SCI_CLR_INTR(ncr_sc); 265 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 266 splx(s); 267 return datalen - resid; 268 } 269 270 int 271 sbc_pdma_out(ncr_sc, phase, datalen, data) 272 struct ncr5380_softc *ncr_sc; 273 int phase, datalen; 274 u_char *data; 275 { 276 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 277 volatile long *long_data = (long *)sc->sc_drq_addr; 278 volatile u_char *byte_data = (u_char *)sc->sc_nodrq_addr; 279 int i, s, resid; 280 u_char icmd; 281 282 s = splbio(); 283 icmd = *(ncr_sc->sci_icmd) & SCI_ICMD_RMASK; 284 *ncr_sc->sci_icmd = icmd | SCI_ICMD_DATA; 285 *ncr_sc->sci_mode |= SCI_MODE_DMA; 286 *ncr_sc->sci_dma_send = 0; 287 288 resid = datalen; 289 if (sbc_ready(ncr_sc) == 0) 290 goto interrupt; 291 292 #define W1 *byte_data = *data++ 293 #define W4 *long_data = *((long*)data)++ 294 while (resid >= 64) { 295 if (sbc_ready(ncr_sc) == 0) 296 goto interrupt; 297 W1; 298 resid--; 299 if (sbc_ready(ncr_sc) == 0) 300 goto interrupt; 301 W1; 302 resid--; 303 if (sbc_ready(ncr_sc) == 0) 304 goto interrupt; 305 W1; 306 resid--; 307 if (sbc_ready(ncr_sc) == 0) 308 goto interrupt; 309 W1; 310 resid--; 311 if (sbc_ready(ncr_sc) == 0) 312 goto interrupt; 313 W4; W4; W4; W4; 314 W4; W4; W4; W4; 315 W4; W4; W4; W4; 316 W4; W4; W4; 317 resid -= 60; 318 } 319 for (; resid; resid--) { 320 if (sbc_ready(ncr_sc) == 0) 321 goto interrupt; 322 W1; 323 } 324 #undef W1 325 #undef W4 326 327 for (i = TIMEOUT; i > 0; i--) { 328 if ((*ncr_sc->sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) 329 != SCI_CSR_DREQ) 330 break; 331 } 332 if (i != 0) 333 *byte_data = 0; 334 else 335 printf("%s: timeout waiting for final SCI_DSR_DREQ.\n", 336 ncr_sc->sc_dev.dv_xname); 337 338 sbc_wait_not_req(ncr_sc); 339 interrupt: 340 SCI_CLR_INTR(ncr_sc); 341 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 342 *ncr_sc->sci_icmd = icmd; 343 splx(s); 344 return (datalen - resid); 345 } 346 347 348 /*** 349 * The following code implements interrupt-driven PDMA. 350 ***/ 351 352 /* 353 * This is the meat of the PDMA transfer. 354 * When we get here, we shove data as fast as the mac can take it. 355 * We depend on several things: 356 * * All macs after the Mac Plus that have a 5380 chip should have a general 357 * logic IC that handshakes data for blind transfers. 358 * * If the SCSI controller finishes sending/receiving data before we do, 359 * the same general logic IC will generate a /BERR for us in short order. 360 * * The fault address for said /BERR minus the base address for the 361 * transfer will be the amount of data that was actually written. 362 * 363 * We use the nofault flag and the setjmp/longjmp in locore.s so we can 364 * detect and handle the bus error for early termination of a command. 365 * This is usually caused by a disconnecting target. 366 */ 367 void 368 sbc_drq_intr(p) 369 void *p; 370 { 371 extern int *nofault, mac68k_buserr_addr; 372 struct sbc_softc *sc = (struct sbc_softc *) p; 373 struct ncr5380_softc *ncr_sc = (struct ncr5380_softc *) p; 374 struct sci_req *sr = ncr_sc->sc_current; 375 struct sbc_pdma_handle *dh = sr->sr_dma_hand; 376 label_t faultbuf; 377 volatile u_int32_t *long_drq; 378 u_int32_t *long_data; 379 volatile u_int8_t *drq; 380 u_int8_t *data; 381 int count, dcount, resid; 382 #ifdef SBC_WRITE_HACK 383 u_int8_t tmp; 384 #endif 385 386 /* 387 * If we're not ready to xfer data, or have no more, just return. 388 */ 389 if ((*ncr_sc->sci_csr & SCI_CSR_DREQ) == 0 || dh->dh_len == 0) 390 return; 391 392 #ifdef SBC_DEBUG 393 if (sbc_debug & SBC_DB_INTR) 394 printf("%s: drq intr, dh_len=0x%x, dh_flags=0x%x\n", 395 ncr_sc->sc_dev.dv_xname, dh->dh_len, dh->dh_flags); 396 #endif 397 398 /* 399 * Setup for a possible bus error caused by SCSI controller 400 * switching out of DATA-IN/OUT before we're done with the 401 * current transfer. 402 */ 403 nofault = (int *) &faultbuf; 404 405 if (setjmp((label_t *) nofault)) { 406 nofault = (int *) 0; 407 if ((dh->dh_flags & SBC_DH_DONE) == 0) { 408 count = (( (u_long) mac68k_buserr_addr 409 - (u_long) sc->sc_drq_addr)); 410 411 if ((count < 0) || (count > dh->dh_len)) { 412 printf("%s: complete=0x%x (pending 0x%x)\n", 413 ncr_sc->sc_dev.dv_xname, count, dh->dh_len); 414 panic("something is wrong"); 415 } 416 417 dh->dh_addr += count; 418 dh->dh_len -= count; 419 } else 420 count = 0; 421 422 #ifdef SBC_DEBUG 423 if (sbc_debug & SBC_DB_INTR) 424 printf("%s: drq /berr, complete=0x%x (pending 0x%x)\n", 425 ncr_sc->sc_dev.dv_xname, count, dh->dh_len); 426 #endif 427 mac68k_buserr_addr = 0; 428 429 return; 430 } 431 432 if (dh->dh_flags & SBC_DH_OUT) { /* Data Out */ 433 #if notyet /* XXX */ 434 /* 435 * Get the source address aligned. 436 */ 437 resid = 438 count = min(dh->dh_len, 4 - (((int) dh->dh_addr) & 0x3)); 439 if (count && count < 4) { 440 drq = (volatile u_int8_t *) sc->sc_drq_addr; 441 data = (u_int8_t *) dh->dh_addr; 442 443 #define W1 *drq++ = *data++ 444 while (count) { 445 W1; count--; 446 } 447 #undef W1 448 dh->dh_addr += resid; 449 dh->dh_len -= resid; 450 } 451 452 /* 453 * Start the transfer. 454 */ 455 while (dh->dh_len) { 456 dcount = count = min(dh->dh_len, MAX_DMA_LEN); 457 long_drq = (volatile u_int32_t *) sc->sc_drq_addr; 458 long_data = (u_int32_t *) dh->dh_addr; 459 460 #define W4 *long_drq++ = *long_data++ 461 while (count >= 64) { 462 W4; W4; W4; W4; W4; W4; W4; W4; 463 W4; W4; W4; W4; W4; W4; W4; W4; /* 64 */ 464 count -= 64; 465 } 466 while (count >= 4) { 467 W4; count -= 4; 468 } 469 #undef W4 470 data = (u_int8_t *) long_data; 471 drq = (u_int8_t *) long_drq; 472 #else /* notyet */ 473 /* 474 * Start the transfer. 475 */ 476 while (dh->dh_len) { 477 dcount = count = min(dh->dh_len, MAX_DMA_LEN); 478 drq = (volatile u_int8_t *) sc->sc_drq_addr; 479 data = (u_int8_t *) dh->dh_addr; 480 #endif /* notyet */ 481 482 #define W1 *drq++ = *data++ 483 while (count) { 484 W1; count--; 485 } 486 #undef W1 487 dh->dh_len -= dcount; 488 dh->dh_addr += dcount; 489 } 490 dh->dh_flags |= SBC_DH_DONE; 491 492 #ifdef SBC_WRITE_HACK 493 /* 494 * XXX -- Read a byte from the SBC to trigger a /BERR. 495 * This seems to be necessary for us to notice that 496 * the target has disconnected. Ick. 06 jun 1996 (sr) 497 */ 498 if (dcount >= MAX_DMA_LEN) { 499 #if 0 500 while ((*ncr_sc->sci_csr & SCI_CSR_ACK) == 0) 501 ; 502 #endif 503 drq = (volatile u_int8_t *) sc->sc_drq_addr; 504 } 505 tmp = *drq; 506 #endif 507 } else { /* Data In */ 508 /* 509 * Get the dest address aligned. 510 */ 511 resid = 512 count = min(dh->dh_len, 4 - (((int) dh->dh_addr) & 0x3)); 513 if (count && count < 4) { 514 data = (u_int8_t *) dh->dh_addr; 515 drq = (volatile u_int8_t *) sc->sc_drq_addr; 516 517 #define R1 *data++ = *drq++ 518 while (count) { 519 R1; count--; 520 } 521 #undef R1 522 dh->dh_addr += resid; 523 dh->dh_len -= resid; 524 } 525 526 /* 527 * Start the transfer. 528 */ 529 while (dh->dh_len) { 530 dcount = count = min(dh->dh_len, MAX_DMA_LEN); 531 long_data = (u_int32_t *) dh->dh_addr; 532 long_drq = (volatile u_int32_t *) sc->sc_drq_addr; 533 534 #define R4 *long_data++ = *long_drq++ 535 while (count >= 64) { 536 R4; R4; R4; R4; R4; R4; R4; R4; 537 R4; R4; R4; R4; R4; R4; R4; R4; /* 64 */ 538 count -= 64; 539 } 540 while (count >= 4) { 541 R4; count -= 4; 542 } 543 #undef R4 544 data = (u_int8_t *) long_data; 545 drq = (volatile u_int8_t *) long_drq; 546 547 #define R1 *data++ = *drq++ 548 while (count) { 549 R1; count--; 550 } 551 #undef R1 552 dh->dh_len -= dcount; 553 dh->dh_addr += dcount; 554 } 555 dh->dh_flags |= SBC_DH_DONE; 556 } 557 558 /* 559 * OK. No bus error occurred above. Clear the nofault flag 560 * so we no longer short-circuit bus errors. 561 */ 562 nofault = (int *) 0; 563 564 #ifdef SBC_DEBUG 565 if (sbc_debug & (SBC_DB_REG | SBC_DB_INTR)) 566 printf("%s: drq intr complete: csr=0x%x, bus_csr=0x%x\n", 567 ncr_sc->sc_dev.dv_xname, *ncr_sc->sci_csr, 568 *ncr_sc->sci_bus_csr); 569 #endif 570 } 571 572 void 573 sbc_dma_alloc(ncr_sc) 574 struct ncr5380_softc *ncr_sc; 575 { 576 struct sbc_softc *sc = (struct sbc_softc *) ncr_sc; 577 struct sci_req *sr = ncr_sc->sc_current; 578 struct scsi_xfer *xs = sr->sr_xs; 579 struct sbc_pdma_handle *dh; 580 int i, xlen; 581 582 #ifdef DIAGNOSTIC 583 if (sr->sr_dma_hand != NULL) 584 panic("sbc_dma_alloc: already have PDMA handle"); 585 #endif 586 587 /* Polled transfers shouldn't allocate a PDMA handle. */ 588 if (sr->sr_flags & SR_IMMED) 589 return; 590 591 xlen = ncr_sc->sc_datalen; 592 593 /* Make sure our caller checked sc_min_dma_len. */ 594 if (xlen < MIN_DMA_LEN) 595 panic("sbc_dma_alloc: len=0x%x\n", xlen); 596 597 /* 598 * Find free PDMA handle. Guaranteed to find one since we 599 * have as many PDMA handles as the driver has processes. 600 * (instances?) 601 */ 602 for (i = 0; i < SCI_OPENINGS; i++) { 603 if ((sc->sc_pdma[i].dh_flags & SBC_DH_BUSY) == 0) 604 goto found; 605 } 606 panic("sbc: no free PDMA handles"); 607 found: 608 dh = &sc->sc_pdma[i]; 609 dh->dh_flags = SBC_DH_BUSY; 610 dh->dh_addr = ncr_sc->sc_dataptr; 611 dh->dh_len = xlen; 612 613 /* Copy the 'write' flag for convenience. */ 614 if (xs->flags & SCSI_DATA_OUT) 615 dh->dh_flags |= SBC_DH_OUT; 616 617 sr->sr_dma_hand = dh; 618 } 619 620 void 621 sbc_dma_free(ncr_sc) 622 struct ncr5380_softc *ncr_sc; 623 { 624 struct sci_req *sr = ncr_sc->sc_current; 625 struct sbc_pdma_handle *dh = sr->sr_dma_hand; 626 627 #ifdef DIAGNOSTIC 628 if (sr->sr_dma_hand == NULL) 629 panic("sbc_dma_free: no DMA handle"); 630 #endif 631 632 if (ncr_sc->sc_state & NCR_DOINGDMA) 633 panic("sbc_dma_free: free while in progress"); 634 635 if (dh->dh_flags & SBC_DH_BUSY) { 636 dh->dh_flags = 0; 637 dh->dh_addr = NULL; 638 dh->dh_len = 0; 639 } 640 sr->sr_dma_hand = NULL; 641 } 642 643 void 644 sbc_dma_poll(ncr_sc) 645 struct ncr5380_softc *ncr_sc; 646 { 647 struct sci_req *sr = ncr_sc->sc_current; 648 649 /* 650 * We shouldn't arrive here; if SR_IMMED is set, then 651 * dma_alloc() should have refused to allocate a handle 652 * for the transfer. This forces the polled PDMA code 653 * to handle the request... 654 */ 655 #ifdef SBC_DEBUG 656 if (sbc_debug & SBC_DB_DMA) 657 printf("%s: lost DRQ interrupt?\n", ncr_sc->sc_dev.dv_xname); 658 #endif 659 sr->sr_flags |= SR_OVERDUE; 660 } 661 662 void 663 sbc_dma_setup(ncr_sc) 664 struct ncr5380_softc *ncr_sc; 665 { 666 /* Not needed; we don't have real DMA */ 667 } 668 669 void 670 sbc_dma_start(ncr_sc) 671 struct ncr5380_softc *ncr_sc; 672 { 673 struct sbc_softc *sc = (struct sbc_softc *) ncr_sc; 674 struct sci_req *sr = ncr_sc->sc_current; 675 struct sbc_pdma_handle *dh = sr->sr_dma_hand; 676 677 /* 678 * Match bus phase, clear pending interrupts, set DMA mode, and 679 * assert data bus (for writing only), then start the transfer. 680 */ 681 if (dh->dh_flags & SBC_DH_OUT) { 682 *ncr_sc->sci_tcmd = PHASE_DATA_OUT; 683 SCI_CLR_INTR(ncr_sc); 684 if (sc->sc_clrintr) 685 (*sc->sc_clrintr)(ncr_sc); 686 *ncr_sc->sci_mode |= SCI_MODE_DMA; 687 *ncr_sc->sci_icmd = SCI_ICMD_DATA; 688 *ncr_sc->sci_dma_send = 0; 689 } else { 690 *ncr_sc->sci_tcmd = PHASE_DATA_IN; 691 SCI_CLR_INTR(ncr_sc); 692 if (sc->sc_clrintr) 693 (*sc->sc_clrintr)(ncr_sc); 694 *ncr_sc->sci_mode |= SCI_MODE_DMA; 695 *ncr_sc->sci_icmd = 0; 696 *ncr_sc->sci_irecv = 0; 697 } 698 ncr_sc->sc_state |= NCR_DOINGDMA; 699 700 #ifdef SBC_DEBUG 701 if (sbc_debug & SBC_DB_DMA) 702 printf("%s: PDMA started, va=%p, len=0x%x\n", 703 ncr_sc->sc_dev.dv_xname, dh->dh_addr, dh->dh_len); 704 #endif 705 } 706 707 void 708 sbc_dma_eop(ncr_sc) 709 struct ncr5380_softc *ncr_sc; 710 { 711 /* Not used; the EOP pin is wired high (GMFH, pp. 389-390) */ 712 } 713 714 void 715 sbc_dma_stop(ncr_sc) 716 struct ncr5380_softc *ncr_sc; 717 { 718 struct sbc_softc *sc = (struct sbc_softc *) ncr_sc; 719 struct sci_req *sr = ncr_sc->sc_current; 720 struct sbc_pdma_handle *dh = sr->sr_dma_hand; 721 int ntrans; 722 723 if ((ncr_sc->sc_state & NCR_DOINGDMA) == 0) { 724 #ifdef SBC_DEBUG 725 if (sbc_debug & SBC_DB_DMA) 726 printf("%s: dma_stop: DMA not running\n", 727 ncr_sc->sc_dev.dv_xname); 728 #endif 729 return; 730 } 731 ncr_sc->sc_state &= ~NCR_DOINGDMA; 732 733 if ((ncr_sc->sc_state & NCR_ABORTING) == 0) { 734 ntrans = ncr_sc->sc_datalen - dh->dh_len; 735 736 #ifdef SBC_DEBUG 737 if (sbc_debug & SBC_DB_DMA) 738 printf("%s: dma_stop: ntrans=0x%x\n", 739 ncr_sc->sc_dev.dv_xname, ntrans); 740 #endif 741 742 if (ntrans > ncr_sc->sc_datalen) 743 panic("sbc_dma_stop: excess transfer\n"); 744 745 /* Adjust data pointer */ 746 ncr_sc->sc_dataptr += ntrans; 747 ncr_sc->sc_datalen -= ntrans; 748 749 /* Clear any pending interrupts. */ 750 SCI_CLR_INTR(ncr_sc); 751 if (sc->sc_clrintr) 752 (*sc->sc_clrintr)(ncr_sc); 753 } 754 755 /* Put SBIC back into PIO mode. */ 756 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 757 *ncr_sc->sci_icmd = 0; 758 759 #ifdef SBC_DEBUG 760 if (sbc_debug & SBC_DB_REG) 761 printf("%s: dma_stop: csr=0x%x, bus_csr=0x%x\n", 762 ncr_sc->sc_dev.dv_xname, *ncr_sc->sci_csr, 763 *ncr_sc->sci_bus_csr); 764 #endif 765 } 766
Indexes created Mon Sep 22 21:09:42 GMT 2025