sbc.c revision 1.24
1 /* $NetBSD: sbc.c,v 1.24 1997/04/18 17:38:08 scottr Exp $ */ 2 3 /* 4 * Copyright (C) 1996 Scott Reynolds. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Scott Reynolds for 17 * the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * This file contains only the machine-dependent parts of the mac68k 35 * NCR 5380 SCSI driver. (Autoconfig stuff and PDMA functions.) 36 * The machine-independent parts are in ncr5380sbc.c 37 * 38 * Supported hardware includes: 39 * Macintosh II family 5380-based controller 40 * 41 * Credits, history: 42 * 43 * Scott Reynolds wrote this module, based on work by Allen Briggs 44 * (mac68k), Gordon W. Ross and David Jones (sun3), and Leo Weppelman 45 * (atari). Thanks to Allen for supplying crucial interpretation of the 46 * NetBSD/mac68k 1.1 'ncrscsi' driver. Also, Allen, Gordon, and Jason 47 * Thorpe all helped to refine this code, and were considerable sources 48 * of moral support. 49 */ 50 51 #include <sys/types.h> 52 #include <sys/param.h> 53 #include <sys/systm.h> 54 #include <sys/kernel.h> 55 #include <sys/errno.h> 56 #include <sys/device.h> 57 #include <sys/buf.h> 58 #include <sys/proc.h> 59 #include <sys/user.h> 60 61 #include <scsi/scsi_all.h> 62 #include <scsi/scsi_debug.h> 63 #include <scsi/scsiconf.h> 64 65 #include <dev/ic/ncr5380reg.h> 66 #include <dev/ic/ncr5380var.h> 67 68 #include <machine/cpu.h> 69 #include <machine/viareg.h> 70 71 #include "sbcreg.h" 72 #include "sbcvar.h" 73 74 int sbc_debug = 0 /* | SBC_DB_INTR | SBC_DB_DMA */; 75 int sbc_link_flags = 0 /* | SDEV_DB2 */; 76 int sbc_options = 0 /* | SBC_PDMA */; 77 78 static void sbc_minphys __P((struct buf *bp)); 79 80 struct scsi_adapter sbc_ops = { 81 ncr5380_scsi_cmd, /* scsi_cmd() */ 82 sbc_minphys, /* scsi_minphys() */ 83 NULL, /* open_target_lu() */ 84 NULL, /* close_target_lu() */ 85 }; 86 87 /* This is copied from julian's bt driver */ 88 /* "so we have a default dev struct for our link struct." */ 89 struct scsi_device sbc_dev = { 90 NULL, /* Use default error handler. */ 91 NULL, /* Use default start handler. */ 92 NULL, /* Use default async handler. */ 93 NULL, /* Use default "done" routine. */ 94 }; 95 96 struct cfdriver sbc_cd = { 97 NULL, "sbc", DV_DULL 98 }; 99 100 static int sbc_ready __P((struct ncr5380_softc *)); 101 static void sbc_wait_not_req __P((struct ncr5380_softc *)); 102 103 static void 104 sbc_minphys(struct buf *bp) 105 { 106 if (bp->b_bcount > MAX_DMA_LEN) 107 bp->b_bcount = MAX_DMA_LEN; 108 return (minphys(bp)); 109 } 110 111 112 /*** 113 * General support for Mac-specific SCSI logic. 114 ***/ 115 116 void 117 sbc_irq_intr(p) 118 void *p; 119 { 120 struct ncr5380_softc *ncr_sc = p; 121 int claimed = 0; 122 123 /* How we ever arrive here without IRQ set is a mystery... */ 124 if (*ncr_sc->sci_csr & SCI_CSR_INT) { 125 #ifdef SBC_DEBUG 126 if (sbc_debug & SBC_DB_INTR) 127 decode_5380_intr(ncr_sc); 128 #endif 129 claimed = ncr5380_intr(ncr_sc); 130 if (!claimed) { 131 if (((*ncr_sc->sci_csr & ~SCI_CSR_PHASE_MATCH) == SCI_CSR_INT) 132 && ((*ncr_sc->sci_bus_csr & ~SCI_BUS_RST) == 0)) 133 SCI_CLR_INTR(ncr_sc); /* RST interrupt */ 134 #ifdef SBC_DEBUG 135 else { 136 printf("%s: spurious intr\n", 137 ncr_sc->sc_dev.dv_xname); 138 SBC_BREAK; 139 } 140 #endif 141 } 142 } 143 } 144 145 #ifdef SBC_DEBUG 146 void 147 decode_5380_intr(ncr_sc) 148 struct ncr5380_softc *ncr_sc; 149 { 150 u_char csr = *ncr_sc->sci_csr; 151 u_char bus_csr = *ncr_sc->sci_bus_csr; 152 153 if (((csr & ~(SCI_CSR_PHASE_MATCH | SCI_CSR_ATN)) == SCI_CSR_INT) && 154 ((bus_csr & ~(SCI_BUS_MSG | SCI_BUS_CD | SCI_BUS_IO | SCI_BUS_DBP)) == SCI_BUS_SEL)) { 155 if (csr & SCI_BUS_IO) 156 printf("%s: reselect\n", ncr_sc->sc_dev.dv_xname); 157 else 158 printf("%s: select\n", ncr_sc->sc_dev.dv_xname); 159 } else if (((csr & ~SCI_CSR_ACK) == (SCI_CSR_DONE | SCI_CSR_INT)) && 160 ((bus_csr & (SCI_BUS_RST | SCI_BUS_BSY | SCI_BUS_SEL)) == SCI_BUS_BSY)) 161 printf("%s: dma eop\n", ncr_sc->sc_dev.dv_xname); 162 else if (((csr & ~SCI_CSR_PHASE_MATCH) == SCI_CSR_INT) && 163 ((bus_csr & ~SCI_BUS_RST) == 0)) 164 printf("%s: bus reset\n", ncr_sc->sc_dev.dv_xname); 165 else if (((csr & ~(SCI_CSR_DREQ | SCI_CSR_ATN | SCI_CSR_ACK)) == (SCI_CSR_PERR | SCI_CSR_INT | SCI_CSR_PHASE_MATCH)) && 166 ((bus_csr & (SCI_BUS_RST | SCI_BUS_BSY | SCI_BUS_SEL)) == SCI_BUS_BSY)) 167 printf("%s: parity error\n", ncr_sc->sc_dev.dv_xname); 168 else if (((csr & ~SCI_CSR_ATN) == SCI_CSR_INT) && 169 ((bus_csr & (SCI_BUS_RST | SCI_BUS_BSY | SCI_BUS_REQ | SCI_BUS_SEL)) == (SCI_BUS_BSY | SCI_BUS_REQ))) 170 printf("%s: phase mismatch\n", ncr_sc->sc_dev.dv_xname); 171 else if (((csr & ~SCI_CSR_PHASE_MATCH) == (SCI_CSR_INT | SCI_CSR_DISC)) && 172 (bus_csr == 0)) 173 printf("%s: disconnect\n", ncr_sc->sc_dev.dv_xname); 174 else 175 printf("%s: unknown intr: csr=%x, bus_csr=%x\n", 176 ncr_sc->sc_dev.dv_xname, csr, bus_csr); 177 } 178 #endif 179 180 181 /*** 182 * The following code implements polled PDMA. 183 ***/ 184 185 #define TIMEOUT 5000000 /* x 2 usec = 10 sec */ 186 187 static __inline__ int 188 sbc_ready(sc) 189 struct ncr5380_softc *sc; 190 { 191 int i = TIMEOUT; 192 193 for (;;) { 194 if ((*sc->sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) == 195 (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) 196 return 1; 197 if (((*sc->sci_csr & SCI_CSR_PHASE_MATCH) == 0) || 198 (SCI_BUSY(sc) == 0)) 199 return 0; 200 if (--i < 0) 201 break; 202 delay(2); 203 } 204 205 printf("%s: ready timeout\n", sc->sc_dev.dv_xname); 206 return 0; 207 } 208 209 static __inline__ void 210 sbc_wait_not_req(sc) 211 struct ncr5380_softc *sc; 212 { 213 int i = TIMEOUT; 214 215 for (;;) { 216 if ((*sc->sci_bus_csr & SCI_BUS_REQ) == 0 || 217 (*sc->sci_csr & SCI_CSR_PHASE_MATCH) == 0 || 218 SCI_BUSY(sc) == 0) { 219 return; 220 } 221 if (--i < 0) 222 break; 223 delay(2); 224 } 225 printf("%s: pdma not_req timeout\n", sc->sc_dev.dv_xname); 226 } 227 228 int 229 sbc_pdma_in(ncr_sc, phase, datalen, data) 230 struct ncr5380_softc *ncr_sc; 231 int phase, datalen; 232 u_char *data; 233 { 234 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 235 volatile u_int32_t *long_data = (u_int32_t *)sc->sc_drq_addr; 236 volatile u_int8_t *byte_data = (u_int8_t *)sc->sc_nodrq_addr; 237 int resid, s; 238 239 s = splbio(); 240 *ncr_sc->sci_mode |= SCI_MODE_DMA; 241 *ncr_sc->sci_irecv = 0; 242 243 #define R4 *((u_int32_t *)data)++ = *long_data++ 244 #define R1 *data++ = *byte_data++ 245 for (resid = datalen; resid >= 128; resid -= 128) { 246 if (sbc_ready(ncr_sc) == 0) 247 goto interrupt; 248 R4; R4; R4; R4; R4; R4; R4; R4; 249 R4; R4; R4; R4; R4; R4; R4; R4; 250 R4; R4; R4; R4; R4; R4; R4; R4; 251 R4; R4; R4; R4; R4; R4; R4; R4; 252 253 long_data = (u_int32_t *)sc->sc_drq_addr; 254 byte_data = (u_int8_t *)sc->sc_nodrq_addr; 255 } 256 while (resid) { 257 if (sbc_ready(ncr_sc) == 0) 258 goto interrupt; 259 R1; 260 resid--; 261 } 262 #undef R4 263 #undef R1 264 265 sbc_wait_not_req(ncr_sc); 266 interrupt: 267 SCI_CLR_INTR(ncr_sc); 268 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 269 splx(s); 270 return datalen - resid; 271 } 272 273 int 274 sbc_pdma_out(ncr_sc, phase, datalen, data) 275 struct ncr5380_softc *ncr_sc; 276 int phase, datalen; 277 u_char *data; 278 { 279 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 280 volatile u_int32_t *long_data = (u_int32_t *)sc->sc_drq_addr; 281 volatile u_int8_t *byte_data = (u_int8_t *)sc->sc_nodrq_addr; 282 int i, s, resid; 283 u_char icmd; 284 285 if (datalen < 64) 286 return ncr5380_pio_out(ncr_sc, phase, datalen, data); 287 288 s = splbio(); 289 icmd = *(ncr_sc->sci_icmd) & SCI_ICMD_RMASK; 290 *ncr_sc->sci_icmd = icmd | SCI_ICMD_DATA; 291 *ncr_sc->sci_mode |= SCI_MODE_DMA; 292 *ncr_sc->sci_dma_send = 0; 293 294 resid = datalen; 295 if (sbc_ready(ncr_sc) == 0) 296 goto interrupt; 297 298 #define W1 *byte_data++ = *data++ 299 #define W4 *long_data++ = *((u_int32_t *)data)++ 300 while (resid >= 64) { 301 if (sbc_ready(ncr_sc) == 0) 302 goto interrupt; 303 W1; 304 resid--; 305 if (sbc_ready(ncr_sc) == 0) 306 goto interrupt; 307 W1; 308 resid--; 309 if (sbc_ready(ncr_sc) == 0) 310 goto interrupt; 311 W1; 312 resid--; 313 if (sbc_ready(ncr_sc) == 0) 314 goto interrupt; 315 W1; 316 resid--; 317 if (sbc_ready(ncr_sc) == 0) 318 goto interrupt; 319 W4; W4; W4; W4; 320 W4; W4; W4; W4; 321 W4; W4; W4; W4; 322 W4; W4; W4; 323 resid -= 60; 324 325 long_data = (u_int32_t *)sc->sc_drq_addr; 326 byte_data = (u_int8_t *)sc->sc_nodrq_addr; 327 } 328 for (; resid; resid--) { 329 if (sbc_ready(ncr_sc) == 0) 330 goto interrupt; 331 W1; 332 } 333 #undef W1 334 #undef W4 335 336 for (i = TIMEOUT; i > 0; i--) { 337 if ((*ncr_sc->sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) 338 != SCI_CSR_DREQ) 339 break; 340 } 341 if (i != 0) 342 *byte_data = 0; 343 else 344 printf("%s: timeout waiting for final SCI_DSR_DREQ.\n", 345 ncr_sc->sc_dev.dv_xname); 346 347 sbc_wait_not_req(ncr_sc); 348 interrupt: 349 SCI_CLR_INTR(ncr_sc); 350 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 351 *ncr_sc->sci_icmd = icmd; 352 splx(s); 353 return (datalen - resid); 354 } 355 356 357 /*** 358 * The following code implements interrupt-driven PDMA. 359 ***/ 360 361 /* 362 * This is the meat of the PDMA transfer. 363 * When we get here, we shove data as fast as the mac can take it. 364 * We depend on several things: 365 * * All macs after the Mac Plus that have a 5380 chip should have a general 366 * logic IC that handshakes data for blind transfers. 367 * * If the SCSI controller finishes sending/receiving data before we do, 368 * the same general logic IC will generate a /BERR for us in short order. 369 * * The fault address for said /BERR minus the base address for the 370 * transfer will be the amount of data that was actually written. 371 * 372 * We use the nofault flag and the setjmp/longjmp in locore.s so we can 373 * detect and handle the bus error for early termination of a command. 374 * This is usually caused by a disconnecting target. 375 */ 376 void 377 sbc_drq_intr(p) 378 void *p; 379 { 380 extern int *nofault, mac68k_buserr_addr; 381 struct sbc_softc *sc = (struct sbc_softc *)p; 382 struct ncr5380_softc *ncr_sc = (struct ncr5380_softc *)p; 383 struct sci_req *sr = ncr_sc->sc_current; 384 struct sbc_pdma_handle *dh = sr->sr_dma_hand; 385 label_t faultbuf; 386 volatile u_int32_t *long_drq; 387 u_int32_t *long_data; 388 volatile u_int8_t *drq; 389 u_int8_t *data; 390 int count, dcount, resid; 391 #ifdef SBC_WRITE_HACK 392 u_int8_t tmp; 393 #endif 394 395 /* 396 * If we're not ready to xfer data, or have no more, just return. 397 */ 398 if ((*ncr_sc->sci_csr & SCI_CSR_DREQ) == 0 || dh->dh_len == 0) 399 return; 400 401 #ifdef SBC_DEBUG 402 if (sbc_debug & SBC_DB_INTR) 403 printf("%s: drq intr, dh_len=0x%x, dh_flags=0x%x\n", 404 ncr_sc->sc_dev.dv_xname, dh->dh_len, dh->dh_flags); 405 #endif 406 407 /* 408 * Setup for a possible bus error caused by SCSI controller 409 * switching out of DATA-IN/OUT before we're done with the 410 * current transfer. 411 */ 412 nofault = (int *) &faultbuf; 413 414 if (setjmp((label_t *)nofault)) { 415 nofault = (int *) 0; 416 if ((dh->dh_flags & SBC_DH_DONE) == 0) { 417 count = (( (u_long)mac68k_buserr_addr 418 - (u_long)sc->sc_drq_addr)); 419 420 if ((count < 0) || (count > dh->dh_len)) { 421 printf("%s: complete=0x%x (pending 0x%x)\n", 422 ncr_sc->sc_dev.dv_xname, count, dh->dh_len); 423 panic("something is wrong"); 424 } 425 426 dh->dh_addr += count; 427 dh->dh_len -= count; 428 } else 429 count = 0; 430 431 #ifdef SBC_DEBUG 432 if (sbc_debug & SBC_DB_INTR) 433 printf("%s: drq /berr, complete=0x%x (pending 0x%x)\n", 434 ncr_sc->sc_dev.dv_xname, count, dh->dh_len); 435 #endif 436 mac68k_buserr_addr = 0; 437 438 return; 439 } 440 441 if (dh->dh_flags & SBC_DH_OUT) { /* Data Out */ 442 #if notyet /* XXX */ 443 /* 444 * Get the source address aligned. 445 */ 446 resid = 447 count = min(dh->dh_len, 4 - (((int)dh->dh_addr) & 0x3)); 448 if (count && count < 4) { 449 drq = (volatile u_int8_t *)sc->sc_drq_addr; 450 data = (u_int8_t *)dh->dh_addr; 451 452 #define W1 *drq++ = *data++ 453 while (count) { 454 W1; count--; 455 } 456 #undef W1 457 dh->dh_addr += resid; 458 dh->dh_len -= resid; 459 } 460 461 /* 462 * Start the transfer. 463 */ 464 while (dh->dh_len) { 465 dcount = count = min(dh->dh_len, MAX_DMA_LEN); 466 long_drq = (volatile u_int32_t *)sc->sc_drq_addr; 467 long_data = (u_int32_t *)dh->dh_addr; 468 469 #define W4 *long_drq++ = *long_data++ 470 while (count >= 64) { 471 W4; W4; W4; W4; W4; W4; W4; W4; 472 W4; W4; W4; W4; W4; W4; W4; W4; /* 64 */ 473 count -= 64; 474 } 475 while (count >= 4) { 476 W4; count -= 4; 477 } 478 #undef W4 479 data = (u_int8_t *)long_data; 480 drq = (u_int8_t *)long_drq; 481 #else /* notyet */ 482 /* 483 * Start the transfer. 484 */ 485 while (dh->dh_len) { 486 dcount = count = min(dh->dh_len, MAX_DMA_LEN); 487 drq = (volatile u_int8_t *)sc->sc_drq_addr; 488 data = (u_int8_t *)dh->dh_addr; 489 #endif /* notyet */ 490 491 #define W1 *drq++ = *data++ 492 while (count) { 493 W1; count--; 494 } 495 #undef W1 496 dh->dh_len -= dcount; 497 dh->dh_addr += dcount; 498 } 499 dh->dh_flags |= SBC_DH_DONE; 500 501 #ifdef SBC_WRITE_HACK 502 /* 503 * XXX -- Read a byte from the SBC to trigger a /BERR. 504 * This seems to be necessary for us to notice that 505 * the target has disconnected. Ick. 06 jun 1996 (sr) 506 */ 507 if (dcount >= MAX_DMA_LEN) { 508 #if 0 509 while ((*ncr_sc->sci_csr & SCI_CSR_ACK) == 0) 510 ; 511 #endif 512 drq = (volatile u_int8_t *)sc->sc_drq_addr; 513 } 514 tmp = *drq; 515 #endif 516 } else { /* Data In */ 517 /* 518 * Get the dest address aligned. 519 */ 520 resid = 521 count = min(dh->dh_len, 4 - (((int)dh->dh_addr) & 0x3)); 522 if (count && count < 4) { 523 data = (u_int8_t *)dh->dh_addr; 524 drq = (volatile u_int8_t *)sc->sc_drq_addr; 525 526 #define R1 *data++ = *drq++ 527 while (count) { 528 R1; count--; 529 } 530 #undef R1 531 dh->dh_addr += resid; 532 dh->dh_len -= resid; 533 } 534 535 /* 536 * Start the transfer. 537 */ 538 while (dh->dh_len) { 539 dcount = count = min(dh->dh_len, MAX_DMA_LEN); 540 long_data = (u_int32_t *)dh->dh_addr; 541 long_drq = (volatile u_int32_t *)sc->sc_drq_addr; 542 543 #define R4 *long_data++ = *long_drq++ 544 while (count >= 64) { 545 R4; R4; R4; R4; R4; R4; R4; R4; 546 R4; R4; R4; R4; R4; R4; R4; R4; /* 64 */ 547 count -= 64; 548 } 549 while (count >= 4) { 550 R4; count -= 4; 551 } 552 #undef R4 553 data = (u_int8_t *)long_data; 554 drq = (volatile u_int8_t *)long_drq; 555 556 #define R1 *data++ = *drq++ 557 while (count) { 558 R1; count--; 559 } 560 #undef R1 561 dh->dh_len -= dcount; 562 dh->dh_addr += dcount; 563 } 564 dh->dh_flags |= SBC_DH_DONE; 565 } 566 567 /* 568 * OK. No bus error occurred above. Clear the nofault flag 569 * so we no longer short-circuit bus errors. 570 */ 571 nofault = (int *) 0; 572 573 #ifdef SBC_DEBUG 574 if (sbc_debug & (SBC_DB_REG | SBC_DB_INTR)) 575 printf("%s: drq intr complete: csr=0x%x, bus_csr=0x%x\n", 576 ncr_sc->sc_dev.dv_xname, *ncr_sc->sci_csr, 577 *ncr_sc->sci_bus_csr); 578 #endif 579 } 580 581 void 582 sbc_dma_alloc(ncr_sc) 583 struct ncr5380_softc *ncr_sc; 584 { 585 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 586 struct sci_req *sr = ncr_sc->sc_current; 587 struct scsi_xfer *xs = sr->sr_xs; 588 struct sbc_pdma_handle *dh; 589 int i, xlen; 590 591 #ifdef DIAGNOSTIC 592 if (sr->sr_dma_hand != NULL) 593 panic("sbc_dma_alloc: already have PDMA handle"); 594 #endif 595 596 /* Polled transfers shouldn't allocate a PDMA handle. */ 597 if (sr->sr_flags & SR_IMMED) 598 return; 599 600 xlen = ncr_sc->sc_datalen; 601 602 /* Make sure our caller checked sc_min_dma_len. */ 603 if (xlen < MIN_DMA_LEN) 604 panic("sbc_dma_alloc: len=0x%x\n", xlen); 605 606 /* 607 * Find free PDMA handle. Guaranteed to find one since we 608 * have as many PDMA handles as the driver has processes. 609 * (instances?) 610 */ 611 for (i = 0; i < SCI_OPENINGS; i++) { 612 if ((sc->sc_pdma[i].dh_flags & SBC_DH_BUSY) == 0) 613 goto found; 614 } 615 panic("sbc: no free PDMA handles"); 616 found: 617 dh = &sc->sc_pdma[i]; 618 dh->dh_flags = SBC_DH_BUSY; 619 dh->dh_addr = ncr_sc->sc_dataptr; 620 dh->dh_len = xlen; 621 622 /* Copy the 'write' flag for convenience. */ 623 if (xs->flags & SCSI_DATA_OUT) 624 dh->dh_flags |= SBC_DH_OUT; 625 626 sr->sr_dma_hand = dh; 627 } 628 629 void 630 sbc_dma_free(ncr_sc) 631 struct ncr5380_softc *ncr_sc; 632 { 633 struct sci_req *sr = ncr_sc->sc_current; 634 struct sbc_pdma_handle *dh = sr->sr_dma_hand; 635 636 #ifdef DIAGNOSTIC 637 if (sr->sr_dma_hand == NULL) 638 panic("sbc_dma_free: no DMA handle"); 639 #endif 640 641 if (ncr_sc->sc_state & NCR_DOINGDMA) 642 panic("sbc_dma_free: free while in progress"); 643 644 if (dh->dh_flags & SBC_DH_BUSY) { 645 dh->dh_flags = 0; 646 dh->dh_addr = NULL; 647 dh->dh_len = 0; 648 } 649 sr->sr_dma_hand = NULL; 650 } 651 652 void 653 sbc_dma_poll(ncr_sc) 654 struct ncr5380_softc *ncr_sc; 655 { 656 struct sci_req *sr = ncr_sc->sc_current; 657 658 /* 659 * We shouldn't arrive here; if SR_IMMED is set, then 660 * dma_alloc() should have refused to allocate a handle 661 * for the transfer. This forces the polled PDMA code 662 * to handle the request... 663 */ 664 #ifdef SBC_DEBUG 665 if (sbc_debug & SBC_DB_DMA) 666 printf("%s: lost DRQ interrupt?\n", ncr_sc->sc_dev.dv_xname); 667 #endif 668 sr->sr_flags |= SR_OVERDUE; 669 } 670 671 void 672 sbc_dma_setup(ncr_sc) 673 struct ncr5380_softc *ncr_sc; 674 { 675 /* Not needed; we don't have real DMA */ 676 } 677 678 void 679 sbc_dma_start(ncr_sc) 680 struct ncr5380_softc *ncr_sc; 681 { 682 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 683 struct sci_req *sr = ncr_sc->sc_current; 684 struct sbc_pdma_handle *dh = sr->sr_dma_hand; 685 686 /* 687 * Match bus phase, clear pending interrupts, set DMA mode, and 688 * assert data bus (for writing only), then start the transfer. 689 */ 690 if (dh->dh_flags & SBC_DH_OUT) { 691 *ncr_sc->sci_tcmd = PHASE_DATA_OUT; 692 SCI_CLR_INTR(ncr_sc); 693 if (sc->sc_clrintr) 694 (*sc->sc_clrintr)(ncr_sc); 695 *ncr_sc->sci_mode |= SCI_MODE_DMA; 696 *ncr_sc->sci_icmd = SCI_ICMD_DATA; 697 *ncr_sc->sci_dma_send = 0; 698 } else { 699 *ncr_sc->sci_tcmd = PHASE_DATA_IN; 700 SCI_CLR_INTR(ncr_sc); 701 if (sc->sc_clrintr) 702 (*sc->sc_clrintr)(ncr_sc); 703 *ncr_sc->sci_mode |= SCI_MODE_DMA; 704 *ncr_sc->sci_icmd = 0; 705 *ncr_sc->sci_irecv = 0; 706 } 707 ncr_sc->sc_state |= NCR_DOINGDMA; 708 709 #ifdef SBC_DEBUG 710 if (sbc_debug & SBC_DB_DMA) 711 printf("%s: PDMA started, va=%p, len=0x%x\n", 712 ncr_sc->sc_dev.dv_xname, dh->dh_addr, dh->dh_len); 713 #endif 714 } 715 716 void 717 sbc_dma_eop(ncr_sc) 718 struct ncr5380_softc *ncr_sc; 719 { 720 /* Not used; the EOP pin is wired high (GMFH, pp. 389-390) */ 721 } 722 723 void 724 sbc_dma_stop(ncr_sc) 725 struct ncr5380_softc *ncr_sc; 726 { 727 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 728 struct sci_req *sr = ncr_sc->sc_current; 729 struct sbc_pdma_handle *dh = sr->sr_dma_hand; 730 int ntrans; 731 732 if ((ncr_sc->sc_state & NCR_DOINGDMA) == 0) { 733 #ifdef SBC_DEBUG 734 if (sbc_debug & SBC_DB_DMA) 735 printf("%s: dma_stop: DMA not running\n", 736 ncr_sc->sc_dev.dv_xname); 737 #endif 738 return; 739 } 740 ncr_sc->sc_state &= ~NCR_DOINGDMA; 741 742 if ((ncr_sc->sc_state & NCR_ABORTING) == 0) { 743 ntrans = ncr_sc->sc_datalen - dh->dh_len; 744 745 #ifdef SBC_DEBUG 746 if (sbc_debug & SBC_DB_DMA) 747 printf("%s: dma_stop: ntrans=0x%x\n", 748 ncr_sc->sc_dev.dv_xname, ntrans); 749 #endif 750 751 if (ntrans > ncr_sc->sc_datalen) 752 panic("sbc_dma_stop: excess transfer\n"); 753 754 /* Adjust data pointer */ 755 ncr_sc->sc_dataptr += ntrans; 756 ncr_sc->sc_datalen -= ntrans; 757 758 /* Clear any pending interrupts. */ 759 SCI_CLR_INTR(ncr_sc); 760 if (sc->sc_clrintr) 761 (*sc->sc_clrintr)(ncr_sc); 762 } 763 764 /* Put SBIC back into PIO mode. */ 765 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 766 *ncr_sc->sci_icmd = 0; 767 768 #ifdef SBC_DEBUG 769 if (sbc_debug & SBC_DB_REG) 770 printf("%s: dma_stop: csr=0x%x, bus_csr=0x%x\n", 771 ncr_sc->sc_dev.dv_xname, *ncr_sc->sci_csr, 772 *ncr_sc->sci_bus_csr); 773 #endif 774 } 775
Indexes created Tue Sep 23 14:10:03 GMT 2025