sbc.c revision 1.28
1 /* $NetBSD: sbc.c,v 1.28 1997/06/30 05:24:35 scottr Exp $ */ 2 3 /* 4 * Copyright (C) 1996 Scott Reynolds. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Scott Reynolds for 17 * the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * This file contains only the machine-dependent parts of the mac68k 35 * NCR 5380 SCSI driver. (Autoconfig stuff and PDMA functions.) 36 * The machine-independent parts are in ncr5380sbc.c 37 * 38 * Supported hardware includes: 39 * Macintosh II family 5380-based controller 40 * 41 * Credits, history: 42 * 43 * Scott Reynolds wrote this module, based on work by Allen Briggs 44 * (mac68k), Gordon W. Ross and David Jones (sun3), and Leo Weppelman 45 * (atari). Thanks to Allen for supplying crucial interpretation of the 46 * NetBSD/mac68k 1.1 'ncrscsi' driver. Also, Allen, Gordon, and Jason 47 * Thorpe all helped to refine this code, and were considerable sources 48 * of moral support. 49 */ 50 51 #include <sys/types.h> 52 #include <sys/param.h> 53 #include <sys/systm.h> 54 #include <sys/kernel.h> 55 #include <sys/errno.h> 56 #include <sys/device.h> 57 #include <sys/buf.h> 58 #include <sys/proc.h> 59 #include <sys/user.h> 60 61 #include <scsi/scsi_all.h> 62 #include <scsi/scsi_debug.h> 63 #include <scsi/scsiconf.h> 64 65 #include <dev/ic/ncr5380reg.h> 66 #include <dev/ic/ncr5380var.h> 67 68 #include <machine/cpu.h> 69 #include <machine/viareg.h> 70 71 #include "sbcreg.h" 72 #include "sbcvar.h" 73 74 int sbc_debug = 0 /* | SBC_DB_INTR | SBC_DB_DMA */; 75 int sbc_link_flags = 0 /* | SDEV_DB2 */; 76 int sbc_options = 0 /* | SBC_PDMA */; 77 78 static void sbc_minphys __P((struct buf *bp)); 79 80 struct scsi_adapter sbc_ops = { 81 ncr5380_scsi_cmd, /* scsi_cmd() */ 82 sbc_minphys, /* scsi_minphys() */ 83 NULL, /* open_target_lu() */ 84 NULL, /* close_target_lu() */ 85 }; 86 87 /* This is copied from julian's bt driver */ 88 /* "so we have a default dev struct for our link struct." */ 89 struct scsi_device sbc_dev = { 90 NULL, /* Use default error handler. */ 91 NULL, /* Use default start handler. */ 92 NULL, /* Use default async handler. */ 93 NULL, /* Use default "done" routine. */ 94 }; 95 96 struct cfdriver sbc_cd = { 97 NULL, "sbc", DV_DULL 98 }; 99 100 static int sbc_wait_busy __P((struct ncr5380_softc *)); 101 static int sbc_ready __P((struct ncr5380_softc *)); 102 static int sbc_wait_dreq __P((struct ncr5380_softc *)); 103 104 static void 105 sbc_minphys(struct buf *bp) 106 { 107 if (bp->b_bcount > MAX_DMA_LEN) 108 bp->b_bcount = MAX_DMA_LEN; 109 return (minphys(bp)); 110 } 111 112 113 /*** 114 * General support for Mac-specific SCSI logic. 115 ***/ 116 117 /* These are used in the following inline functions. */ 118 int sbc_wait_busy_timo = 1000 * 5000; /* X2 = 10 S. */ 119 int sbc_ready_timo = 1000 * 5000; /* X2 = 10 S. */ 120 int sbc_wait_dreq_timo = 1000 * 5000; /* X2 = 10 S. */ 121 122 /* Return zero on success. */ 123 static __inline__ int 124 sbc_wait_busy(sc) 125 struct ncr5380_softc *sc; 126 { 127 int timo = sbc_wait_busy_timo; 128 for (;;) { 129 if (SCI_BUSY(sc)) { 130 timo = 0; /* return 0 */ 131 break; 132 } 133 if (--timo < 0) 134 break; /* return -1 */ 135 delay(2); 136 } 137 return (timo); 138 } 139 140 static __inline__ int 141 sbc_ready(sc) 142 struct ncr5380_softc *sc; 143 { 144 int timo = sbc_ready_timo; 145 146 for (;;) { 147 if ((*sc->sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) 148 == (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 149 timo = 0; 150 break; 151 } 152 if (((*sc->sci_csr & SCI_CSR_PHASE_MATCH) == 0) 153 || (SCI_BUSY(sc) == 0)) { 154 timo = -1; 155 break; 156 } 157 if (--timo < 0) 158 break; /* return -1 */ 159 delay(2); 160 } 161 return (timo); 162 } 163 164 static __inline__ int 165 sbc_wait_dreq(sc) 166 struct ncr5380_softc *sc; 167 { 168 int timo = sbc_wait_dreq_timo; 169 170 for (;;) { 171 if ((*sc->sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) 172 == (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 173 timo = 0; 174 break; 175 } 176 if (--timo < 0) 177 break; /* return -1 */ 178 delay(2); 179 } 180 return (timo); 181 } 182 183 void 184 sbc_irq_intr(p) 185 void *p; 186 { 187 struct ncr5380_softc *ncr_sc = p; 188 int claimed = 0; 189 190 /* How we ever arrive here without IRQ set is a mystery... */ 191 if (*ncr_sc->sci_csr & SCI_CSR_INT) { 192 #ifdef SBC_DEBUG 193 if (sbc_debug & SBC_DB_INTR) 194 decode_5380_intr(ncr_sc); 195 #endif 196 claimed = ncr5380_intr(ncr_sc); 197 if (!claimed) { 198 if (((*ncr_sc->sci_csr & ~SCI_CSR_PHASE_MATCH) == SCI_CSR_INT) 199 && ((*ncr_sc->sci_bus_csr & ~SCI_BUS_RST) == 0)) 200 SCI_CLR_INTR(ncr_sc); /* RST interrupt */ 201 #ifdef SBC_DEBUG 202 else { 203 printf("%s: spurious intr\n", 204 ncr_sc->sc_dev.dv_xname); 205 SBC_BREAK; 206 } 207 #endif 208 } 209 } 210 } 211 212 #ifdef SBC_DEBUG 213 void 214 decode_5380_intr(ncr_sc) 215 struct ncr5380_softc *ncr_sc; 216 { 217 u_int8_t csr = *ncr_sc->sci_csr; 218 u_int8_t bus_csr = *ncr_sc->sci_bus_csr; 219 220 if (((csr & ~(SCI_CSR_PHASE_MATCH | SCI_CSR_ATN)) == SCI_CSR_INT) && 221 ((bus_csr & ~(SCI_BUS_MSG | SCI_BUS_CD | SCI_BUS_IO | SCI_BUS_DBP)) == SCI_BUS_SEL)) { 222 if (csr & SCI_BUS_IO) 223 printf("%s: reselect\n", ncr_sc->sc_dev.dv_xname); 224 else 225 printf("%s: select\n", ncr_sc->sc_dev.dv_xname); 226 } else if (((csr & ~SCI_CSR_ACK) == (SCI_CSR_DONE | SCI_CSR_INT)) && 227 ((bus_csr & (SCI_BUS_RST | SCI_BUS_BSY | SCI_BUS_SEL)) == SCI_BUS_BSY)) 228 printf("%s: dma eop\n", ncr_sc->sc_dev.dv_xname); 229 else if (((csr & ~SCI_CSR_PHASE_MATCH) == SCI_CSR_INT) && 230 ((bus_csr & ~SCI_BUS_RST) == 0)) 231 printf("%s: bus reset\n", ncr_sc->sc_dev.dv_xname); 232 else if (((csr & ~(SCI_CSR_DREQ | SCI_CSR_ATN | SCI_CSR_ACK)) == (SCI_CSR_PERR | SCI_CSR_INT | SCI_CSR_PHASE_MATCH)) && 233 ((bus_csr & (SCI_BUS_RST | SCI_BUS_BSY | SCI_BUS_SEL)) == SCI_BUS_BSY)) 234 printf("%s: parity error\n", ncr_sc->sc_dev.dv_xname); 235 else if (((csr & ~SCI_CSR_ATN) == SCI_CSR_INT) && 236 ((bus_csr & (SCI_BUS_RST | SCI_BUS_BSY | SCI_BUS_REQ | SCI_BUS_SEL)) == (SCI_BUS_BSY | SCI_BUS_REQ))) 237 printf("%s: phase mismatch\n", ncr_sc->sc_dev.dv_xname); 238 else if (((csr & ~SCI_CSR_PHASE_MATCH) == (SCI_CSR_INT | SCI_CSR_DISC)) && 239 (bus_csr == 0)) 240 printf("%s: disconnect\n", ncr_sc->sc_dev.dv_xname); 241 else 242 printf("%s: unknown intr: csr=%x, bus_csr=%x\n", 243 ncr_sc->sc_dev.dv_xname, csr, bus_csr); 244 } 245 #endif 246 247 248 /*** 249 * The following code implements polled PDMA. 250 ***/ 251 252 int 253 sbc_pdma_in(ncr_sc, phase, datalen, data) 254 struct ncr5380_softc *ncr_sc; 255 int phase; 256 int datalen; 257 u_char *data; 258 { 259 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 260 volatile u_int32_t *long_data = (u_int32_t *)sc->sc_drq_addr; 261 volatile u_int8_t *byte_data = (u_int8_t *)sc->sc_nodrq_addr; 262 int resid, s; 263 264 if (datalen < ncr_sc->sc_min_dma_len || 265 (sc->sc_options & SBC_PDMA) == 0) 266 return ncr5380_pio_in(ncr_sc, phase, datalen, data); 267 268 s = splbio(); 269 if (sbc_wait_busy(ncr_sc)) { 270 splx(s); 271 return 0; 272 } 273 274 *ncr_sc->sci_mode |= SCI_MODE_DMA; 275 *ncr_sc->sci_irecv = 0; 276 277 #define R4 *((u_int32_t *)data)++ = *long_data 278 #define R1 *((u_int8_t *)data)++ = *byte_data 279 for (resid = datalen; resid >= 128; resid -= 128) { 280 if (sbc_ready(ncr_sc)) 281 goto interrupt; 282 R4; R4; R4; R4; R4; R4; R4; R4; 283 R4; R4; R4; R4; R4; R4; R4; R4; 284 R4; R4; R4; R4; R4; R4; R4; R4; 285 R4; R4; R4; R4; R4; R4; R4; R4; /* 128 */ 286 } 287 while (resid) { 288 if (sbc_ready(ncr_sc)) 289 goto interrupt; 290 R1; 291 resid--; 292 } 293 #undef R4 294 #undef R1 295 296 interrupt: 297 SCI_CLR_INTR(ncr_sc); 298 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 299 *ncr_sc->sci_icmd = 0; 300 splx(s); 301 return (datalen - resid); 302 } 303 304 int 305 sbc_pdma_out(ncr_sc, phase, datalen, data) 306 struct ncr5380_softc *ncr_sc; 307 int phase; 308 int datalen; 309 u_char *data; 310 { 311 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 312 volatile u_int32_t *long_data = (u_int32_t *)sc->sc_drq_addr; 313 volatile u_int8_t *byte_data = (u_int8_t *)sc->sc_nodrq_addr; 314 int resid, s; 315 u_int8_t icmd; 316 317 if (datalen < ncr_sc->sc_min_dma_len || 318 (sc->sc_options & SBC_PDMA) == 0) 319 return ncr5380_pio_out(ncr_sc, phase, datalen, data); 320 321 s = splbio(); 322 if (sbc_wait_busy(ncr_sc)) { 323 splx(s); 324 return 0; 325 } 326 327 icmd = *(ncr_sc->sci_icmd) & SCI_ICMD_RMASK; 328 *ncr_sc->sci_icmd = icmd | SCI_ICMD_DATA; 329 *ncr_sc->sci_mode |= SCI_MODE_DMA; 330 *ncr_sc->sci_dma_send = 0; 331 332 #define W1 *byte_data = *((u_int8_t *)data)++ 333 #define W4 *long_data = *((u_int32_t *)data)++ 334 for (resid = datalen; resid >= 64; resid -= 64) { 335 if (sbc_ready(ncr_sc)) 336 goto interrupt; 337 W1; 338 if (sbc_ready(ncr_sc)) 339 goto interrupt; 340 W1; 341 if (sbc_ready(ncr_sc)) 342 goto interrupt; 343 W1; 344 if (sbc_ready(ncr_sc)) 345 goto interrupt; 346 W1; 347 if (sbc_ready(ncr_sc)) 348 goto interrupt; 349 W4; W4; W4; W4; 350 W4; W4; W4; W4; 351 W4; W4; W4; W4; 352 W4; W4; W4; 353 } 354 while (resid) { 355 if (sbc_ready(ncr_sc)) 356 goto interrupt; 357 W1; 358 resid--; 359 } 360 #undef W1 361 #undef W4 362 if (sbc_wait_dreq(ncr_sc)) 363 printf("%s: timeout waiting for DREQ.\n", 364 ncr_sc->sc_dev.dv_xname); 365 366 *byte_data = 0; 367 goto done; 368 369 interrupt: 370 if ((*ncr_sc->sci_csr & SCI_CSR_PHASE_MATCH) == 0) { 371 *ncr_sc->sci_icmd = icmd & ~SCI_ICMD_DATA; 372 --resid; 373 } 374 375 done: 376 SCI_CLR_INTR(ncr_sc); 377 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 378 *ncr_sc->sci_icmd = icmd; 379 splx(s); 380 return (datalen - resid); 381 } 382 383 384 /*** 385 * The following code implements interrupt-driven PDMA. 386 ***/ 387 388 /* 389 * This is the meat of the PDMA transfer. 390 * When we get here, we shove data as fast as the mac can take it. 391 * We depend on several things: 392 * * All macs after the Mac Plus that have a 5380 chip should have a general 393 * logic IC that handshakes data for blind transfers. 394 * * If the SCSI controller finishes sending/receiving data before we do, 395 * the same general logic IC will generate a /BERR for us in short order. 396 * * The fault address for said /BERR minus the base address for the 397 * transfer will be the amount of data that was actually written. 398 * 399 * We use the nofault flag and the setjmp/longjmp in locore.s so we can 400 * detect and handle the bus error for early termination of a command. 401 * This is usually caused by a disconnecting target. 402 */ 403 void 404 sbc_drq_intr(p) 405 void *p; 406 { 407 extern int *nofault, m68k_fault_addr; 408 struct sbc_softc *sc = (struct sbc_softc *)p; 409 struct ncr5380_softc *ncr_sc = (struct ncr5380_softc *)p; 410 struct sci_req *sr = ncr_sc->sc_current; 411 struct sbc_pdma_handle *dh = sr->sr_dma_hand; 412 label_t faultbuf; 413 volatile u_int32_t *long_drq; 414 u_int32_t *long_data; 415 volatile u_int8_t *drq; 416 u_int8_t *data; 417 int count, dcount, resid; 418 u_int8_t tmp; 419 420 /* Work around lame gcc initialization bug */ 421 (void)&drq; 422 423 /* 424 * If we're not ready to xfer data, or have no more, just return. 425 */ 426 if ((*ncr_sc->sci_csr & SCI_CSR_DREQ) == 0 || dh->dh_len == 0) 427 return; 428 429 #ifdef SBC_DEBUG 430 if (sbc_debug & SBC_DB_INTR) 431 printf("%s: drq intr, dh_len=0x%x, dh_flags=0x%x\n", 432 ncr_sc->sc_dev.dv_xname, dh->dh_len, dh->dh_flags); 433 #endif 434 435 /* 436 * Setup for a possible bus error caused by SCSI controller 437 * switching out of DATA-IN/OUT before we're done with the 438 * current transfer. 439 */ 440 nofault = (int *)&faultbuf; 441 442 if (setjmp((label_t *)nofault)) { 443 nofault = (int *)0; 444 if ((dh->dh_flags & SBC_DH_DONE) == 0) { 445 count = (( (u_long)m68k_fault_addr 446 - (u_long)sc->sc_drq_addr)); 447 448 if ((count < 0) || (count > dh->dh_len)) { 449 printf("%s: complete=0x%x (pending 0x%x)\n", 450 ncr_sc->sc_dev.dv_xname, count, dh->dh_len); 451 panic("something is wrong"); 452 } 453 454 dh->dh_addr += count; 455 dh->dh_len -= count; 456 } else 457 count = 0; 458 459 #ifdef SBC_DEBUG 460 if (sbc_debug & SBC_DB_INTR) 461 printf("%s: drq /berr, complete=0x%x (pending 0x%x)\n", 462 ncr_sc->sc_dev.dv_xname, count, dh->dh_len); 463 #endif 464 m68k_fault_addr = 0; 465 466 return; 467 } 468 469 if (dh->dh_flags & SBC_DH_OUT) { /* Data Out */ 470 dcount = 0; 471 472 /* 473 * Get the source address aligned. 474 */ 475 resid = 476 count = min(dh->dh_len, 4 - (((int)dh->dh_addr) & 0x3)); 477 if (count && count < 4) { 478 drq = (volatile u_int8_t *)sc->sc_drq_addr; 479 data = (u_int8_t *)dh->dh_addr; 480 481 #define W1 *drq++ = *data++ 482 while (count) { 483 W1; count--; 484 } 485 #undef W1 486 dh->dh_addr += resid; 487 dh->dh_len -= resid; 488 } 489 490 /* 491 * Start the transfer. 492 */ 493 while (dh->dh_len) { 494 dcount = count = min(dh->dh_len, MAX_DMA_LEN); 495 long_drq = (volatile u_int32_t *)sc->sc_drq_addr; 496 long_data = (u_int32_t *)dh->dh_addr; 497 498 #define W4 *long_drq++ = *long_data++ 499 while (count >= 64) { 500 W4; W4; W4; W4; W4; W4; W4; W4; 501 W4; W4; W4; W4; W4; W4; W4; W4; /* 64 */ 502 count -= 64; 503 } 504 while (count >= 4) { 505 W4; count -= 4; 506 } 507 #undef W4 508 data = (u_int8_t *)long_data; 509 drq = (u_int8_t *)long_drq; 510 511 #define W1 *drq++ = *data++ 512 while (count) { 513 W1; count--; 514 } 515 #undef W1 516 dh->dh_len -= dcount; 517 dh->dh_addr += dcount; 518 } 519 dh->dh_flags |= SBC_DH_DONE; 520 521 /* 522 * XXX -- Read a byte from the SBC to trigger a /BERR. 523 * This seems to be necessary for us to notice that 524 * the target has disconnected. Ick. 06 jun 1996 (sr) 525 */ 526 if (dcount >= MAX_DMA_LEN) 527 drq = (volatile u_int8_t *)sc->sc_drq_addr; 528 tmp = *drq; 529 } else { /* Data In */ 530 /* 531 * Get the dest address aligned. 532 */ 533 resid = 534 count = min(dh->dh_len, 4 - (((int)dh->dh_addr) & 0x3)); 535 if (count && count < 4) { 536 data = (u_int8_t *)dh->dh_addr; 537 drq = (volatile u_int8_t *)sc->sc_drq_addr; 538 539 #define R1 *data++ = *drq++ 540 while (count) { 541 R1; count--; 542 } 543 #undef R1 544 dh->dh_addr += resid; 545 dh->dh_len -= resid; 546 } 547 548 /* 549 * Start the transfer. 550 */ 551 while (dh->dh_len) { 552 dcount = count = min(dh->dh_len, MAX_DMA_LEN); 553 long_data = (u_int32_t *)dh->dh_addr; 554 long_drq = (volatile u_int32_t *)sc->sc_drq_addr; 555 556 #define R4 *long_data++ = *long_drq++ 557 while (count >= 64) { 558 R4; R4; R4; R4; R4; R4; R4; R4; 559 R4; R4; R4; R4; R4; R4; R4; R4; /* 64 */ 560 count -= 64; 561 } 562 while (count >= 4) { 563 R4; count -= 4; 564 } 565 #undef R4 566 data = (u_int8_t *)long_data; 567 drq = (volatile u_int8_t *)long_drq; 568 569 #define R1 *data++ = *drq++ 570 while (count) { 571 R1; count--; 572 } 573 #undef R1 574 dh->dh_len -= dcount; 575 dh->dh_addr += dcount; 576 } 577 dh->dh_flags |= SBC_DH_DONE; 578 } 579 580 /* 581 * OK. No bus error occurred above. Clear the nofault flag 582 * so we no longer short-circuit bus errors. 583 */ 584 nofault = (int *)0; 585 586 #ifdef SBC_DEBUG 587 if (sbc_debug & (SBC_DB_REG | SBC_DB_INTR)) 588 printf("%s: drq intr complete: csr=0x%x, bus_csr=0x%x\n", 589 ncr_sc->sc_dev.dv_xname, *ncr_sc->sci_csr, 590 *ncr_sc->sci_bus_csr); 591 #endif 592 } 593 594 void 595 sbc_dma_alloc(ncr_sc) 596 struct ncr5380_softc *ncr_sc; 597 { 598 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 599 struct sci_req *sr = ncr_sc->sc_current; 600 struct scsi_xfer *xs = sr->sr_xs; 601 struct sbc_pdma_handle *dh; 602 int i, xlen; 603 604 #ifdef DIAGNOSTIC 605 if (sr->sr_dma_hand != NULL) 606 panic("sbc_dma_alloc: already have PDMA handle"); 607 #endif 608 609 /* Polled transfers shouldn't allocate a PDMA handle. */ 610 if (sr->sr_flags & SR_IMMED) 611 return; 612 613 xlen = ncr_sc->sc_datalen; 614 615 /* Make sure our caller checked sc_min_dma_len. */ 616 if (xlen < MIN_DMA_LEN) 617 panic("sbc_dma_alloc: len=0x%x\n", xlen); 618 619 /* 620 * Find free PDMA handle. Guaranteed to find one since we 621 * have as many PDMA handles as the driver has processes. 622 * (instances?) 623 */ 624 for (i = 0; i < SCI_OPENINGS; i++) { 625 if ((sc->sc_pdma[i].dh_flags & SBC_DH_BUSY) == 0) 626 goto found; 627 } 628 panic("sbc: no free PDMA handles"); 629 found: 630 dh = &sc->sc_pdma[i]; 631 dh->dh_flags = SBC_DH_BUSY; 632 dh->dh_addr = ncr_sc->sc_dataptr; 633 dh->dh_len = xlen; 634 635 /* Copy the 'write' flag for convenience. */ 636 if (xs->flags & SCSI_DATA_OUT) 637 dh->dh_flags |= SBC_DH_OUT; 638 639 sr->sr_dma_hand = dh; 640 } 641 642 void 643 sbc_dma_free(ncr_sc) 644 struct ncr5380_softc *ncr_sc; 645 { 646 struct sci_req *sr = ncr_sc->sc_current; 647 struct sbc_pdma_handle *dh = sr->sr_dma_hand; 648 649 #ifdef DIAGNOSTIC 650 if (sr->sr_dma_hand == NULL) 651 panic("sbc_dma_free: no DMA handle"); 652 #endif 653 654 if (ncr_sc->sc_state & NCR_DOINGDMA) 655 panic("sbc_dma_free: free while in progress"); 656 657 if (dh->dh_flags & SBC_DH_BUSY) { 658 dh->dh_flags = 0; 659 dh->dh_addr = NULL; 660 dh->dh_len = 0; 661 } 662 sr->sr_dma_hand = NULL; 663 } 664 665 void 666 sbc_dma_poll(ncr_sc) 667 struct ncr5380_softc *ncr_sc; 668 { 669 struct sci_req *sr = ncr_sc->sc_current; 670 671 /* 672 * We shouldn't arrive here; if SR_IMMED is set, then 673 * dma_alloc() should have refused to allocate a handle 674 * for the transfer. This forces the polled PDMA code 675 * to handle the request... 676 */ 677 #ifdef SBC_DEBUG 678 if (sbc_debug & SBC_DB_DMA) 679 printf("%s: lost DRQ interrupt?\n", ncr_sc->sc_dev.dv_xname); 680 #endif 681 sr->sr_flags |= SR_OVERDUE; 682 } 683 684 void 685 sbc_dma_setup(ncr_sc) 686 struct ncr5380_softc *ncr_sc; 687 { 688 /* Not needed; we don't have real DMA */ 689 } 690 691 void 692 sbc_dma_start(ncr_sc) 693 struct ncr5380_softc *ncr_sc; 694 { 695 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 696 struct sci_req *sr = ncr_sc->sc_current; 697 struct sbc_pdma_handle *dh = sr->sr_dma_hand; 698 699 /* 700 * Match bus phase, clear pending interrupts, set DMA mode, and 701 * assert data bus (for writing only), then start the transfer. 702 */ 703 if (dh->dh_flags & SBC_DH_OUT) { 704 *ncr_sc->sci_tcmd = PHASE_DATA_OUT; 705 SCI_CLR_INTR(ncr_sc); 706 if (sc->sc_clrintr) 707 (*sc->sc_clrintr)(ncr_sc); 708 *ncr_sc->sci_mode |= SCI_MODE_DMA; 709 *ncr_sc->sci_icmd = SCI_ICMD_DATA; 710 *ncr_sc->sci_dma_send = 0; 711 } else { 712 *ncr_sc->sci_tcmd = PHASE_DATA_IN; 713 SCI_CLR_INTR(ncr_sc); 714 if (sc->sc_clrintr) 715 (*sc->sc_clrintr)(ncr_sc); 716 *ncr_sc->sci_mode |= SCI_MODE_DMA; 717 *ncr_sc->sci_icmd = 0; 718 *ncr_sc->sci_irecv = 0; 719 } 720 ncr_sc->sc_state |= NCR_DOINGDMA; 721 722 #ifdef SBC_DEBUG 723 if (sbc_debug & SBC_DB_DMA) 724 printf("%s: PDMA started, va=%p, len=0x%x\n", 725 ncr_sc->sc_dev.dv_xname, dh->dh_addr, dh->dh_len); 726 #endif 727 } 728 729 void 730 sbc_dma_eop(ncr_sc) 731 struct ncr5380_softc *ncr_sc; 732 { 733 /* Not used; the EOP pin is wired high (GMFH, pp. 389-390) */ 734 } 735 736 void 737 sbc_dma_stop(ncr_sc) 738 struct ncr5380_softc *ncr_sc; 739 { 740 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 741 struct sci_req *sr = ncr_sc->sc_current; 742 struct sbc_pdma_handle *dh = sr->sr_dma_hand; 743 int ntrans; 744 745 if ((ncr_sc->sc_state & NCR_DOINGDMA) == 0) { 746 #ifdef SBC_DEBUG 747 if (sbc_debug & SBC_DB_DMA) 748 printf("%s: dma_stop: DMA not running\n", 749 ncr_sc->sc_dev.dv_xname); 750 #endif 751 return; 752 } 753 ncr_sc->sc_state &= ~NCR_DOINGDMA; 754 755 if ((ncr_sc->sc_state & NCR_ABORTING) == 0) { 756 ntrans = ncr_sc->sc_datalen - dh->dh_len; 757 758 #ifdef SBC_DEBUG 759 if (sbc_debug & SBC_DB_DMA) 760 printf("%s: dma_stop: ntrans=0x%x\n", 761 ncr_sc->sc_dev.dv_xname, ntrans); 762 #endif 763 764 if (ntrans > ncr_sc->sc_datalen) 765 panic("sbc_dma_stop: excess transfer\n"); 766 767 /* Adjust data pointer */ 768 ncr_sc->sc_dataptr += ntrans; 769 ncr_sc->sc_datalen -= ntrans; 770 771 /* Clear any pending interrupts. */ 772 SCI_CLR_INTR(ncr_sc); 773 if (sc->sc_clrintr) 774 (*sc->sc_clrintr)(ncr_sc); 775 } 776 777 /* Put SBIC back into PIO mode. */ 778 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 779 *ncr_sc->sci_icmd = 0; 780 781 #ifdef SBC_DEBUG 782 if (sbc_debug & SBC_DB_REG) 783 printf("%s: dma_stop: csr=0x%x, bus_csr=0x%x\n", 784 ncr_sc->sc_dev.dv_xname, *ncr_sc->sci_csr, 785 *ncr_sc->sci_bus_csr); 786 #endif 787 } 788
Indexes created Tue Sep 23 14:10:03 GMT 2025