sbc.c revision 1.3
1 /* $NetBSD: sbc.c,v 1.3 1996/04/30 17:07:17 scottr Exp $ */ 2 3 /* 4 * Copyright (c) 1996 Scott Reynolds 5 * Copyright (c) 1995 David Jones 6 * Copyright (c) 1995 Allen Briggs 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of the authors may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 4. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by David Jones, Allen 22 * Briggs and Scott Reynolds. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 28 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 29 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 30 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 31 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 33 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 /* 37 * This file contains only the machine-dependent parts of the mac68k 38 * NCR 5380 SCSI driver. (Autoconfig stuff and PDMA functions.) 39 * The machine-independent parts are in ncr5380sbc.c 40 * 41 * Supported hardware includes: 42 * Macintosh II family 5380-based controller 43 * 44 * Credits, history: 45 * 46 * Scott Reynolds wrote this module, based on work by Allen Briggs 47 * (mac68k), David Jones (sun3), and Leo Weppelman (atari). Allen 48 * supplied some crucial interpretation of the NetBSD 1.1 'ncrscsi' 49 * driver. Allen, Gordon W. Ross, and Jason Thorpe all helped to 50 * refine this code, and were considerable sources of moral support. 51 * 52 * The sbc_options code is based on similar code in Jason's modified 53 * NetBSD/sparc 'si' driver. 54 */ 55 56 #include <sys/types.h> 57 #include <sys/param.h> 58 #include <sys/systm.h> 59 #include <sys/kernel.h> 60 #include <sys/errno.h> 61 #include <sys/device.h> 62 #include <sys/buf.h> 63 #include <sys/proc.h> 64 #include <sys/user.h> 65 66 #include <scsi/scsi_all.h> 67 #include <scsi/scsi_debug.h> 68 #include <scsi/scsiconf.h> 69 70 #include <dev/ic/ncr5380reg.h> 71 #include <dev/ic/ncr5380var.h> 72 73 #include <machine/viareg.h> 74 75 #include "sbcreg.h" 76 77 /* 78 * Transfers smaller than this are done using PIO 79 * (on assumption they're not worth PDMA overhead) 80 */ 81 #define MIN_DMA_LEN 128 82 83 /* 84 * Transfers larger than 8192 bytes need to be split up 85 * due to the size of the PDMA space. 86 */ 87 #define MAX_DMA_LEN 0x2000 88 89 /* 90 * From Guide to the Macintosh Family Hardware, p. 137 91 * These are offsets from SCSIBase (see pmap_bootstrap.c) 92 */ 93 #define SBC_REGISTER_OFFSET 0x10000 94 #define SBC_DMA_DRQ_OFFSET 0x06000 95 #define SBC_DMA_NODRQ_OFFSET 0x12000 96 97 #ifdef SBC_DEBUG 98 # define SBC_DB_INTR 0x01 99 # define SBC_DB_DMA 0x02 100 # define SBC_DB_REG 0x04 101 # define SBC_DB_BREAK 0x08 102 103 int sbc_debug = 0 /* | SBC_DB_INTR | SBC_DB_DMA */; 104 int sbc_link_flags = 0 /* | SDEV_DB2 */; 105 106 # ifndef DDB 107 # define Debugger() printf("Debug: sbc.c:%d\n", __LINE__) 108 # endif 109 # define SBC_BREAK \ 110 do { if (sbc_debug & SBC_DB_BREAK) Debugger(); } while (0) 111 #else 112 # define SBC_BREAK 113 #endif 114 115 /* 116 * This structure is used to keep track of PDMA requests. 117 */ 118 struct sbc_pdma_handle { 119 int dh_flags; /* flags */ 120 #define SBC_DH_BUSY 0x01 /* This handle is in use */ 121 #define SBC_DH_OUT 0x02 /* PDMA data out (write) */ 122 u_char *dh_addr; /* data buffer */ 123 int dh_len; /* length of data buffer */ 124 }; 125 126 /* 127 * The first structure member has to be the ncr5380_softc 128 * so we can just cast to go back and forth between them. 129 */ 130 struct sbc_softc { 131 struct ncr5380_softc ncr_sc; 132 volatile struct sbc_regs *sc_regs; 133 volatile long *sc_drq_addr; 134 volatile u_char *sc_nodrq_addr; 135 volatile u_char *sc_ienable; 136 volatile u_char *sc_iflag; 137 int sc_options; /* options for this instance. */ 138 struct sbc_pdma_handle sc_pdma[SCI_OPENINGS]; 139 }; 140 141 /* 142 * Options. By default, SCSI interrupts and reselect are disabled. 143 * You may enable either of these features with the `flags' directive 144 * in your kernel's configuration file. 145 * 146 * Alternatively, you can patch your kernel with DDB or some other 147 * mechanism. The sc_options member of the softc is OR'd with 148 * the value in sbc_options. 149 */ 150 #define SBC_INTR 0x01 /* Allow SCSI IRQ/DRQ interrupts */ 151 #define SBC_RESELECT 0x02 /* Allow disconnect/reselect */ 152 #define SBC_OPTIONS_MASK (SBC_INTR|SBC_RESELECT) 153 #define SBC_OPTIONS_BITS "\10\2RESELECT\1INTR" 154 int sbc_options = 0; 155 156 static int sbc_match __P(()); 157 static void sbc_attach __P(()); 158 static void sbc_minphys __P((struct buf *bp)); 159 160 static int sbc_wait_busy __P((struct ncr5380_softc *)); 161 static int sbc_ready __P((struct ncr5380_softc *)); 162 static int sbc_wait_dreq __P((struct ncr5380_softc *)); 163 static int sbc_pdma_in __P((struct ncr5380_softc *, int, int, u_char *)); 164 static int sbc_pdma_out __P((struct ncr5380_softc *, int, int, u_char *)); 165 #ifdef SBC_DEBUG 166 static void decode_5380_intr __P((struct ncr5380_softc *)); 167 #endif 168 169 void sbc_intr_enable __P((struct ncr5380_softc *)); 170 void sbc_intr_disable __P((struct ncr5380_softc *)); 171 void sbc_irq_intr __P((void *)); 172 void sbc_drq_intr __P((void *)); 173 void sbc_dma_alloc __P((struct ncr5380_softc *)); 174 void sbc_dma_free __P((struct ncr5380_softc *)); 175 void sbc_dma_poll __P((struct ncr5380_softc *)); 176 void sbc_dma_setup __P((struct ncr5380_softc *)); 177 void sbc_dma_start __P((struct ncr5380_softc *)); 178 void sbc_dma_eop __P((struct ncr5380_softc *)); 179 void sbc_dma_stop __P((struct ncr5380_softc *)); 180 181 static struct scsi_adapter sbc_ops = { 182 ncr5380_scsi_cmd, /* scsi_cmd() */ 183 sbc_minphys, /* scsi_minphys() */ 184 NULL, /* open_target_lu() */ 185 NULL, /* close_target_lu() */ 186 }; 187 188 /* This is copied from julian's bt driver */ 189 /* "so we have a default dev struct for our link struct." */ 190 static struct scsi_device sbc_dev = { 191 NULL, /* Use default error handler. */ 192 NULL, /* Use default start handler. */ 193 NULL, /* Use default async handler. */ 194 NULL, /* Use default "done" routine. */ 195 }; 196 197 struct cfattach sbc_ca = { 198 sizeof(struct sbc_softc), sbc_match, sbc_attach 199 }; 200 201 struct cfdriver sbc_cd = { 202 NULL, "sbc", DV_DULL 203 }; 204 205 206 static int 207 sbc_print(aux, name) 208 void *aux; 209 char *name; 210 { 211 if (name != NULL) 212 printf("%s: scsibus ", name); 213 return UNCONF; 214 } 215 216 static int 217 sbc_match(parent, match, args) 218 struct device *parent; 219 void *match, *args; 220 { 221 struct device *self = match; /* XXX mainbus is "indirect" */ 222 struct confargs *ca = args; 223 224 if (matchbyname(parent, match, ca) == 0) 225 return 0; 226 if (!mac68k_machine.scsi80) 227 return 0; 228 if (self->dv_cfdata->cf_unit != 0) 229 return 0; 230 return 1; 231 } 232 233 static void 234 sbc_attach(parent, self, args) 235 struct device *parent, *self; 236 void *args; 237 { 238 static int probed = 0; 239 struct sbc_softc *sc = (struct sbc_softc *) self; 240 struct ncr5380_softc *ncr_sc = (struct ncr5380_softc *) sc; 241 struct confargs *ca = args; 242 extern vm_offset_t SCSIBase; 243 int i; 244 245 /* Pull in the options flags. */ 246 sc->sc_options = 247 ((ncr_sc->sc_dev.dv_cfdata->cf_flags | sbc_options) & SBC_OPTIONS_MASK); 248 249 /* 250 * Set up base address of 5380 251 */ 252 sc->sc_regs = (struct sbc_regs *)(SCSIBase + SBC_REGISTER_OFFSET); 253 254 /* 255 * Fill in the prototype scsi_link. 256 */ 257 ncr_sc->sc_link.adapter_softc = sc; 258 ncr_sc->sc_link.adapter_target = 7; 259 ncr_sc->sc_link.adapter = &sbc_ops; 260 ncr_sc->sc_link.device = &sbc_dev; 261 262 /* 263 * Initialize fields used by the MI code 264 */ 265 ncr_sc->sci_r0 = &sc->sc_regs->sci_pr0.sci_reg; 266 ncr_sc->sci_r1 = &sc->sc_regs->sci_pr1.sci_reg; 267 ncr_sc->sci_r2 = &sc->sc_regs->sci_pr2.sci_reg; 268 ncr_sc->sci_r3 = &sc->sc_regs->sci_pr3.sci_reg; 269 ncr_sc->sci_r4 = &sc->sc_regs->sci_pr4.sci_reg; 270 ncr_sc->sci_r5 = &sc->sc_regs->sci_pr5.sci_reg; 271 ncr_sc->sci_r6 = &sc->sc_regs->sci_pr6.sci_reg; 272 ncr_sc->sci_r7 = &sc->sc_regs->sci_pr7.sci_reg; 273 274 /* 275 * MD function pointers used by the MI code. 276 */ 277 ncr_sc->sc_pio_out = sbc_pdma_out; 278 ncr_sc->sc_pio_in = sbc_pdma_in; 279 ncr_sc->sc_dma_alloc = NULL; 280 ncr_sc->sc_dma_free = NULL; 281 ncr_sc->sc_dma_poll = NULL; 282 ncr_sc->sc_intr_on = NULL; 283 ncr_sc->sc_intr_off = NULL; 284 ncr_sc->sc_dma_setup = NULL; 285 ncr_sc->sc_dma_start = NULL; 286 ncr_sc->sc_dma_eop = NULL; 287 ncr_sc->sc_dma_stop = NULL; 288 ncr_sc->sc_flags = 0; 289 ncr_sc->sc_min_dma_len = MIN_DMA_LEN; 290 291 /* 292 * MD function pointers used by the MI code. 293 */ 294 if ((sc->sc_options & SBC_INTR) == 0) { 295 ncr_sc->sc_flags |= NCR5380_FORCE_POLLING; 296 } else { 297 if (sc->sc_options & SBC_RESELECT) 298 ncr_sc->sc_flags |= NCR5380_PERMIT_RESELECT; 299 ncr_sc->sc_dma_alloc = sbc_dma_alloc; 300 ncr_sc->sc_dma_free = sbc_dma_free; 301 ncr_sc->sc_dma_poll = sbc_dma_poll; 302 ncr_sc->sc_dma_setup = sbc_dma_setup; 303 ncr_sc->sc_dma_start = sbc_dma_start; 304 ncr_sc->sc_dma_eop = sbc_dma_eop; 305 ncr_sc->sc_dma_stop = sbc_dma_stop; 306 mac68k_register_scsi_drq(sbc_drq_intr, ncr_sc); 307 mac68k_register_scsi_irq(sbc_irq_intr, ncr_sc); 308 } 309 310 /* 311 * Initialize fields used only here in the MD code. 312 */ 313 sc->sc_drq_addr = (long *) (SCSIBase + SBC_DMA_DRQ_OFFSET); 314 sc->sc_nodrq_addr = (u_char *) (SCSIBase + SBC_DMA_NODRQ_OFFSET); 315 if (VIA2 == VIA2OFF) { 316 sc->sc_ienable = Via1Base + VIA2 * 0x2000 + vIER; 317 sc->sc_iflag = Via1Base + VIA2 * 0x2000 + vIFR; 318 } else { 319 sc->sc_ienable = Via1Base + VIA2 * 0x2000 + rIER; 320 sc->sc_iflag = Via1Base + VIA2 * 0x2000 + rIFR; 321 } 322 323 if (sc->sc_options) 324 printf(": options=%b", sc->sc_options, SBC_OPTIONS_BITS); 325 printf("\n"); 326 327 /* Now enable SCSI interrupts through VIA2, if appropriate */ 328 if (sc->sc_options & SBC_INTR) 329 sbc_intr_enable(ncr_sc); 330 331 #ifdef SBC_DEBUG 332 if (sbc_debug) 333 printf("%s: softc=%x regs=%x\n", ncr_sc->sc_dev.dv_xname, 334 sc, sc->sc_regs); 335 ncr_sc->sc_link.flags |= sbc_link_flags; 336 #endif 337 338 /* 339 * Initialize the SCSI controller itself. 340 */ 341 ncr5380_init(ncr_sc); 342 ncr5380_reset_scsibus(ncr_sc); 343 config_found(self, &(ncr_sc->sc_link), sbc_print); 344 } 345 346 347 static void 348 sbc_minphys(struct buf *bp) 349 { 350 if (bp->b_bcount > MAX_DMA_LEN) 351 bp->b_bcount = MAX_DMA_LEN; 352 return (minphys(bp)); 353 } 354 355 356 /*** 357 * General support for Mac-specific SCSI logic. 358 ***/ 359 360 /* These are used in the following inline functions. */ 361 int sbc_wait_busy_timo = 1000 * 5000; /* X2 = 10 S. */ 362 int sbc_ready_timo = 1000 * 5000; /* X2 = 10 S. */ 363 int sbc_wait_dreq_timo = 1000 * 5000; /* X2 = 10 S. */ 364 365 /* Return zero on success. */ 366 static __inline__ int 367 sbc_wait_busy(sc) 368 struct ncr5380_softc *sc; 369 { 370 register int timo = sbc_wait_busy_timo; 371 for (;;) { 372 if (SCI_BUSY(sc)) { 373 timo = 0; /* return 0 */ 374 break; 375 } 376 if (--timo < 0) 377 break; /* return -1 */ 378 delay(2); 379 } 380 return (timo); 381 } 382 383 static __inline__ int 384 sbc_ready(sc) 385 struct ncr5380_softc *sc; 386 { 387 register int timo = sbc_ready_timo; 388 389 for (;;) { 390 if ((*sc->sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) 391 == (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 392 timo = 0; 393 break; 394 } 395 if (((*sc->sci_csr & SCI_CSR_PHASE_MATCH) == 0) 396 || (SCI_BUSY(sc) == 0)) { 397 timo = -1; 398 break; 399 } 400 if (--timo < 0) 401 break; /* return -1 */ 402 delay(2); 403 } 404 return (timo); 405 } 406 407 static __inline__ int 408 sbc_wait_dreq(sc) 409 struct ncr5380_softc *sc; 410 { 411 register int timo = sbc_wait_dreq_timo; 412 413 for (;;) { 414 if ((*sc->sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) 415 == (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 416 timo = 0; 417 break; 418 } 419 if (--timo < 0) 420 break; /* return -1 */ 421 delay(2); 422 } 423 return (timo); 424 } 425 426 427 /*** 428 * Macintosh SCSI interrupt support routines. 429 ***/ 430 431 void 432 sbc_intr_enable(ncr_sc) 433 struct ncr5380_softc *ncr_sc; 434 { 435 register struct sbc_softc *sc = (struct sbc_softc *) ncr_sc; 436 int s; 437 438 s = splhigh(); 439 *sc->sc_iflag = (V2IF_SCSIIRQ | V2IF_SCSIDRQ); 440 *sc->sc_ienable = 0x80 | (V2IF_SCSIIRQ | V2IF_SCSIDRQ); 441 splx(s); 442 } 443 444 void 445 sbc_intr_disable(ncr_sc) 446 struct ncr5380_softc *ncr_sc; 447 { 448 register struct sbc_softc *sc = (struct sbc_softc *) ncr_sc; 449 int s; 450 451 s = splhigh(); 452 *sc->sc_ienable = (V2IF_SCSIIRQ | V2IF_SCSIDRQ); 453 splx(s); 454 } 455 456 void 457 sbc_irq_intr(p) 458 void *p; 459 { 460 static int handling_sbc_intr = 0; 461 register struct ncr5380_softc *ncr_sc = p; 462 register int claimed = 0; 463 464 /* How we ever arrive here without IRQ set is a mystery... */ 465 if (*ncr_sc->sci_csr & SCI_CSR_INT) { 466 /* 467 * For some reason, the hardware sometimes generates a 468 * spurious selection interrupt. I don't know why this 469 * happens, but the following hack works around it. --sar 470 */ 471 if (handling_sbc_intr) 472 return; 473 handling_sbc_intr++; 474 475 #ifdef SBC_DEBUG 476 if (sbc_debug & SBC_DB_INTR) 477 decode_5380_intr(ncr_sc); 478 #endif 479 claimed = ncr5380_intr(ncr_sc); 480 if (!claimed) { 481 if (((*ncr_sc->sci_csr & ~SCI_CSR_PHASE_MATCH) == SCI_CSR_INT) 482 && ((*ncr_sc->sci_bus_csr & ~SCI_BUS_RST) == 0)) 483 SCI_CLR_INTR(ncr_sc); /* RST interrupt */ 484 #ifdef SBC_DEBUG 485 else { 486 printf("%s: spurious intr\n", 487 ncr_sc->sc_dev.dv_xname); 488 SBC_BREAK; 489 } 490 #endif 491 } 492 493 /* We can handle another interrupt from the SBC now. */ 494 handling_sbc_intr = 0; 495 } 496 } 497 498 #ifdef SBC_DEBUG 499 void 500 decode_5380_intr(ncr_sc) 501 struct ncr5380_softc *ncr_sc; 502 { 503 register u_char csr = *ncr_sc->sci_csr; 504 register u_char bus_csr = *ncr_sc->sci_bus_csr; 505 506 if (((csr & ~(SCI_CSR_PHASE_MATCH | SCI_CSR_ATN)) == SCI_CSR_INT) && 507 ((bus_csr & ~(SCI_BUS_MSG | SCI_BUS_CD | SCI_BUS_IO | SCI_BUS_DBP)) == SCI_BUS_SEL)) { 508 if (csr & SCI_BUS_IO) 509 printf("%s: reselect\n", ncr_sc->sc_dev.dv_xname); 510 else 511 printf("%s: select\n", ncr_sc->sc_dev.dv_xname); 512 } else if (((csr & ~SCI_CSR_ACK) == (SCI_CSR_DONE | SCI_CSR_INT)) && 513 ((bus_csr & (SCI_BUS_RST | SCI_BUS_BSY | SCI_BUS_SEL)) == SCI_BUS_BSY)) 514 printf("%s: dma eop\n", ncr_sc->sc_dev.dv_xname); 515 else if (((csr & ~SCI_CSR_PHASE_MATCH) == SCI_CSR_INT) && 516 ((bus_csr & ~SCI_BUS_RST) == 0)) 517 printf("%s: bus reset\n", ncr_sc->sc_dev.dv_xname); 518 else if (((csr & ~(SCI_CSR_DREQ | SCI_CSR_ATN | SCI_CSR_ACK)) == (SCI_CSR_PERR | SCI_CSR_INT | SCI_CSR_PHASE_MATCH)) && 519 ((bus_csr & (SCI_BUS_RST | SCI_BUS_BSY | SCI_BUS_SEL)) == SCI_BUS_BSY)) 520 printf("%s: parity error\n", ncr_sc->sc_dev.dv_xname); 521 else if (((csr & ~SCI_CSR_ATN) == SCI_CSR_INT) && 522 ((bus_csr & (SCI_BUS_RST | SCI_BUS_BSY | SCI_BUS_REQ | SCI_BUS_SEL)) == (SCI_BUS_BSY | SCI_BUS_REQ))) 523 printf("%s: phase mismatch\n", ncr_sc->sc_dev.dv_xname); 524 else if (((csr & ~SCI_CSR_PHASE_MATCH) == (SCI_CSR_INT | SCI_CSR_DISC)) && 525 (bus_csr == 0)) 526 printf("%s: disconnect\n", ncr_sc->sc_dev.dv_xname); 527 else 528 printf("%s: unknown intr: csr=%x, bus_csr=%x\n", 529 ncr_sc->sc_dev.dv_xname, csr, bus_csr); 530 } 531 #endif 532 533 /*** 534 * The following code implements polled PDMA. 535 ***/ 536 537 static int 538 sbc_pdma_out(ncr_sc, phase, count, data) 539 struct ncr5380_softc *ncr_sc; 540 int phase; 541 int count; 542 u_char *data; 543 { 544 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 545 register volatile long *long_data = sc->sc_drq_addr; 546 register volatile u_char *byte_data = sc->sc_nodrq_addr; 547 register int len = count; 548 549 if (count < ncr_sc->sc_min_dma_len) 550 return ncr5380_pio_out(ncr_sc, phase, count, data); 551 552 if (sbc_wait_busy(ncr_sc) == 0) { 553 *ncr_sc->sci_mode &= ~SCI_MODE_MONBSY; /* XXX */ 554 *ncr_sc->sci_mode |= SCI_MODE_DMA; 555 *ncr_sc->sci_icmd |= SCI_ICMD_DATA; 556 *ncr_sc->sci_dma_send = 0; 557 558 #define W1 *byte_data = *data++ 559 #define W4 *long_data = *((long*)data)++ 560 while (len >= 64) { 561 if (sbc_ready(ncr_sc)) 562 goto timeout; 563 W1; 564 if (sbc_ready(ncr_sc)) 565 goto timeout; 566 W1; 567 if (sbc_ready(ncr_sc)) 568 goto timeout; 569 W1; 570 if (sbc_ready(ncr_sc)) 571 goto timeout; 572 W1; 573 if (sbc_ready(ncr_sc)) 574 goto timeout; 575 W4; W4; W4; W4; 576 W4; W4; W4; W4; 577 W4; W4; W4; W4; 578 W4; W4; W4; 579 len -= 64; 580 } 581 while (len) { 582 if (sbc_ready(ncr_sc)) 583 goto timeout; 584 W1; 585 len--; 586 } 587 #undef W1 588 #undef W4 589 if (sbc_wait_dreq(ncr_sc)) 590 printf("%s: timeout waiting for DREQ.\n", 591 ncr_sc->sc_dev.dv_xname); 592 593 *byte_data = 0; 594 595 SCI_CLR_INTR(ncr_sc); 596 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 597 *ncr_sc->sci_icmd = 0; 598 } 599 return count - len; 600 601 timeout: 602 printf("%s: pdma_out: timeout len=%d count=%d\n", 603 ncr_sc->sc_dev.dv_xname, len, count); 604 if ((*ncr_sc->sci_csr & SCI_CSR_PHASE_MATCH) == 0) { 605 *ncr_sc->sci_icmd &= ~SCI_ICMD_DATA; 606 --len; 607 } 608 609 SCI_CLR_INTR(ncr_sc); 610 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 611 *ncr_sc->sci_icmd = 0; 612 return count - len; 613 } 614 615 static int 616 sbc_pdma_in(ncr_sc, phase, count, data) 617 struct ncr5380_softc *ncr_sc; 618 int phase; 619 int count; 620 u_char *data; 621 { 622 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 623 register volatile long *long_data = sc->sc_drq_addr; 624 register volatile u_char *byte_data = sc->sc_nodrq_addr; 625 register int len = count; 626 627 if (count < ncr_sc->sc_min_dma_len) 628 return ncr5380_pio_in(ncr_sc, phase, count, data); 629 630 if (sbc_wait_busy(ncr_sc) == 0) { 631 *ncr_sc->sci_mode &= ~SCI_MODE_MONBSY; /* XXX */ 632 *ncr_sc->sci_mode |= SCI_MODE_DMA; 633 *ncr_sc->sci_icmd |= SCI_ICMD_DATA; 634 *ncr_sc->sci_irecv = 0; 635 636 #define R4 *((long *)data)++ = *long_data 637 #define R1 *data++ = *byte_data 638 while (len >= 1024) { 639 if (sbc_ready(ncr_sc)) 640 goto timeout; 641 R4; R4; R4; R4; R4; R4; R4; R4; 642 R4; R4; R4; R4; R4; R4; R4; R4; 643 R4; R4; R4; R4; R4; R4; R4; R4; 644 R4; R4; R4; R4; R4; R4; R4; R4; /* 128 */ 645 if (sbc_ready(ncr_sc)) 646 goto timeout; 647 R4; R4; R4; R4; R4; R4; R4; R4; 648 R4; R4; R4; R4; R4; R4; R4; R4; 649 R4; R4; R4; R4; R4; R4; R4; R4; 650 R4; R4; R4; R4; R4; R4; R4; R4; /* 256 */ 651 if (sbc_ready(ncr_sc)) 652 goto timeout; 653 R4; R4; R4; R4; R4; R4; R4; R4; 654 R4; R4; R4; R4; R4; R4; R4; R4; 655 R4; R4; R4; R4; R4; R4; R4; R4; 656 R4; R4; R4; R4; R4; R4; R4; R4; /* 384 */ 657 if (sbc_ready(ncr_sc)) 658 goto timeout; 659 R4; R4; R4; R4; R4; R4; R4; R4; 660 R4; R4; R4; R4; R4; R4; R4; R4; 661 R4; R4; R4; R4; R4; R4; R4; R4; 662 R4; R4; R4; R4; R4; R4; R4; R4; /* 512 */ 663 if (sbc_ready(ncr_sc)) 664 goto timeout; 665 R4; R4; R4; R4; R4; R4; R4; R4; 666 R4; R4; R4; R4; R4; R4; R4; R4; 667 R4; R4; R4; R4; R4; R4; R4; R4; 668 R4; R4; R4; R4; R4; R4; R4; R4; /* 640 */ 669 if (sbc_ready(ncr_sc)) 670 goto timeout; 671 R4; R4; R4; R4; R4; R4; R4; R4; 672 R4; R4; R4; R4; R4; R4; R4; R4; 673 R4; R4; R4; R4; R4; R4; R4; R4; 674 R4; R4; R4; R4; R4; R4; R4; R4; /* 768 */ 675 if (sbc_ready(ncr_sc)) 676 goto timeout; 677 R4; R4; R4; R4; R4; R4; R4; R4; 678 R4; R4; R4; R4; R4; R4; R4; R4; 679 R4; R4; R4; R4; R4; R4; R4; R4; 680 R4; R4; R4; R4; R4; R4; R4; R4; /* 896 */ 681 if (sbc_ready(ncr_sc)) 682 goto timeout; 683 R4; R4; R4; R4; R4; R4; R4; R4; 684 R4; R4; R4; R4; R4; R4; R4; R4; 685 R4; R4; R4; R4; R4; R4; R4; R4; 686 R4; R4; R4; R4; R4; R4; R4; R4; /* 1024 */ 687 len -= 1024; 688 } 689 while (len >= 128) { 690 if (sbc_ready(ncr_sc)) 691 goto timeout; 692 R4; R4; R4; R4; R4; R4; R4; R4; 693 R4; R4; R4; R4; R4; R4; R4; R4; 694 R4; R4; R4; R4; R4; R4; R4; R4; 695 R4; R4; R4; R4; R4; R4; R4; R4; /* 128 */ 696 len -= 128; 697 } 698 while (len) { 699 if (sbc_ready(ncr_sc)) 700 goto timeout; 701 R1; 702 len--; 703 } 704 #undef R4 705 #undef R1 706 SCI_CLR_INTR(ncr_sc); 707 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 708 *ncr_sc->sci_icmd = 0; 709 } 710 return count - len; 711 712 timeout: 713 printf("%s: pdma_in: timeout len=%d count=%d\n", 714 ncr_sc->sc_dev.dv_xname, len, count); 715 716 SCI_CLR_INTR(ncr_sc); 717 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 718 *ncr_sc->sci_icmd = 0; 719 return count - len; 720 } 721 722 723 /*** 724 * The following code implements interrupt-driven PDMA. 725 ***/ 726 727 /* 728 * This is the meat of the PDMA transfer. 729 * When we get here, we shove data as fast as the mac can take it. 730 * We depend on several things: 731 * * All macs after the Mac Plus that have a 5380 chip should have a general 732 * logic IC that handshakes data for blind transfers. 733 * * If the SCSI controller finishes sending/receiving data before we do, 734 * the same general logic IC will generate a /BERR for us in short order. 735 * * The fault address for said /BERR minus the base address for the 736 * transfer will be the amount of data that was actually written. 737 * 738 * We use the nofault flag and the setjmp/longjmp in locore.s so we can 739 * detect and handle the bus error for early termination of a command. 740 * This is usually caused by a disconnecting target. 741 */ 742 void 743 sbc_drq_intr(p) 744 void *p; 745 { 746 extern int *nofault, mac68k_buserr_addr; 747 register struct sbc_softc *sc = (struct sbc_softc *) p; 748 register struct ncr5380_softc *ncr_sc = (struct ncr5380_softc *) p; 749 register struct sci_req *sr = ncr_sc->sc_current; 750 register struct sbc_pdma_handle *dh = sr->sr_dma_hand; 751 label_t faultbuf; 752 volatile u_int32_t *long_drq; 753 u_int32_t *long_data; 754 volatile u_int8_t *drq; 755 u_int8_t *data; 756 register int count; 757 int dcount, resid; 758 759 /* 760 * If we're not ready to xfer data, or have no more, just return. 761 */ 762 if ((*ncr_sc->sci_csr & SCI_CSR_DREQ) == 0 || dh->dh_len == 0) 763 return; 764 765 #ifdef SBC_DEBUG 766 if (sbc_debug & SBC_DB_INTR) 767 printf("%s: drq intr, dh_len=0x%x, dh_flags=0x%x\n", 768 ncr_sc->sc_dev.dv_xname, dh->dh_len, dh->dh_flags); 769 #endif 770 771 /* 772 * Setup for a possible bus error caused by SCSI controller 773 * switching out of DATA-IN/OUT before we're done with the 774 * current transfer. 775 */ 776 nofault = (int *) &faultbuf; 777 778 if (setjmp((label_t *) nofault)) { 779 nofault = (int *) 0; 780 count = ( (u_long) mac68k_buserr_addr 781 - (u_long) sc->sc_drq_addr); 782 783 if ((count < 0) || (count > dh->dh_len)) { 784 printf("%s: complete=0x%x (pending 0x%x)\n", 785 ncr_sc->sc_dev.dv_xname, count, dh->dh_len); 786 panic("something is wrong"); 787 } 788 #ifdef SBC_DEBUG 789 if (sbc_debug & SBC_DB_INTR) 790 printf("%s: drq /berr, pending=0x%x, complete=0x%x\n", 791 ncr_sc->sc_dev.dv_xname, dh->dh_len, count); 792 #endif 793 794 dh->dh_addr += count; 795 dh->dh_len -= count; 796 mac68k_buserr_addr = 0; 797 798 return; 799 } 800 801 if (dh->dh_flags & SBC_DH_OUT) { /* Data Out */ 802 /* 803 * Get the source address aligned. 804 */ 805 resid = count = min(dh->dh_len, 806 4 - (((int) dh->dh_addr) & 0x3)); 807 if (count && count < 4) { 808 data = (u_int8_t *) dh->dh_addr; 809 drq = (u_int8_t *) sc->sc_drq_addr; 810 #define W1 *drq++ = *data++ 811 while (count) { 812 W1; count--; 813 } 814 #undef W1 815 dh->dh_addr += resid; 816 dh->dh_len -= resid; 817 } 818 819 /* 820 * Get ready to start the transfer. 821 */ 822 while (dh->dh_len) { 823 dcount = count = min(dh->dh_len, MAX_DMA_LEN); 824 long_drq = (volatile u_int32_t *) sc->sc_drq_addr; 825 long_data = (u_int32_t *) dh->dh_addr; 826 827 #define W4 *long_drq++ = *long_data++ 828 while (count >= 64) { 829 W4; W4; W4; W4; W4; W4; W4; W4; 830 W4; W4; W4; W4; W4; W4; W4; W4; /* 64 */ 831 count -= 64; 832 } 833 while (count >= 4) { 834 W4; count -= 4; 835 } 836 #undef W4 837 data = (u_int8_t *) long_data; 838 drq = (u_int8_t *) long_drq; 839 #define W1 *drq++ = *data++ 840 while (count) { 841 W1; count--; 842 } 843 #undef W1 844 dh->dh_len -= dcount; 845 dh->dh_addr += dcount; 846 } 847 } else { /* Data In */ 848 /* 849 * Get the dest address aligned. 850 */ 851 resid = count = min(dh->dh_len, 852 4 - (((int) dh->dh_addr) & 0x3)); 853 if (count && count < 4) { 854 data = (u_int8_t *) dh->dh_addr; 855 drq = (u_int8_t *) sc->sc_drq_addr; 856 #define R1 *data++ = *drq++ 857 while (count) { 858 R1; count--; 859 } 860 #undef R1 861 dh->dh_addr += resid; 862 dh->dh_len -= resid; 863 } 864 865 /* 866 * Get ready to start the transfer. 867 */ 868 while (dh->dh_len) { 869 dcount = count = min(dh->dh_len, MAX_DMA_LEN); 870 long_drq = (volatile u_int32_t *) sc->sc_drq_addr; 871 long_data = (u_int32_t *) dh->dh_addr; 872 873 #define R4 *long_data++ = *long_drq++ 874 while (count >= 512) { 875 if ((*ncr_sc->sci_csr & SCI_CSR_DREQ) == 0) { 876 nofault = (int *) 0; 877 878 dh->dh_addr += (dcount - count); 879 dh->dh_len -= (dcount - count); 880 return; 881 } 882 R4; R4; R4; R4; R4; R4; R4; R4; 883 R4; R4; R4; R4; R4; R4; R4; R4; /* 64 */ 884 R4; R4; R4; R4; R4; R4; R4; R4; 885 R4; R4; R4; R4; R4; R4; R4; R4; /* 128 */ 886 R4; R4; R4; R4; R4; R4; R4; R4; 887 R4; R4; R4; R4; R4; R4; R4; R4; 888 R4; R4; R4; R4; R4; R4; R4; R4; 889 R4; R4; R4; R4; R4; R4; R4; R4; /* 256 */ 890 R4; R4; R4; R4; R4; R4; R4; R4; 891 R4; R4; R4; R4; R4; R4; R4; R4; 892 R4; R4; R4; R4; R4; R4; R4; R4; 893 R4; R4; R4; R4; R4; R4; R4; R4; 894 R4; R4; R4; R4; R4; R4; R4; R4; 895 R4; R4; R4; R4; R4; R4; R4; R4; 896 R4; R4; R4; R4; R4; R4; R4; R4; 897 R4; R4; R4; R4; R4; R4; R4; R4; /* 512 */ 898 count -= 512; 899 } 900 while (count >= 4) { 901 R4; count -= 4; 902 } 903 #undef R4 904 data = (u_int8_t *) long_data; 905 drq = (u_int8_t *) long_drq; 906 #define R1 *data++ = *drq++ 907 while (count) { 908 R1; count--; 909 } 910 #undef R1 911 dh->dh_len -= dcount; 912 dh->dh_addr += dcount; 913 } 914 } 915 916 /* 917 * OK. No bus error occurred above. Clear the nofault flag 918 * so we no longer short-circuit bus errors. 919 */ 920 nofault = (int *) 0; 921 } 922 923 void 924 sbc_dma_alloc(ncr_sc) 925 struct ncr5380_softc *ncr_sc; 926 { 927 struct sbc_softc *sc = (struct sbc_softc *) ncr_sc; 928 struct sci_req *sr = ncr_sc->sc_current; 929 struct scsi_xfer *xs = sr->sr_xs; 930 struct sbc_pdma_handle *dh; 931 int i, xlen; 932 933 #ifdef DIAGNOSTIC 934 if (sr->sr_dma_hand != NULL) 935 panic("sbc_dma_alloc: already have PDMA handle"); 936 #endif 937 938 /* Polled transfers shouldn't allocate a PDMA handle. */ 939 if (sr->sr_flags & SR_IMMED) 940 return; 941 942 /* XXX - we don't trust PDMA writes yet! */ 943 if (xs->flags & SCSI_DATA_OUT) 944 return; 945 946 xlen = ncr_sc->sc_datalen; 947 948 /* Make sure our caller checked sc_min_dma_len. */ 949 if (xlen < MIN_DMA_LEN) 950 panic("sbc_dma_alloc: len=0x%x\n", xlen); 951 952 /* 953 * Find free PDMA handle. Guaranteed to find one since we 954 * have as many PDMA handles as the driver has processes. 955 * (instances?) 956 */ 957 for (i = 0; i < SCI_OPENINGS; i++) { 958 if ((sc->sc_pdma[i].dh_flags & SBC_DH_BUSY) == 0) 959 goto found; 960 } 961 panic("sbc: no free PDMA handles"); 962 found: 963 dh = &sc->sc_pdma[i]; 964 dh->dh_flags = SBC_DH_BUSY; 965 dh->dh_addr = ncr_sc->sc_dataptr; 966 dh->dh_len = xlen; 967 968 /* Copy the 'write' flag for convenience. */ 969 if (xs->flags & SCSI_DATA_OUT) 970 dh->dh_flags |= SBC_DH_OUT; 971 972 sr->sr_dma_hand = dh; 973 } 974 975 void 976 sbc_dma_free(ncr_sc) 977 struct ncr5380_softc *ncr_sc; 978 { 979 struct sci_req *sr = ncr_sc->sc_current; 980 struct sbc_pdma_handle *dh = sr->sr_dma_hand; 981 982 #ifdef DIAGNOSTIC 983 if (sr->sr_dma_hand == NULL) 984 panic("sbc_dma_free: no DMA handle"); 985 #endif 986 987 if (ncr_sc->sc_state & NCR_DOINGDMA) 988 panic("sbc_dma_free: free while in progress"); 989 990 if (dh->dh_flags & SBC_DH_BUSY) { 991 dh->dh_flags = 0; 992 dh->dh_addr = NULL; 993 dh->dh_len = 0; 994 } 995 sr->sr_dma_hand = NULL; 996 } 997 998 void 999 sbc_dma_poll(ncr_sc) 1000 struct ncr5380_softc *ncr_sc; 1001 { 1002 struct sbc_softc *sc = (struct sbc_softc *) ncr_sc; 1003 struct sci_req *sr = ncr_sc->sc_current; 1004 1005 /* 1006 * We shouldn't arrive here; if SR_IMMED is set, then 1007 * dma_alloc() should have refused to allocate a handle 1008 * for the transfer. This forces the polled PDMA code 1009 * to handle the request... 1010 */ 1011 #ifdef SBC_DEBUG 1012 if (sbc_debug & SBC_DB_DMA) 1013 printf("%s: lost DRQ interrupt?\n", ncr_sc->sc_dev.dv_xname); 1014 #endif 1015 sr->sr_flags |= SR_OVERDUE; 1016 } 1017 1018 void 1019 sbc_dma_setup(ncr_sc) 1020 struct ncr5380_softc *ncr_sc; 1021 { 1022 /* Not needed; we don't have real DMA */ 1023 } 1024 1025 void 1026 sbc_dma_start(ncr_sc) 1027 struct ncr5380_softc *ncr_sc; 1028 { 1029 struct sci_req *sr = ncr_sc->sc_current; 1030 struct sbc_pdma_handle *dh = sr->sr_dma_hand; 1031 int s; 1032 1033 s = splbio(); 1034 1035 /* 1036 * Match bus phase, set DMA mode, and assert data bus (for 1037 * writing only), then start the transfer. 1038 */ 1039 if (dh->dh_flags & SBC_DH_OUT) { 1040 *ncr_sc->sci_tcmd = PHASE_DATA_OUT; 1041 SCI_CLR_INTR(ncr_sc); 1042 *ncr_sc->sci_mode |= SCI_MODE_DMA; 1043 *ncr_sc->sci_icmd = SCI_ICMD_DATA; 1044 *ncr_sc->sci_dma_send = 0; 1045 } else { 1046 *ncr_sc->sci_tcmd = PHASE_DATA_IN; 1047 SCI_CLR_INTR(ncr_sc); 1048 *ncr_sc->sci_mode |= SCI_MODE_DMA; 1049 *ncr_sc->sci_icmd = 0; 1050 *ncr_sc->sci_irecv = 0; 1051 } 1052 ncr_sc->sc_state |= NCR_DOINGDMA; 1053 1054 splx(s); 1055 1056 #ifdef SBC_DEBUG 1057 if (sbc_debug & SBC_DB_DMA) 1058 printf("%s: PDMA started, va=%p, len=0x%x\n", 1059 ncr_sc->sc_dev.dv_xname, dh->dh_addr, dh->dh_len); 1060 #endif 1061 } 1062 1063 void 1064 sbc_dma_eop(ncr_sc) 1065 struct ncr5380_softc *ncr_sc; 1066 { 1067 /* Not used; the EOP pin is wired high (GMFH, pp. 389-390) */ 1068 } 1069 1070 void 1071 sbc_dma_stop(ncr_sc) 1072 struct ncr5380_softc *ncr_sc; 1073 { 1074 struct sbc_softc *sc = (struct sbc_softc *) ncr_sc; 1075 struct sci_req *sr = ncr_sc->sc_current; 1076 struct sbc_pdma_handle *dh = sr->sr_dma_hand; 1077 register int ntrans; 1078 1079 if ((ncr_sc->sc_state & NCR_DOINGDMA) == 0) { 1080 #ifdef SBC_DEBUG 1081 if (sbc_debug & SBC_DB_DMA) 1082 printf("%s: dma_stop: DMA not running\n", 1083 ncr_sc->sc_dev.dv_xname); 1084 #endif 1085 return; 1086 } 1087 ncr_sc->sc_state &= ~NCR_DOINGDMA; 1088 1089 if ((ncr_sc->sc_state & NCR_ABORTING) == 0) { 1090 ntrans = ncr_sc->sc_datalen - dh->dh_len; 1091 1092 #ifdef SBC_DEBUG 1093 if (sbc_debug & SBC_DB_DMA) 1094 printf("%s: dma_stop: ntrans=0x%x\n", 1095 ncr_sc->sc_dev.dv_xname, ntrans); 1096 #endif 1097 1098 if (ntrans > ncr_sc->sc_datalen) 1099 panic("sbc_dma_stop: excess transfer\n"); 1100 1101 /* Adjust data pointer */ 1102 ncr_sc->sc_dataptr += ntrans; 1103 ncr_sc->sc_datalen -= ntrans; 1104 1105 /* Clear any pending interrupts. */ 1106 SCI_CLR_INTR(ncr_sc); 1107 } 1108 1109 /* Put SBIC back into PIO mode. */ 1110 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 1111 *ncr_sc->sci_icmd = 0; 1112 1113 #ifdef SBC_DEBUG 1114 if (sbc_debug & SBC_DB_REG) 1115 printf("%s: dma_stop: csr=0x%x, bus_csr=0x%x\n", 1116 ncr_sc->sc_dev.dv_xname, *ncr_sc->sci_csr, 1117 *ncr_sc->sci_bus_csr); 1118 #endif 1119 } 1120
Indexes created Tue Sep 23 14:10:03 GMT 2025