sbc.c revision 1.30
1 /* $NetBSD: sbc.c,v 1.30 1997/08/27 11:23:53 bouyer Exp $ */ 2 3 /* 4 * Copyright (C) 1996 Scott Reynolds. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Scott Reynolds for 17 * the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * This file contains only the machine-dependent parts of the mac68k 35 * NCR 5380 SCSI driver. (Autoconfig stuff and PDMA functions.) 36 * The machine-independent parts are in ncr5380sbc.c 37 * 38 * Supported hardware includes: 39 * Macintosh II family 5380-based controller 40 * 41 * Credits, history: 42 * 43 * Scott Reynolds wrote this module, based on work by Allen Briggs 44 * (mac68k), Gordon W. Ross and David Jones (sun3), and Leo Weppelman 45 * (atari). Thanks to Allen for supplying crucial interpretation of the 46 * NetBSD/mac68k 1.1 'ncrscsi' driver. Also, Allen, Gordon, and Jason 47 * Thorpe all helped to refine this code, and were considerable sources 48 * of moral support. 49 */ 50 51 #include <sys/types.h> 52 #include <sys/param.h> 53 #include <sys/systm.h> 54 #include <sys/kernel.h> 55 #include <sys/errno.h> 56 #include <sys/device.h> 57 #include <sys/buf.h> 58 #include <sys/proc.h> 59 #include <sys/user.h> 60 61 #include <dev/scsipi/scsi_all.h> 62 #include <dev/scsipi/scsipi_all.h> 63 #include <dev/scsipi/scsipi_debug.h> 64 #include <dev/scsipi/scsiconf.h> 65 66 #include <dev/ic/ncr5380reg.h> 67 #include <dev/ic/ncr5380var.h> 68 69 #include <machine/cpu.h> 70 #include <machine/viareg.h> 71 72 #include <mac68k/dev/sbcreg.h> 73 #include <mac68k/dev/sbcvar.h> 74 75 int sbc_debug = 0 /* | SBC_DB_INTR | SBC_DB_DMA */; 76 int sbc_link_flags = 0 /* | SDEV_DB2 */; 77 int sbc_options = 0 /* | SBC_PDMA */; 78 79 static void sbc_minphys __P((struct buf *bp)); 80 81 struct scsipi_adapter sbc_ops = { 82 ncr5380_scsi_cmd, /* scsi_cmd() */ 83 sbc_minphys, /* scsi_minphys() */ 84 NULL, /* open_target_lu() */ 85 NULL, /* close_target_lu() */ 86 }; 87 88 /* This is copied from julian's bt driver */ 89 /* "so we have a default dev struct for our link struct." */ 90 struct scsipi_device sbc_dev = { 91 NULL, /* Use default error handler. */ 92 NULL, /* Use default start handler. */ 93 NULL, /* Use default async handler. */ 94 NULL, /* Use default "done" routine. */ 95 }; 96 97 struct cfdriver sbc_cd = { 98 NULL, "sbc", DV_DULL 99 }; 100 101 static int sbc_wait_busy __P((struct ncr5380_softc *)); 102 static int sbc_ready __P((struct ncr5380_softc *)); 103 static int sbc_wait_dreq __P((struct ncr5380_softc *)); 104 105 static void 106 sbc_minphys(struct buf *bp) 107 { 108 if (bp->b_bcount > MAX_DMA_LEN) 109 bp->b_bcount = MAX_DMA_LEN; 110 return (minphys(bp)); 111 } 112 113 114 /*** 115 * General support for Mac-specific SCSI logic. 116 ***/ 117 118 /* These are used in the following inline functions. */ 119 int sbc_wait_busy_timo = 1000 * 5000; /* X2 = 10 S. */ 120 int sbc_ready_timo = 1000 * 5000; /* X2 = 10 S. */ 121 int sbc_wait_dreq_timo = 1000 * 5000; /* X2 = 10 S. */ 122 123 /* Return zero on success. */ 124 static __inline__ int 125 sbc_wait_busy(sc) 126 struct ncr5380_softc *sc; 127 { 128 int timo = sbc_wait_busy_timo; 129 for (;;) { 130 if (SCI_BUSY(sc)) { 131 timo = 0; /* return 0 */ 132 break; 133 } 134 if (--timo < 0) 135 break; /* return -1 */ 136 delay(2); 137 } 138 return (timo); 139 } 140 141 static __inline__ int 142 sbc_ready(sc) 143 struct ncr5380_softc *sc; 144 { 145 int timo = sbc_ready_timo; 146 147 for (;;) { 148 if ((*sc->sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) 149 == (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 150 timo = 0; 151 break; 152 } 153 if (((*sc->sci_csr & SCI_CSR_PHASE_MATCH) == 0) 154 || (SCI_BUSY(sc) == 0)) { 155 timo = -1; 156 break; 157 } 158 if (--timo < 0) 159 break; /* return -1 */ 160 delay(2); 161 } 162 return (timo); 163 } 164 165 static __inline__ int 166 sbc_wait_dreq(sc) 167 struct ncr5380_softc *sc; 168 { 169 int timo = sbc_wait_dreq_timo; 170 171 for (;;) { 172 if ((*sc->sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) 173 == (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 174 timo = 0; 175 break; 176 } 177 if (--timo < 0) 178 break; /* return -1 */ 179 delay(2); 180 } 181 return (timo); 182 } 183 184 void 185 sbc_irq_intr(p) 186 void *p; 187 { 188 struct ncr5380_softc *ncr_sc = p; 189 int claimed = 0; 190 191 /* How we ever arrive here without IRQ set is a mystery... */ 192 if (*ncr_sc->sci_csr & SCI_CSR_INT) { 193 #ifdef SBC_DEBUG 194 if (sbc_debug & SBC_DB_INTR) 195 decode_5380_intr(ncr_sc); 196 #endif 197 claimed = ncr5380_intr(ncr_sc); 198 if (!claimed) { 199 if (((*ncr_sc->sci_csr & ~SCI_CSR_PHASE_MATCH) == SCI_CSR_INT) 200 && ((*ncr_sc->sci_bus_csr & ~SCI_BUS_RST) == 0)) 201 SCI_CLR_INTR(ncr_sc); /* RST interrupt */ 202 #ifdef SBC_DEBUG 203 else { 204 printf("%s: spurious intr\n", 205 ncr_sc->sc_dev.dv_xname); 206 SBC_BREAK; 207 } 208 #endif 209 } 210 } 211 } 212 213 #ifdef SBC_DEBUG 214 void 215 decode_5380_intr(ncr_sc) 216 struct ncr5380_softc *ncr_sc; 217 { 218 u_int8_t csr = *ncr_sc->sci_csr; 219 u_int8_t bus_csr = *ncr_sc->sci_bus_csr; 220 221 if (((csr & ~(SCI_CSR_PHASE_MATCH | SCI_CSR_ATN)) == SCI_CSR_INT) && 222 ((bus_csr & ~(SCI_BUS_MSG | SCI_BUS_CD | SCI_BUS_IO | SCI_BUS_DBP)) == SCI_BUS_SEL)) { 223 if (csr & SCI_BUS_IO) 224 printf("%s: reselect\n", ncr_sc->sc_dev.dv_xname); 225 else 226 printf("%s: select\n", ncr_sc->sc_dev.dv_xname); 227 } else if (((csr & ~SCI_CSR_ACK) == (SCI_CSR_DONE | SCI_CSR_INT)) && 228 ((bus_csr & (SCI_BUS_RST | SCI_BUS_BSY | SCI_BUS_SEL)) == SCI_BUS_BSY)) 229 printf("%s: dma eop\n", ncr_sc->sc_dev.dv_xname); 230 else if (((csr & ~SCI_CSR_PHASE_MATCH) == SCI_CSR_INT) && 231 ((bus_csr & ~SCI_BUS_RST) == 0)) 232 printf("%s: bus reset\n", ncr_sc->sc_dev.dv_xname); 233 else if (((csr & ~(SCI_CSR_DREQ | SCI_CSR_ATN | SCI_CSR_ACK)) == (SCI_CSR_PERR | SCI_CSR_INT | SCI_CSR_PHASE_MATCH)) && 234 ((bus_csr & (SCI_BUS_RST | SCI_BUS_BSY | SCI_BUS_SEL)) == SCI_BUS_BSY)) 235 printf("%s: parity error\n", ncr_sc->sc_dev.dv_xname); 236 else if (((csr & ~SCI_CSR_ATN) == SCI_CSR_INT) && 237 ((bus_csr & (SCI_BUS_RST | SCI_BUS_BSY | SCI_BUS_REQ | SCI_BUS_SEL)) == (SCI_BUS_BSY | SCI_BUS_REQ))) 238 printf("%s: phase mismatch\n", ncr_sc->sc_dev.dv_xname); 239 else if (((csr & ~SCI_CSR_PHASE_MATCH) == (SCI_CSR_INT | SCI_CSR_DISC)) && 240 (bus_csr == 0)) 241 printf("%s: disconnect\n", ncr_sc->sc_dev.dv_xname); 242 else 243 printf("%s: unknown intr: csr=%x, bus_csr=%x\n", 244 ncr_sc->sc_dev.dv_xname, csr, bus_csr); 245 } 246 #endif 247 248 249 /*** 250 * The following code implements polled PDMA. 251 ***/ 252 253 int 254 sbc_pdma_in(ncr_sc, phase, datalen, data) 255 struct ncr5380_softc *ncr_sc; 256 int phase; 257 int datalen; 258 u_char *data; 259 { 260 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 261 volatile u_int32_t *long_data = (u_int32_t *)sc->sc_drq_addr; 262 volatile u_int8_t *byte_data = (u_int8_t *)sc->sc_nodrq_addr; 263 int resid, s; 264 265 if (datalen < ncr_sc->sc_min_dma_len || 266 (sc->sc_options & SBC_PDMA) == 0) 267 return ncr5380_pio_in(ncr_sc, phase, datalen, data); 268 269 s = splbio(); 270 if (sbc_wait_busy(ncr_sc)) { 271 splx(s); 272 return 0; 273 } 274 275 *ncr_sc->sci_mode |= SCI_MODE_DMA; 276 *ncr_sc->sci_irecv = 0; 277 278 #define R4 *((u_int32_t *)data)++ = *long_data 279 #define R1 *((u_int8_t *)data)++ = *byte_data 280 for (resid = datalen; resid >= 128; resid -= 128) { 281 if (sbc_ready(ncr_sc)) 282 goto interrupt; 283 R4; R4; R4; R4; R4; R4; R4; R4; 284 R4; R4; R4; R4; R4; R4; R4; R4; 285 R4; R4; R4; R4; R4; R4; R4; R4; 286 R4; R4; R4; R4; R4; R4; R4; R4; /* 128 */ 287 } 288 while (resid) { 289 if (sbc_ready(ncr_sc)) 290 goto interrupt; 291 R1; 292 resid--; 293 } 294 #undef R4 295 #undef R1 296 297 interrupt: 298 SCI_CLR_INTR(ncr_sc); 299 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 300 *ncr_sc->sci_icmd = 0; 301 splx(s); 302 return (datalen - resid); 303 } 304 305 int 306 sbc_pdma_out(ncr_sc, phase, datalen, data) 307 struct ncr5380_softc *ncr_sc; 308 int phase; 309 int datalen; 310 u_char *data; 311 { 312 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 313 volatile u_int32_t *long_data = (u_int32_t *)sc->sc_drq_addr; 314 volatile u_int8_t *byte_data = (u_int8_t *)sc->sc_nodrq_addr; 315 int resid, s; 316 u_int8_t icmd; 317 318 if (datalen < ncr_sc->sc_min_dma_len || 319 (sc->sc_options & SBC_PDMA) == 0) 320 return ncr5380_pio_out(ncr_sc, phase, datalen, data); 321 322 s = splbio(); 323 if (sbc_wait_busy(ncr_sc)) { 324 splx(s); 325 return 0; 326 } 327 328 icmd = *(ncr_sc->sci_icmd) & SCI_ICMD_RMASK; 329 *ncr_sc->sci_icmd = icmd | SCI_ICMD_DATA; 330 *ncr_sc->sci_mode |= SCI_MODE_DMA; 331 *ncr_sc->sci_dma_send = 0; 332 333 #define W1 *byte_data = *((u_int8_t *)data)++ 334 #define W4 *long_data = *((u_int32_t *)data)++ 335 for (resid = datalen; resid >= 64; resid -= 64) { 336 if (sbc_ready(ncr_sc)) 337 goto interrupt; 338 W1; 339 if (sbc_ready(ncr_sc)) 340 goto interrupt; 341 W1; 342 if (sbc_ready(ncr_sc)) 343 goto interrupt; 344 W1; 345 if (sbc_ready(ncr_sc)) 346 goto interrupt; 347 W1; 348 if (sbc_ready(ncr_sc)) 349 goto interrupt; 350 W4; W4; W4; W4; 351 W4; W4; W4; W4; 352 W4; W4; W4; W4; 353 W4; W4; W4; 354 } 355 while (resid) { 356 if (sbc_ready(ncr_sc)) 357 goto interrupt; 358 W1; 359 resid--; 360 } 361 #undef W1 362 #undef W4 363 if (sbc_wait_dreq(ncr_sc)) 364 printf("%s: timeout waiting for DREQ.\n", 365 ncr_sc->sc_dev.dv_xname); 366 367 *byte_data = 0; 368 goto done; 369 370 interrupt: 371 if ((*ncr_sc->sci_csr & SCI_CSR_PHASE_MATCH) == 0) { 372 *ncr_sc->sci_icmd = icmd & ~SCI_ICMD_DATA; 373 --resid; 374 } 375 376 done: 377 SCI_CLR_INTR(ncr_sc); 378 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 379 *ncr_sc->sci_icmd = icmd; 380 splx(s); 381 return (datalen - resid); 382 } 383 384 385 /*** 386 * The following code implements interrupt-driven PDMA. 387 ***/ 388 389 /* 390 * This is the meat of the PDMA transfer. 391 * When we get here, we shove data as fast as the mac can take it. 392 * We depend on several things: 393 * * All macs after the Mac Plus that have a 5380 chip should have a general 394 * logic IC that handshakes data for blind transfers. 395 * * If the SCSI controller finishes sending/receiving data before we do, 396 * the same general logic IC will generate a /BERR for us in short order. 397 * * The fault address for said /BERR minus the base address for the 398 * transfer will be the amount of data that was actually written. 399 * 400 * We use the nofault flag and the setjmp/longjmp in locore.s so we can 401 * detect and handle the bus error for early termination of a command. 402 * This is usually caused by a disconnecting target. 403 */ 404 void 405 sbc_drq_intr(p) 406 void *p; 407 { 408 extern int *nofault, m68k_fault_addr; 409 struct sbc_softc *sc = (struct sbc_softc *)p; 410 struct ncr5380_softc *ncr_sc = (struct ncr5380_softc *)p; 411 struct sci_req *sr = ncr_sc->sc_current; 412 struct sbc_pdma_handle *dh = sr->sr_dma_hand; 413 label_t faultbuf; 414 volatile u_int32_t *long_drq; 415 u_int32_t *long_data; 416 volatile u_int8_t *drq; 417 u_int8_t *data; 418 int count, dcount, resid; 419 u_int8_t tmp; 420 421 /* Work around lame gcc initialization bug */ 422 (void)&drq; 423 424 /* 425 * If we're not ready to xfer data, or have no more, just return. 426 */ 427 if ((*ncr_sc->sci_csr & SCI_CSR_DREQ) == 0 || dh->dh_len == 0) 428 return; 429 430 #ifdef SBC_DEBUG 431 if (sbc_debug & SBC_DB_INTR) 432 printf("%s: drq intr, dh_len=0x%x, dh_flags=0x%x\n", 433 ncr_sc->sc_dev.dv_xname, dh->dh_len, dh->dh_flags); 434 #endif 435 436 /* 437 * Setup for a possible bus error caused by SCSI controller 438 * switching out of DATA-IN/OUT before we're done with the 439 * current transfer. 440 */ 441 nofault = (int *)&faultbuf; 442 443 if (setjmp((label_t *)nofault)) { 444 nofault = (int *)0; 445 if ((dh->dh_flags & SBC_DH_DONE) == 0) { 446 count = (( (u_long)m68k_fault_addr 447 - (u_long)sc->sc_drq_addr)); 448 449 if ((count < 0) || (count > dh->dh_len)) { 450 printf("%s: complete=0x%x (pending 0x%x)\n", 451 ncr_sc->sc_dev.dv_xname, count, dh->dh_len); 452 panic("something is wrong"); 453 } 454 455 dh->dh_addr += count; 456 dh->dh_len -= count; 457 } else 458 count = 0; 459 460 #ifdef SBC_DEBUG 461 if (sbc_debug & SBC_DB_INTR) 462 printf("%s: drq /berr, complete=0x%x (pending 0x%x)\n", 463 ncr_sc->sc_dev.dv_xname, count, dh->dh_len); 464 #endif 465 m68k_fault_addr = 0; 466 467 return; 468 } 469 470 if (dh->dh_flags & SBC_DH_OUT) { /* Data Out */ 471 dcount = 0; 472 473 /* 474 * Get the source address aligned. 475 */ 476 resid = 477 count = min(dh->dh_len, 4 - (((int)dh->dh_addr) & 0x3)); 478 if (count && count < 4) { 479 drq = (volatile u_int8_t *)sc->sc_drq_addr; 480 data = (u_int8_t *)dh->dh_addr; 481 482 #define W1 *drq++ = *data++ 483 while (count) { 484 W1; count--; 485 } 486 #undef W1 487 dh->dh_addr += resid; 488 dh->dh_len -= resid; 489 } 490 491 /* 492 * Start the transfer. 493 */ 494 while (dh->dh_len) { 495 dcount = count = min(dh->dh_len, MAX_DMA_LEN); 496 long_drq = (volatile u_int32_t *)sc->sc_drq_addr; 497 long_data = (u_int32_t *)dh->dh_addr; 498 499 #define W4 *long_drq++ = *long_data++ 500 while (count >= 64) { 501 W4; W4; W4; W4; W4; W4; W4; W4; 502 W4; W4; W4; W4; W4; W4; W4; W4; /* 64 */ 503 count -= 64; 504 } 505 while (count >= 4) { 506 W4; count -= 4; 507 } 508 #undef W4 509 data = (u_int8_t *)long_data; 510 drq = (u_int8_t *)long_drq; 511 512 #define W1 *drq++ = *data++ 513 while (count) { 514 W1; count--; 515 } 516 #undef W1 517 dh->dh_len -= dcount; 518 dh->dh_addr += dcount; 519 } 520 dh->dh_flags |= SBC_DH_DONE; 521 522 /* 523 * XXX -- Read a byte from the SBC to trigger a /BERR. 524 * This seems to be necessary for us to notice that 525 * the target has disconnected. Ick. 06 jun 1996 (sr) 526 */ 527 if (dcount >= MAX_DMA_LEN) 528 drq = (volatile u_int8_t *)sc->sc_drq_addr; 529 tmp = *drq; 530 } else { /* Data In */ 531 /* 532 * Get the dest address aligned. 533 */ 534 resid = 535 count = min(dh->dh_len, 4 - (((int)dh->dh_addr) & 0x3)); 536 if (count && count < 4) { 537 data = (u_int8_t *)dh->dh_addr; 538 drq = (volatile u_int8_t *)sc->sc_drq_addr; 539 540 #define R1 *data++ = *drq++ 541 while (count) { 542 R1; count--; 543 } 544 #undef R1 545 dh->dh_addr += resid; 546 dh->dh_len -= resid; 547 } 548 549 /* 550 * Start the transfer. 551 */ 552 while (dh->dh_len) { 553 dcount = count = min(dh->dh_len, MAX_DMA_LEN); 554 long_data = (u_int32_t *)dh->dh_addr; 555 long_drq = (volatile u_int32_t *)sc->sc_drq_addr; 556 557 #define R4 *long_data++ = *long_drq++ 558 while (count >= 64) { 559 R4; R4; R4; R4; R4; R4; R4; R4; 560 R4; R4; R4; R4; R4; R4; R4; R4; /* 64 */ 561 count -= 64; 562 } 563 while (count >= 4) { 564 R4; count -= 4; 565 } 566 #undef R4 567 data = (u_int8_t *)long_data; 568 drq = (volatile u_int8_t *)long_drq; 569 570 #define R1 *data++ = *drq++ 571 while (count) { 572 R1; count--; 573 } 574 #undef R1 575 dh->dh_len -= dcount; 576 dh->dh_addr += dcount; 577 } 578 dh->dh_flags |= SBC_DH_DONE; 579 } 580 581 /* 582 * OK. No bus error occurred above. Clear the nofault flag 583 * so we no longer short-circuit bus errors. 584 */ 585 nofault = (int *)0; 586 587 #ifdef SBC_DEBUG 588 if (sbc_debug & (SBC_DB_REG | SBC_DB_INTR)) 589 printf("%s: drq intr complete: csr=0x%x, bus_csr=0x%x\n", 590 ncr_sc->sc_dev.dv_xname, *ncr_sc->sci_csr, 591 *ncr_sc->sci_bus_csr); 592 #endif 593 } 594 595 void 596 sbc_dma_alloc(ncr_sc) 597 struct ncr5380_softc *ncr_sc; 598 { 599 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 600 struct sci_req *sr = ncr_sc->sc_current; 601 struct scsipi_xfer *xs = sr->sr_xs; 602 struct sbc_pdma_handle *dh; 603 int i, xlen; 604 605 #ifdef DIAGNOSTIC 606 if (sr->sr_dma_hand != NULL) 607 panic("sbc_dma_alloc: already have PDMA handle"); 608 #endif 609 610 /* Polled transfers shouldn't allocate a PDMA handle. */ 611 if (sr->sr_flags & SR_IMMED) 612 return; 613 614 xlen = ncr_sc->sc_datalen; 615 616 /* Make sure our caller checked sc_min_dma_len. */ 617 if (xlen < MIN_DMA_LEN) 618 panic("sbc_dma_alloc: len=0x%x\n", xlen); 619 620 /* 621 * Find free PDMA handle. Guaranteed to find one since we 622 * have as many PDMA handles as the driver has processes. 623 * (instances?) 624 */ 625 for (i = 0; i < SCI_OPENINGS; i++) { 626 if ((sc->sc_pdma[i].dh_flags & SBC_DH_BUSY) == 0) 627 goto found; 628 } 629 panic("sbc: no free PDMA handles"); 630 found: 631 dh = &sc->sc_pdma[i]; 632 dh->dh_flags = SBC_DH_BUSY; 633 dh->dh_addr = ncr_sc->sc_dataptr; 634 dh->dh_len = xlen; 635 636 /* Copy the 'write' flag for convenience. */ 637 if (xs->flags & SCSI_DATA_OUT) 638 dh->dh_flags |= SBC_DH_OUT; 639 640 sr->sr_dma_hand = dh; 641 } 642 643 void 644 sbc_dma_free(ncr_sc) 645 struct ncr5380_softc *ncr_sc; 646 { 647 struct sci_req *sr = ncr_sc->sc_current; 648 struct sbc_pdma_handle *dh = sr->sr_dma_hand; 649 650 #ifdef DIAGNOSTIC 651 if (sr->sr_dma_hand == NULL) 652 panic("sbc_dma_free: no DMA handle"); 653 #endif 654 655 if (ncr_sc->sc_state & NCR_DOINGDMA) 656 panic("sbc_dma_free: free while in progress"); 657 658 if (dh->dh_flags & SBC_DH_BUSY) { 659 dh->dh_flags = 0; 660 dh->dh_addr = NULL; 661 dh->dh_len = 0; 662 } 663 sr->sr_dma_hand = NULL; 664 } 665 666 void 667 sbc_dma_poll(ncr_sc) 668 struct ncr5380_softc *ncr_sc; 669 { 670 struct sci_req *sr = ncr_sc->sc_current; 671 672 /* 673 * We shouldn't arrive here; if SR_IMMED is set, then 674 * dma_alloc() should have refused to allocate a handle 675 * for the transfer. This forces the polled PDMA code 676 * to handle the request... 677 */ 678 #ifdef SBC_DEBUG 679 if (sbc_debug & SBC_DB_DMA) 680 printf("%s: lost DRQ interrupt?\n", ncr_sc->sc_dev.dv_xname); 681 #endif 682 sr->sr_flags |= SR_OVERDUE; 683 } 684 685 void 686 sbc_dma_setup(ncr_sc) 687 struct ncr5380_softc *ncr_sc; 688 { 689 /* Not needed; we don't have real DMA */ 690 } 691 692 void 693 sbc_dma_start(ncr_sc) 694 struct ncr5380_softc *ncr_sc; 695 { 696 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 697 struct sci_req *sr = ncr_sc->sc_current; 698 struct sbc_pdma_handle *dh = sr->sr_dma_hand; 699 700 /* 701 * Match bus phase, clear pending interrupts, set DMA mode, and 702 * assert data bus (for writing only), then start the transfer. 703 */ 704 if (dh->dh_flags & SBC_DH_OUT) { 705 *ncr_sc->sci_tcmd = PHASE_DATA_OUT; 706 SCI_CLR_INTR(ncr_sc); 707 if (sc->sc_clrintr) 708 (*sc->sc_clrintr)(ncr_sc); 709 *ncr_sc->sci_mode |= SCI_MODE_DMA; 710 *ncr_sc->sci_icmd = SCI_ICMD_DATA; 711 *ncr_sc->sci_dma_send = 0; 712 } else { 713 *ncr_sc->sci_tcmd = PHASE_DATA_IN; 714 SCI_CLR_INTR(ncr_sc); 715 if (sc->sc_clrintr) 716 (*sc->sc_clrintr)(ncr_sc); 717 *ncr_sc->sci_mode |= SCI_MODE_DMA; 718 *ncr_sc->sci_icmd = 0; 719 *ncr_sc->sci_irecv = 0; 720 } 721 ncr_sc->sc_state |= NCR_DOINGDMA; 722 723 #ifdef SBC_DEBUG 724 if (sbc_debug & SBC_DB_DMA) 725 printf("%s: PDMA started, va=%p, len=0x%x\n", 726 ncr_sc->sc_dev.dv_xname, dh->dh_addr, dh->dh_len); 727 #endif 728 } 729 730 void 731 sbc_dma_eop(ncr_sc) 732 struct ncr5380_softc *ncr_sc; 733 { 734 /* Not used; the EOP pin is wired high (GMFH, pp. 389-390) */ 735 } 736 737 void 738 sbc_dma_stop(ncr_sc) 739 struct ncr5380_softc *ncr_sc; 740 { 741 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 742 struct sci_req *sr = ncr_sc->sc_current; 743 struct sbc_pdma_handle *dh = sr->sr_dma_hand; 744 int ntrans; 745 746 if ((ncr_sc->sc_state & NCR_DOINGDMA) == 0) { 747 #ifdef SBC_DEBUG 748 if (sbc_debug & SBC_DB_DMA) 749 printf("%s: dma_stop: DMA not running\n", 750 ncr_sc->sc_dev.dv_xname); 751 #endif 752 return; 753 } 754 ncr_sc->sc_state &= ~NCR_DOINGDMA; 755 756 if ((ncr_sc->sc_state & NCR_ABORTING) == 0) { 757 ntrans = ncr_sc->sc_datalen - dh->dh_len; 758 759 #ifdef SBC_DEBUG 760 if (sbc_debug & SBC_DB_DMA) 761 printf("%s: dma_stop: ntrans=0x%x\n", 762 ncr_sc->sc_dev.dv_xname, ntrans); 763 #endif 764 765 if (ntrans > ncr_sc->sc_datalen) 766 panic("sbc_dma_stop: excess transfer\n"); 767 768 /* Adjust data pointer */ 769 ncr_sc->sc_dataptr += ntrans; 770 ncr_sc->sc_datalen -= ntrans; 771 772 /* Clear any pending interrupts. */ 773 SCI_CLR_INTR(ncr_sc); 774 if (sc->sc_clrintr) 775 (*sc->sc_clrintr)(ncr_sc); 776 } 777 778 /* Put SBIC back into PIO mode. */ 779 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 780 *ncr_sc->sci_icmd = 0; 781 782 #ifdef SBC_DEBUG 783 if (sbc_debug & SBC_DB_REG) 784 printf("%s: dma_stop: csr=0x%x, bus_csr=0x%x\n", 785 ncr_sc->sc_dev.dv_xname, *ncr_sc->sci_csr, 786 *ncr_sc->sci_bus_csr); 787 #endif 788 } 789
Indexes created Tue Sep 23 20:09:58 GMT 2025