sbc.c revision 1.32
1 /* $NetBSD: sbc.c,v 1.32 1997/10/10 05:55:01 scottr Exp $ */ 2 3 /* 4 * Copyright (C) 1996 Scott Reynolds. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * This file contains only the machine-dependent parts of the mac68k 31 * NCR 5380 SCSI driver. (Autoconfig stuff and PDMA functions.) 32 * The machine-independent parts are in ncr5380sbc.c 33 * 34 * Supported hardware includes: 35 * Macintosh II family 5380-based controller 36 * 37 * Credits, history: 38 * 39 * Scott Reynolds wrote this module, based on work by Allen Briggs 40 * (mac68k), Gordon W. Ross and David Jones (sun3), and Leo Weppelman 41 * (atari). Thanks to Allen for supplying crucial interpretation of the 42 * NetBSD/mac68k 1.1 'ncrscsi' driver. Also, Allen, Gordon, and Jason 43 * Thorpe all helped to refine this code, and were considerable sources 44 * of moral support. 45 */ 46 47 #include <sys/types.h> 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/kernel.h> 51 #include <sys/errno.h> 52 #include <sys/device.h> 53 #include <sys/buf.h> 54 #include <sys/proc.h> 55 #include <sys/user.h> 56 57 #include <dev/scsipi/scsi_all.h> 58 #include <dev/scsipi/scsipi_all.h> 59 #include <dev/scsipi/scsipi_debug.h> 60 #include <dev/scsipi/scsiconf.h> 61 62 #include <dev/ic/ncr5380reg.h> 63 #include <dev/ic/ncr5380var.h> 64 65 #include <machine/cpu.h> 66 #include <machine/viareg.h> 67 68 #include <mac68k/dev/sbcreg.h> 69 #include <mac68k/dev/sbcvar.h> 70 71 int sbc_debug = 0 /* | SBC_DB_INTR | SBC_DB_DMA */; 72 int sbc_link_flags = 0 /* | SDEV_DB2 */; 73 int sbc_options = 0 /* | SBC_PDMA */; 74 75 static void sbc_minphys __P((struct buf *bp)); 76 77 struct scsipi_adapter sbc_ops = { 78 ncr5380_scsi_cmd, /* scsi_cmd() */ 79 sbc_minphys, /* scsi_minphys() */ 80 NULL, /* open_target_lu() */ 81 NULL, /* close_target_lu() */ 82 }; 83 84 /* This is copied from julian's bt driver */ 85 /* "so we have a default dev struct for our link struct." */ 86 struct scsipi_device sbc_dev = { 87 NULL, /* Use default error handler. */ 88 NULL, /* Use default start handler. */ 89 NULL, /* Use default async handler. */ 90 NULL, /* Use default "done" routine. */ 91 }; 92 93 struct cfdriver sbc_cd = { 94 NULL, "sbc", DV_DULL 95 }; 96 97 extern label_t *nofault; 98 extern caddr_t m68k_fault_addr; 99 100 static int sbc_wait_busy __P((struct ncr5380_softc *)); 101 static int sbc_ready __P((struct ncr5380_softc *)); 102 static int sbc_wait_dreq __P((struct ncr5380_softc *)); 103 104 static void 105 sbc_minphys(struct buf *bp) 106 { 107 if (bp->b_bcount > MAX_DMA_LEN) 108 bp->b_bcount = MAX_DMA_LEN; 109 return (minphys(bp)); 110 } 111 112 113 /*** 114 * General support for Mac-specific SCSI logic. 115 ***/ 116 117 /* These are used in the following inline functions. */ 118 int sbc_wait_busy_timo = 1000 * 5000; /* X2 = 10 S. */ 119 int sbc_ready_timo = 1000 * 5000; /* X2 = 10 S. */ 120 int sbc_wait_dreq_timo = 1000 * 5000; /* X2 = 10 S. */ 121 122 /* Return zero on success. */ 123 static __inline__ int 124 sbc_wait_busy(sc) 125 struct ncr5380_softc *sc; 126 { 127 int timo = sbc_wait_busy_timo; 128 for (;;) { 129 if (SCI_BUSY(sc)) { 130 timo = 0; /* return 0 */ 131 break; 132 } 133 if (--timo < 0) 134 break; /* return -1 */ 135 delay(2); 136 } 137 return (timo); 138 } 139 140 static __inline__ int 141 sbc_ready(sc) 142 struct ncr5380_softc *sc; 143 { 144 int timo = sbc_ready_timo; 145 146 for (;;) { 147 if ((*sc->sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) 148 == (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 149 timo = 0; 150 break; 151 } 152 if (((*sc->sci_csr & SCI_CSR_PHASE_MATCH) == 0) 153 || (SCI_BUSY(sc) == 0)) { 154 timo = -1; 155 break; 156 } 157 if (--timo < 0) 158 break; /* return -1 */ 159 delay(2); 160 } 161 return (timo); 162 } 163 164 static __inline__ int 165 sbc_wait_dreq(sc) 166 struct ncr5380_softc *sc; 167 { 168 int timo = sbc_wait_dreq_timo; 169 170 for (;;) { 171 if ((*sc->sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) 172 == (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 173 timo = 0; 174 break; 175 } 176 if (--timo < 0) 177 break; /* return -1 */ 178 delay(2); 179 } 180 return (timo); 181 } 182 183 void 184 sbc_irq_intr(p) 185 void *p; 186 { 187 struct ncr5380_softc *ncr_sc = p; 188 int claimed = 0; 189 190 /* How we ever arrive here without IRQ set is a mystery... */ 191 if (*ncr_sc->sci_csr & SCI_CSR_INT) { 192 #ifdef SBC_DEBUG 193 if (sbc_debug & SBC_DB_INTR) 194 decode_5380_intr(ncr_sc); 195 #endif 196 claimed = ncr5380_intr(ncr_sc); 197 if (!claimed) { 198 if (((*ncr_sc->sci_csr & ~SCI_CSR_PHASE_MATCH) == SCI_CSR_INT) 199 && ((*ncr_sc->sci_bus_csr & ~SCI_BUS_RST) == 0)) 200 SCI_CLR_INTR(ncr_sc); /* RST interrupt */ 201 #ifdef SBC_DEBUG 202 else { 203 printf("%s: spurious intr\n", 204 ncr_sc->sc_dev.dv_xname); 205 SBC_BREAK; 206 } 207 #endif 208 } 209 } 210 } 211 212 #ifdef SBC_DEBUG 213 void 214 decode_5380_intr(ncr_sc) 215 struct ncr5380_softc *ncr_sc; 216 { 217 u_int8_t csr = *ncr_sc->sci_csr; 218 u_int8_t bus_csr = *ncr_sc->sci_bus_csr; 219 220 if (((csr & ~(SCI_CSR_PHASE_MATCH | SCI_CSR_ATN)) == SCI_CSR_INT) && 221 ((bus_csr & ~(SCI_BUS_MSG | SCI_BUS_CD | SCI_BUS_IO | SCI_BUS_DBP)) == SCI_BUS_SEL)) { 222 if (csr & SCI_BUS_IO) 223 printf("%s: reselect\n", ncr_sc->sc_dev.dv_xname); 224 else 225 printf("%s: select\n", ncr_sc->sc_dev.dv_xname); 226 } else if (((csr & ~SCI_CSR_ACK) == (SCI_CSR_DONE | SCI_CSR_INT)) && 227 ((bus_csr & (SCI_BUS_RST | SCI_BUS_BSY | SCI_BUS_SEL)) == SCI_BUS_BSY)) 228 printf("%s: dma eop\n", ncr_sc->sc_dev.dv_xname); 229 else if (((csr & ~SCI_CSR_PHASE_MATCH) == SCI_CSR_INT) && 230 ((bus_csr & ~SCI_BUS_RST) == 0)) 231 printf("%s: bus reset\n", ncr_sc->sc_dev.dv_xname); 232 else if (((csr & ~(SCI_CSR_DREQ | SCI_CSR_ATN | SCI_CSR_ACK)) == (SCI_CSR_PERR | SCI_CSR_INT | SCI_CSR_PHASE_MATCH)) && 233 ((bus_csr & (SCI_BUS_RST | SCI_BUS_BSY | SCI_BUS_SEL)) == SCI_BUS_BSY)) 234 printf("%s: parity error\n", ncr_sc->sc_dev.dv_xname); 235 else if (((csr & ~SCI_CSR_ATN) == SCI_CSR_INT) && 236 ((bus_csr & (SCI_BUS_RST | SCI_BUS_BSY | SCI_BUS_REQ | SCI_BUS_SEL)) == (SCI_BUS_BSY | SCI_BUS_REQ))) 237 printf("%s: phase mismatch\n", ncr_sc->sc_dev.dv_xname); 238 else if (((csr & ~SCI_CSR_PHASE_MATCH) == (SCI_CSR_INT | SCI_CSR_DISC)) && 239 (bus_csr == 0)) 240 printf("%s: disconnect\n", ncr_sc->sc_dev.dv_xname); 241 else 242 printf("%s: unknown intr: csr=%x, bus_csr=%x\n", 243 ncr_sc->sc_dev.dv_xname, csr, bus_csr); 244 } 245 #endif 246 247 248 /*** 249 * The following code implements polled PDMA. 250 ***/ 251 252 int 253 sbc_pdma_in(ncr_sc, phase, datalen, data) 254 struct ncr5380_softc *ncr_sc; 255 int phase; 256 int datalen; 257 u_char *data; 258 { 259 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 260 volatile u_int32_t *long_data = (u_int32_t *)sc->sc_drq_addr; 261 volatile u_int8_t *byte_data = (u_int8_t *)sc->sc_nodrq_addr; 262 int resid, s; 263 264 if (datalen < ncr_sc->sc_min_dma_len || 265 (sc->sc_options & SBC_PDMA) == 0) 266 return ncr5380_pio_in(ncr_sc, phase, datalen, data); 267 268 s = splbio(); 269 if (sbc_wait_busy(ncr_sc)) { 270 splx(s); 271 return 0; 272 } 273 274 *ncr_sc->sci_mode |= SCI_MODE_DMA; 275 *ncr_sc->sci_irecv = 0; 276 277 #define R4 *((u_int32_t *)data)++ = *long_data 278 #define R1 *((u_int8_t *)data)++ = *byte_data 279 for (resid = datalen; resid >= 128; resid -= 128) { 280 if (sbc_ready(ncr_sc)) 281 goto interrupt; 282 R4; R4; R4; R4; R4; R4; R4; R4; 283 R4; R4; R4; R4; R4; R4; R4; R4; 284 R4; R4; R4; R4; R4; R4; R4; R4; 285 R4; R4; R4; R4; R4; R4; R4; R4; /* 128 */ 286 } 287 while (resid) { 288 if (sbc_ready(ncr_sc)) 289 goto interrupt; 290 R1; 291 resid--; 292 } 293 #undef R4 294 #undef R1 295 296 interrupt: 297 SCI_CLR_INTR(ncr_sc); 298 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 299 *ncr_sc->sci_icmd = 0; 300 splx(s); 301 return (datalen - resid); 302 } 303 304 int 305 sbc_pdma_out(ncr_sc, phase, datalen, data) 306 struct ncr5380_softc *ncr_sc; 307 int phase; 308 int datalen; 309 u_char *data; 310 { 311 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 312 volatile u_int32_t *long_data = (u_int32_t *)sc->sc_drq_addr; 313 volatile u_int8_t *byte_data = (u_int8_t *)sc->sc_nodrq_addr; 314 label_t faultbuf; 315 int resid, s; 316 u_int8_t icmd; 317 318 #if 1 319 /* Work around lame gcc initialization bug */ 320 (void)&data; 321 #endif 322 323 if (datalen < ncr_sc->sc_min_dma_len || 324 (sc->sc_options & SBC_PDMA) == 0) 325 return ncr5380_pio_out(ncr_sc, phase, datalen, data); 326 327 s = splbio(); 328 if (sbc_wait_busy(ncr_sc)) { 329 splx(s); 330 return 0; 331 } 332 333 icmd = *(ncr_sc->sci_icmd) & SCI_ICMD_RMASK; 334 *ncr_sc->sci_icmd = icmd | SCI_ICMD_DATA; 335 *ncr_sc->sci_mode |= SCI_MODE_DMA; 336 *ncr_sc->sci_dma_send = 0; 337 338 /* 339 * Setup for a possible bus error caused by SCSI controller 340 * switching out of DATA OUT before we're done with the 341 * current transfer. (See comment before sbc_drq_intr().) 342 */ 343 nofault = &faultbuf; 344 345 if (setjmp(nofault)) { 346 printf("buf = 0x%lx, fault = 0x%lx\n", 347 (u_long)sc->sc_drq_addr, (u_long)m68k_fault_addr); 348 panic("Unexpected bus error in sbc_pdma_out()"); 349 } 350 351 #define W1 *byte_data = *((u_int8_t *)data)++ 352 #define W4 *long_data = *((u_int32_t *)data)++ 353 for (resid = datalen; resid >= 64; resid -= 64) { 354 if (sbc_ready(ncr_sc)) 355 goto interrupt; 356 W1; 357 if (sbc_ready(ncr_sc)) 358 goto interrupt; 359 W1; 360 if (sbc_ready(ncr_sc)) 361 goto interrupt; 362 W1; 363 if (sbc_ready(ncr_sc)) 364 goto interrupt; 365 W1; 366 if (sbc_ready(ncr_sc)) 367 goto interrupt; 368 W4; W4; W4; W4; 369 W4; W4; W4; W4; 370 W4; W4; W4; W4; 371 W4; W4; W4; 372 } 373 while (resid) { 374 if (sbc_ready(ncr_sc)) 375 goto interrupt; 376 W1; 377 resid--; 378 } 379 #undef W1 380 #undef W4 381 if (sbc_wait_dreq(ncr_sc)) 382 printf("%s: timeout waiting for DREQ.\n", 383 ncr_sc->sc_dev.dv_xname); 384 385 *byte_data = 0; 386 goto done; 387 388 interrupt: 389 if ((*ncr_sc->sci_csr & SCI_CSR_PHASE_MATCH) == 0) { 390 *ncr_sc->sci_icmd = icmd & ~SCI_ICMD_DATA; 391 --resid; 392 } 393 394 done: 395 SCI_CLR_INTR(ncr_sc); 396 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 397 *ncr_sc->sci_icmd = icmd; 398 splx(s); 399 return (datalen - resid); 400 } 401 402 403 /*** 404 * The following code implements interrupt-driven PDMA. 405 ***/ 406 407 /* 408 * This is the meat of the PDMA transfer. 409 * When we get here, we shove data as fast as the mac can take it. 410 * We depend on several things: 411 * * All macs after the Mac Plus that have a 5380 chip should have a general 412 * logic IC that handshakes data for blind transfers. 413 * * If the SCSI controller finishes sending/receiving data before we do, 414 * the same general logic IC will generate a /BERR for us in short order. 415 * * The fault address for said /BERR minus the base address for the 416 * transfer will be the amount of data that was actually written. 417 * 418 * We use the nofault flag and the setjmp/longjmp in locore.s so we can 419 * detect and handle the bus error for early termination of a command. 420 * This is usually caused by a disconnecting target. 421 */ 422 void 423 sbc_drq_intr(p) 424 void *p; 425 { 426 struct sbc_softc *sc = (struct sbc_softc *)p; 427 struct ncr5380_softc *ncr_sc = (struct ncr5380_softc *)p; 428 struct sci_req *sr = ncr_sc->sc_current; 429 struct sbc_pdma_handle *dh = sr->sr_dma_hand; 430 label_t faultbuf; 431 volatile u_int32_t *long_drq; 432 u_int32_t *long_data; 433 volatile u_int8_t *drq; 434 u_int8_t *data; 435 int count, dcount, resid; 436 u_int8_t tmp; 437 438 /* Work around lame gcc initialization bug */ 439 (void)&drq; 440 441 /* 442 * If we're not ready to xfer data, or have no more, just return. 443 */ 444 if ((*ncr_sc->sci_csr & SCI_CSR_DREQ) == 0 || dh->dh_len == 0) 445 return; 446 447 #ifdef SBC_DEBUG 448 if (sbc_debug & SBC_DB_INTR) 449 printf("%s: drq intr, dh_len=0x%x, dh_flags=0x%x\n", 450 ncr_sc->sc_dev.dv_xname, dh->dh_len, dh->dh_flags); 451 #endif 452 453 /* 454 * Setup for a possible bus error caused by SCSI controller 455 * switching out of DATA-IN/OUT before we're done with the 456 * current transfer. 457 */ 458 nofault = &faultbuf; 459 460 if (setjmp((label_t *)nofault)) { 461 nofault = (label_t *)0; 462 if ((dh->dh_flags & SBC_DH_DONE) == 0) { 463 count = (( (u_long)m68k_fault_addr 464 - (u_long)sc->sc_drq_addr)); 465 466 if ((count < 0) || (count > dh->dh_len)) { 467 printf("%s: complete=0x%x (pending 0x%x)\n", 468 ncr_sc->sc_dev.dv_xname, count, dh->dh_len); 469 panic("something is wrong"); 470 } 471 472 dh->dh_addr += count; 473 dh->dh_len -= count; 474 } else 475 count = 0; 476 477 #ifdef SBC_DEBUG 478 if (sbc_debug & SBC_DB_INTR) 479 printf("%s: drq /berr, complete=0x%x (pending 0x%x)\n", 480 ncr_sc->sc_dev.dv_xname, count, dh->dh_len); 481 #endif 482 m68k_fault_addr = 0; 483 484 return; 485 } 486 487 if (dh->dh_flags & SBC_DH_OUT) { /* Data Out */ 488 dcount = 0; 489 490 /* 491 * Get the source address aligned. 492 */ 493 resid = 494 count = min(dh->dh_len, 4 - (((int)dh->dh_addr) & 0x3)); 495 if (count && count < 4) { 496 drq = (volatile u_int8_t *)sc->sc_drq_addr; 497 data = (u_int8_t *)dh->dh_addr; 498 499 #define W1 *drq++ = *data++ 500 while (count) { 501 W1; count--; 502 } 503 #undef W1 504 dh->dh_addr += resid; 505 dh->dh_len -= resid; 506 } 507 508 /* 509 * Start the transfer. 510 */ 511 while (dh->dh_len) { 512 dcount = count = min(dh->dh_len, MAX_DMA_LEN); 513 long_drq = (volatile u_int32_t *)sc->sc_drq_addr; 514 long_data = (u_int32_t *)dh->dh_addr; 515 516 #define W4 *long_drq++ = *long_data++ 517 while (count >= 64) { 518 W4; W4; W4; W4; W4; W4; W4; W4; 519 W4; W4; W4; W4; W4; W4; W4; W4; /* 64 */ 520 count -= 64; 521 } 522 while (count >= 4) { 523 W4; count -= 4; 524 } 525 #undef W4 526 data = (u_int8_t *)long_data; 527 drq = (u_int8_t *)long_drq; 528 529 #define W1 *drq++ = *data++ 530 while (count) { 531 W1; count--; 532 } 533 #undef W1 534 dh->dh_len -= dcount; 535 dh->dh_addr += dcount; 536 } 537 dh->dh_flags |= SBC_DH_DONE; 538 539 /* 540 * XXX -- Read a byte from the SBC to trigger a /BERR. 541 * This seems to be necessary for us to notice that 542 * the target has disconnected. Ick. 06 jun 1996 (sr) 543 */ 544 if (dcount >= MAX_DMA_LEN) 545 drq = (volatile u_int8_t *)sc->sc_drq_addr; 546 tmp = *drq; 547 } else { /* Data In */ 548 /* 549 * Get the dest address aligned. 550 */ 551 resid = 552 count = min(dh->dh_len, 4 - (((int)dh->dh_addr) & 0x3)); 553 if (count && count < 4) { 554 data = (u_int8_t *)dh->dh_addr; 555 drq = (volatile u_int8_t *)sc->sc_drq_addr; 556 557 #define R1 *data++ = *drq++ 558 while (count) { 559 R1; count--; 560 } 561 #undef R1 562 dh->dh_addr += resid; 563 dh->dh_len -= resid; 564 } 565 566 /* 567 * Start the transfer. 568 */ 569 while (dh->dh_len) { 570 dcount = count = min(dh->dh_len, MAX_DMA_LEN); 571 long_data = (u_int32_t *)dh->dh_addr; 572 long_drq = (volatile u_int32_t *)sc->sc_drq_addr; 573 574 #define R4 *long_data++ = *long_drq++ 575 while (count >= 64) { 576 R4; R4; R4; R4; R4; R4; R4; R4; 577 R4; R4; R4; R4; R4; R4; R4; R4; /* 64 */ 578 count -= 64; 579 } 580 while (count >= 4) { 581 R4; count -= 4; 582 } 583 #undef R4 584 data = (u_int8_t *)long_data; 585 drq = (volatile u_int8_t *)long_drq; 586 587 #define R1 *data++ = *drq++ 588 while (count) { 589 R1; count--; 590 } 591 #undef R1 592 dh->dh_len -= dcount; 593 dh->dh_addr += dcount; 594 } 595 dh->dh_flags |= SBC_DH_DONE; 596 } 597 598 /* 599 * OK. No bus error occurred above. Clear the nofault flag 600 * so we no longer short-circuit bus errors. 601 */ 602 nofault = (label_t *)0; 603 604 #ifdef SBC_DEBUG 605 if (sbc_debug & (SBC_DB_REG | SBC_DB_INTR)) 606 printf("%s: drq intr complete: csr=0x%x, bus_csr=0x%x\n", 607 ncr_sc->sc_dev.dv_xname, *ncr_sc->sci_csr, 608 *ncr_sc->sci_bus_csr); 609 #endif 610 } 611 612 void 613 sbc_dma_alloc(ncr_sc) 614 struct ncr5380_softc *ncr_sc; 615 { 616 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 617 struct sci_req *sr = ncr_sc->sc_current; 618 struct scsipi_xfer *xs = sr->sr_xs; 619 struct sbc_pdma_handle *dh; 620 int i, xlen; 621 622 #ifdef DIAGNOSTIC 623 if (sr->sr_dma_hand != NULL) 624 panic("sbc_dma_alloc: already have PDMA handle"); 625 #endif 626 627 /* Polled transfers shouldn't allocate a PDMA handle. */ 628 if (sr->sr_flags & SR_IMMED) 629 return; 630 631 xlen = ncr_sc->sc_datalen; 632 633 /* Make sure our caller checked sc_min_dma_len. */ 634 if (xlen < MIN_DMA_LEN) 635 panic("sbc_dma_alloc: len=0x%x\n", xlen); 636 637 /* 638 * Find free PDMA handle. Guaranteed to find one since we 639 * have as many PDMA handles as the driver has processes. 640 * (instances?) 641 */ 642 for (i = 0; i < SCI_OPENINGS; i++) { 643 if ((sc->sc_pdma[i].dh_flags & SBC_DH_BUSY) == 0) 644 goto found; 645 } 646 panic("sbc: no free PDMA handles"); 647 found: 648 dh = &sc->sc_pdma[i]; 649 dh->dh_flags = SBC_DH_BUSY; 650 dh->dh_addr = ncr_sc->sc_dataptr; 651 dh->dh_len = xlen; 652 653 /* Copy the 'write' flag for convenience. */ 654 if (xs->flags & SCSI_DATA_OUT) 655 dh->dh_flags |= SBC_DH_OUT; 656 657 sr->sr_dma_hand = dh; 658 } 659 660 void 661 sbc_dma_free(ncr_sc) 662 struct ncr5380_softc *ncr_sc; 663 { 664 struct sci_req *sr = ncr_sc->sc_current; 665 struct sbc_pdma_handle *dh = sr->sr_dma_hand; 666 667 #ifdef DIAGNOSTIC 668 if (sr->sr_dma_hand == NULL) 669 panic("sbc_dma_free: no DMA handle"); 670 #endif 671 672 if (ncr_sc->sc_state & NCR_DOINGDMA) 673 panic("sbc_dma_free: free while in progress"); 674 675 if (dh->dh_flags & SBC_DH_BUSY) { 676 dh->dh_flags = 0; 677 dh->dh_addr = NULL; 678 dh->dh_len = 0; 679 } 680 sr->sr_dma_hand = NULL; 681 } 682 683 void 684 sbc_dma_poll(ncr_sc) 685 struct ncr5380_softc *ncr_sc; 686 { 687 struct sci_req *sr = ncr_sc->sc_current; 688 689 /* 690 * We shouldn't arrive here; if SR_IMMED is set, then 691 * dma_alloc() should have refused to allocate a handle 692 * for the transfer. This forces the polled PDMA code 693 * to handle the request... 694 */ 695 #ifdef SBC_DEBUG 696 if (sbc_debug & SBC_DB_DMA) 697 printf("%s: lost DRQ interrupt?\n", ncr_sc->sc_dev.dv_xname); 698 #endif 699 sr->sr_flags |= SR_OVERDUE; 700 } 701 702 void 703 sbc_dma_setup(ncr_sc) 704 struct ncr5380_softc *ncr_sc; 705 { 706 /* Not needed; we don't have real DMA */ 707 } 708 709 void 710 sbc_dma_start(ncr_sc) 711 struct ncr5380_softc *ncr_sc; 712 { 713 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 714 struct sci_req *sr = ncr_sc->sc_current; 715 struct sbc_pdma_handle *dh = sr->sr_dma_hand; 716 717 /* 718 * Match bus phase, clear pending interrupts, set DMA mode, and 719 * assert data bus (for writing only), then start the transfer. 720 */ 721 if (dh->dh_flags & SBC_DH_OUT) { 722 *ncr_sc->sci_tcmd = PHASE_DATA_OUT; 723 SCI_CLR_INTR(ncr_sc); 724 if (sc->sc_clrintr) 725 (*sc->sc_clrintr)(ncr_sc); 726 *ncr_sc->sci_mode |= SCI_MODE_DMA; 727 *ncr_sc->sci_icmd = SCI_ICMD_DATA; 728 *ncr_sc->sci_dma_send = 0; 729 } else { 730 *ncr_sc->sci_tcmd = PHASE_DATA_IN; 731 SCI_CLR_INTR(ncr_sc); 732 if (sc->sc_clrintr) 733 (*sc->sc_clrintr)(ncr_sc); 734 *ncr_sc->sci_mode |= SCI_MODE_DMA; 735 *ncr_sc->sci_icmd = 0; 736 *ncr_sc->sci_irecv = 0; 737 } 738 ncr_sc->sc_state |= NCR_DOINGDMA; 739 740 #ifdef SBC_DEBUG 741 if (sbc_debug & SBC_DB_DMA) 742 printf("%s: PDMA started, va=%p, len=0x%x\n", 743 ncr_sc->sc_dev.dv_xname, dh->dh_addr, dh->dh_len); 744 #endif 745 } 746 747 void 748 sbc_dma_eop(ncr_sc) 749 struct ncr5380_softc *ncr_sc; 750 { 751 /* Not used; the EOP pin is wired high (GMFH, pp. 389-390) */ 752 } 753 754 void 755 sbc_dma_stop(ncr_sc) 756 struct ncr5380_softc *ncr_sc; 757 { 758 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 759 struct sci_req *sr = ncr_sc->sc_current; 760 struct sbc_pdma_handle *dh = sr->sr_dma_hand; 761 int ntrans; 762 763 if ((ncr_sc->sc_state & NCR_DOINGDMA) == 0) { 764 #ifdef SBC_DEBUG 765 if (sbc_debug & SBC_DB_DMA) 766 printf("%s: dma_stop: DMA not running\n", 767 ncr_sc->sc_dev.dv_xname); 768 #endif 769 return; 770 } 771 ncr_sc->sc_state &= ~NCR_DOINGDMA; 772 773 if ((ncr_sc->sc_state & NCR_ABORTING) == 0) { 774 ntrans = ncr_sc->sc_datalen - dh->dh_len; 775 776 #ifdef SBC_DEBUG 777 if (sbc_debug & SBC_DB_DMA) 778 printf("%s: dma_stop: ntrans=0x%x\n", 779 ncr_sc->sc_dev.dv_xname, ntrans); 780 #endif 781 782 if (ntrans > ncr_sc->sc_datalen) 783 panic("sbc_dma_stop: excess transfer\n"); 784 785 /* Adjust data pointer */ 786 ncr_sc->sc_dataptr += ntrans; 787 ncr_sc->sc_datalen -= ntrans; 788 789 /* Clear any pending interrupts. */ 790 SCI_CLR_INTR(ncr_sc); 791 if (sc->sc_clrintr) 792 (*sc->sc_clrintr)(ncr_sc); 793 } 794 795 /* Put SBIC back into PIO mode. */ 796 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 797 *ncr_sc->sci_icmd = 0; 798 799 #ifdef SBC_DEBUG 800 if (sbc_debug & SBC_DB_REG) 801 printf("%s: dma_stop: csr=0x%x, bus_csr=0x%x\n", 802 ncr_sc->sc_dev.dv_xname, *ncr_sc->sci_csr, 803 *ncr_sc->sci_bus_csr); 804 #endif 805 } 806
Indexes created Tue Sep 23 07:09:52 GMT 2025