sbc.c revision 1.33
1 /* $NetBSD: sbc.c,v 1.33 1997/12/06 18:53:30 scottr Exp $ */ 2 3 /* 4 * Copyright (C) 1996 Scott Reynolds. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * This file contains only the machine-dependent parts of the mac68k 31 * NCR 5380 SCSI driver. (Autoconfig stuff and PDMA functions.) 32 * The machine-independent parts are in ncr5380sbc.c 33 * 34 * Supported hardware includes: 35 * Macintosh II family 5380-based controller 36 * 37 * Credits, history: 38 * 39 * Scott Reynolds wrote this module, based on work by Allen Briggs 40 * (mac68k), Gordon W. Ross and David Jones (sun3), and Leo Weppelman 41 * (atari). Thanks to Allen for supplying crucial interpretation of the 42 * NetBSD/mac68k 1.1 'ncrscsi' driver. Also, Allen, Gordon, and Jason 43 * Thorpe all helped to refine this code, and were considerable sources 44 * of moral support. 45 */ 46 47 #include <sys/types.h> 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/kernel.h> 51 #include <sys/errno.h> 52 #include <sys/device.h> 53 #include <sys/buf.h> 54 #include <sys/proc.h> 55 #include <sys/user.h> 56 57 #include <dev/scsipi/scsi_all.h> 58 #include <dev/scsipi/scsipi_all.h> 59 #include <dev/scsipi/scsipi_debug.h> 60 #include <dev/scsipi/scsiconf.h> 61 62 #include <dev/ic/ncr5380reg.h> 63 #include <dev/ic/ncr5380var.h> 64 65 #include <machine/cpu.h> 66 #include <machine/viareg.h> 67 68 #include <mac68k/dev/sbcreg.h> 69 #include <mac68k/dev/sbcvar.h> 70 71 int sbc_debug = 0 /* | SBC_DB_INTR | SBC_DB_DMA */; 72 int sbc_link_flags = 0 /* | SDEV_DB2 */; 73 int sbc_options = 0 /* | SBC_PDMA */; 74 75 static void sbc_minphys __P((struct buf *bp)); 76 77 struct scsipi_adapter sbc_ops = { 78 ncr5380_scsi_cmd, /* scsi_cmd() */ 79 sbc_minphys, /* scsi_minphys() */ 80 NULL, /* open_target_lu() */ 81 NULL, /* close_target_lu() */ 82 }; 83 84 /* This is copied from julian's bt driver */ 85 /* "so we have a default dev struct for our link struct." */ 86 struct scsipi_device sbc_dev = { 87 NULL, /* Use default error handler. */ 88 NULL, /* Use default start handler. */ 89 NULL, /* Use default async handler. */ 90 NULL, /* Use default "done" routine. */ 91 }; 92 93 struct cfdriver sbc_cd = { 94 NULL, "sbc", DV_DULL 95 }; 96 97 extern label_t *nofault; 98 extern caddr_t m68k_fault_addr; 99 100 static int sbc_wait_busy __P((struct ncr5380_softc *)); 101 static int sbc_ready __P((struct ncr5380_softc *)); 102 static int sbc_wait_dreq __P((struct ncr5380_softc *)); 103 104 static void 105 sbc_minphys(struct buf *bp) 106 { 107 if (bp->b_bcount > MAX_DMA_LEN) 108 bp->b_bcount = MAX_DMA_LEN; 109 return (minphys(bp)); 110 } 111 112 113 /*** 114 * General support for Mac-specific SCSI logic. 115 ***/ 116 117 /* These are used in the following inline functions. */ 118 int sbc_wait_busy_timo = 1000 * 5000; /* X2 = 10 S. */ 119 int sbc_ready_timo = 1000 * 5000; /* X2 = 10 S. */ 120 int sbc_wait_dreq_timo = 1000 * 5000; /* X2 = 10 S. */ 121 122 /* Return zero on success. */ 123 static __inline__ int 124 sbc_wait_busy(sc) 125 struct ncr5380_softc *sc; 126 { 127 int timo = sbc_wait_busy_timo; 128 for (;;) { 129 if (SCI_BUSY(sc)) { 130 timo = 0; /* return 0 */ 131 break; 132 } 133 if (--timo < 0) 134 break; /* return -1 */ 135 delay(2); 136 } 137 return (timo); 138 } 139 140 static __inline__ int 141 sbc_ready(sc) 142 struct ncr5380_softc *sc; 143 { 144 int timo = sbc_ready_timo; 145 146 for (;;) { 147 if ((*sc->sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) 148 == (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 149 timo = 0; 150 break; 151 } 152 if (((*sc->sci_csr & SCI_CSR_PHASE_MATCH) == 0) 153 || (SCI_BUSY(sc) == 0)) { 154 timo = -1; 155 break; 156 } 157 if (--timo < 0) 158 break; /* return -1 */ 159 delay(2); 160 } 161 return (timo); 162 } 163 164 static __inline__ int 165 sbc_wait_dreq(sc) 166 struct ncr5380_softc *sc; 167 { 168 int timo = sbc_wait_dreq_timo; 169 170 for (;;) { 171 if ((*sc->sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) 172 == (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 173 timo = 0; 174 break; 175 } 176 if (--timo < 0) 177 break; /* return -1 */ 178 delay(2); 179 } 180 return (timo); 181 } 182 183 void 184 sbc_irq_intr(p) 185 void *p; 186 { 187 struct ncr5380_softc *ncr_sc = p; 188 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 189 int claimed = 0; 190 extern int cold; 191 192 /* How we ever arrive here without IRQ set is a mystery... */ 193 if (*ncr_sc->sci_csr & SCI_CSR_INT) { 194 #ifdef SBC_DEBUG 195 if (sbc_debug & SBC_DB_INTR) 196 decode_5380_intr(ncr_sc); 197 #endif 198 if (!cold) 199 claimed = ncr5380_intr(ncr_sc); 200 if (!claimed) { 201 if (((*ncr_sc->sci_csr & ~SCI_CSR_PHASE_MATCH) == SCI_CSR_INT) 202 && ((*ncr_sc->sci_bus_csr & ~SCI_BUS_RST) == 0)) { 203 SCI_CLR_INTR(ncr_sc); /* RST interrupt */ 204 if (sc->sc_clrintr) 205 (*sc->sc_clrintr)(ncr_sc); 206 } 207 #ifdef SBC_DEBUG 208 else { 209 printf("%s: spurious intr\n", 210 ncr_sc->sc_dev.dv_xname); 211 SBC_BREAK; 212 } 213 #endif 214 } 215 } 216 } 217 218 #ifdef SBC_DEBUG 219 void 220 decode_5380_intr(ncr_sc) 221 struct ncr5380_softc *ncr_sc; 222 { 223 u_int8_t csr = *ncr_sc->sci_csr; 224 u_int8_t bus_csr = *ncr_sc->sci_bus_csr; 225 226 if (((csr & ~(SCI_CSR_PHASE_MATCH | SCI_CSR_ATN)) == SCI_CSR_INT) && 227 ((bus_csr & ~(SCI_BUS_MSG | SCI_BUS_CD | SCI_BUS_IO | SCI_BUS_DBP)) == SCI_BUS_SEL)) { 228 if (csr & SCI_BUS_IO) 229 printf("%s: reselect\n", ncr_sc->sc_dev.dv_xname); 230 else 231 printf("%s: select\n", ncr_sc->sc_dev.dv_xname); 232 } else if (((csr & ~SCI_CSR_ACK) == (SCI_CSR_DONE | SCI_CSR_INT)) && 233 ((bus_csr & (SCI_BUS_RST | SCI_BUS_BSY | SCI_BUS_SEL)) == SCI_BUS_BSY)) 234 printf("%s: dma eop\n", ncr_sc->sc_dev.dv_xname); 235 else if (((csr & ~SCI_CSR_PHASE_MATCH) == SCI_CSR_INT) && 236 ((bus_csr & ~SCI_BUS_RST) == 0)) 237 printf("%s: bus reset\n", ncr_sc->sc_dev.dv_xname); 238 else if (((csr & ~(SCI_CSR_DREQ | SCI_CSR_ATN | SCI_CSR_ACK)) == (SCI_CSR_PERR | SCI_CSR_INT | SCI_CSR_PHASE_MATCH)) && 239 ((bus_csr & (SCI_BUS_RST | SCI_BUS_BSY | SCI_BUS_SEL)) == SCI_BUS_BSY)) 240 printf("%s: parity error\n", ncr_sc->sc_dev.dv_xname); 241 else if (((csr & ~SCI_CSR_ATN) == SCI_CSR_INT) && 242 ((bus_csr & (SCI_BUS_RST | SCI_BUS_BSY | SCI_BUS_REQ | SCI_BUS_SEL)) == (SCI_BUS_BSY | SCI_BUS_REQ))) 243 printf("%s: phase mismatch\n", ncr_sc->sc_dev.dv_xname); 244 else if (((csr & ~SCI_CSR_PHASE_MATCH) == (SCI_CSR_INT | SCI_CSR_DISC)) && 245 (bus_csr == 0)) 246 printf("%s: disconnect\n", ncr_sc->sc_dev.dv_xname); 247 else 248 printf("%s: unknown intr: csr=%x, bus_csr=%x\n", 249 ncr_sc->sc_dev.dv_xname, csr, bus_csr); 250 } 251 #endif 252 253 254 /*** 255 * The following code implements polled PDMA. 256 ***/ 257 258 int 259 sbc_pdma_in(ncr_sc, phase, datalen, data) 260 struct ncr5380_softc *ncr_sc; 261 int phase; 262 int datalen; 263 u_char *data; 264 { 265 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 266 volatile u_int32_t *long_data = (u_int32_t *)sc->sc_drq_addr; 267 volatile u_int8_t *byte_data = (u_int8_t *)sc->sc_nodrq_addr; 268 int resid, s; 269 270 if (datalen < ncr_sc->sc_min_dma_len || 271 (sc->sc_options & SBC_PDMA) == 0) 272 return ncr5380_pio_in(ncr_sc, phase, datalen, data); 273 274 s = splbio(); 275 if (sbc_wait_busy(ncr_sc)) { 276 splx(s); 277 return 0; 278 } 279 280 *ncr_sc->sci_mode |= SCI_MODE_DMA; 281 *ncr_sc->sci_irecv = 0; 282 283 #define R4 *((u_int32_t *)data)++ = *long_data 284 #define R1 *((u_int8_t *)data)++ = *byte_data 285 for (resid = datalen; resid >= 128; resid -= 128) { 286 if (sbc_ready(ncr_sc)) 287 goto interrupt; 288 R4; R4; R4; R4; R4; R4; R4; R4; 289 R4; R4; R4; R4; R4; R4; R4; R4; 290 R4; R4; R4; R4; R4; R4; R4; R4; 291 R4; R4; R4; R4; R4; R4; R4; R4; /* 128 */ 292 } 293 while (resid) { 294 if (sbc_ready(ncr_sc)) 295 goto interrupt; 296 R1; 297 resid--; 298 } 299 #undef R4 300 #undef R1 301 302 interrupt: 303 SCI_CLR_INTR(ncr_sc); 304 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 305 *ncr_sc->sci_icmd = 0; 306 splx(s); 307 return (datalen - resid); 308 } 309 310 int 311 sbc_pdma_out(ncr_sc, phase, datalen, data) 312 struct ncr5380_softc *ncr_sc; 313 int phase; 314 int datalen; 315 u_char *data; 316 { 317 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 318 volatile u_int32_t *long_data = (u_int32_t *)sc->sc_drq_addr; 319 volatile u_int8_t *byte_data = (u_int8_t *)sc->sc_nodrq_addr; 320 label_t faultbuf; 321 int resid, s; 322 u_int8_t icmd; 323 324 #if 1 325 /* Work around lame gcc initialization bug */ 326 (void)&data; 327 #endif 328 329 if (datalen < ncr_sc->sc_min_dma_len || 330 (sc->sc_options & SBC_PDMA) == 0) 331 return ncr5380_pio_out(ncr_sc, phase, datalen, data); 332 333 s = splbio(); 334 if (sbc_wait_busy(ncr_sc)) { 335 splx(s); 336 return 0; 337 } 338 339 icmd = *(ncr_sc->sci_icmd) & SCI_ICMD_RMASK; 340 *ncr_sc->sci_icmd = icmd | SCI_ICMD_DATA; 341 *ncr_sc->sci_mode |= SCI_MODE_DMA; 342 *ncr_sc->sci_dma_send = 0; 343 344 /* 345 * Setup for a possible bus error caused by SCSI controller 346 * switching out of DATA OUT before we're done with the 347 * current transfer. (See comment before sbc_drq_intr().) 348 */ 349 nofault = &faultbuf; 350 351 if (setjmp(nofault)) { 352 printf("buf = 0x%lx, fault = 0x%lx\n", 353 (u_long)sc->sc_drq_addr, (u_long)m68k_fault_addr); 354 panic("Unexpected bus error in sbc_pdma_out()"); 355 } 356 357 #define W1 *byte_data = *((u_int8_t *)data)++ 358 #define W4 *long_data = *((u_int32_t *)data)++ 359 for (resid = datalen; resid >= 64; resid -= 64) { 360 if (sbc_ready(ncr_sc)) 361 goto interrupt; 362 W1; 363 if (sbc_ready(ncr_sc)) 364 goto interrupt; 365 W1; 366 if (sbc_ready(ncr_sc)) 367 goto interrupt; 368 W1; 369 if (sbc_ready(ncr_sc)) 370 goto interrupt; 371 W1; 372 if (sbc_ready(ncr_sc)) 373 goto interrupt; 374 W4; W4; W4; W4; 375 W4; W4; W4; W4; 376 W4; W4; W4; W4; 377 W4; W4; W4; 378 } 379 while (resid) { 380 if (sbc_ready(ncr_sc)) 381 goto interrupt; 382 W1; 383 resid--; 384 } 385 #undef W1 386 #undef W4 387 if (sbc_wait_dreq(ncr_sc)) 388 printf("%s: timeout waiting for DREQ.\n", 389 ncr_sc->sc_dev.dv_xname); 390 391 *byte_data = 0; 392 goto done; 393 394 interrupt: 395 if ((*ncr_sc->sci_csr & SCI_CSR_PHASE_MATCH) == 0) { 396 *ncr_sc->sci_icmd = icmd & ~SCI_ICMD_DATA; 397 --resid; 398 } 399 400 done: 401 SCI_CLR_INTR(ncr_sc); 402 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 403 *ncr_sc->sci_icmd = icmd; 404 splx(s); 405 return (datalen - resid); 406 } 407 408 409 /*** 410 * The following code implements interrupt-driven PDMA. 411 ***/ 412 413 /* 414 * This is the meat of the PDMA transfer. 415 * When we get here, we shove data as fast as the mac can take it. 416 * We depend on several things: 417 * * All macs after the Mac Plus that have a 5380 chip should have a general 418 * logic IC that handshakes data for blind transfers. 419 * * If the SCSI controller finishes sending/receiving data before we do, 420 * the same general logic IC will generate a /BERR for us in short order. 421 * * The fault address for said /BERR minus the base address for the 422 * transfer will be the amount of data that was actually written. 423 * 424 * We use the nofault flag and the setjmp/longjmp in locore.s so we can 425 * detect and handle the bus error for early termination of a command. 426 * This is usually caused by a disconnecting target. 427 */ 428 void 429 sbc_drq_intr(p) 430 void *p; 431 { 432 struct sbc_softc *sc = (struct sbc_softc *)p; 433 struct ncr5380_softc *ncr_sc = (struct ncr5380_softc *)p; 434 struct sci_req *sr = ncr_sc->sc_current; 435 struct sbc_pdma_handle *dh = sr->sr_dma_hand; 436 label_t faultbuf; 437 volatile u_int32_t *long_drq; 438 u_int32_t *long_data; 439 volatile u_int8_t *drq; 440 u_int8_t *data; 441 int count, dcount, resid; 442 u_int8_t tmp; 443 444 /* Work around lame gcc initialization bug */ 445 (void)&drq; 446 447 /* 448 * If we're not ready to xfer data, or have no more, just return. 449 */ 450 if ((*ncr_sc->sci_csr & SCI_CSR_DREQ) == 0 || dh->dh_len == 0) 451 return; 452 453 #ifdef SBC_DEBUG 454 if (sbc_debug & SBC_DB_INTR) 455 printf("%s: drq intr, dh_len=0x%x, dh_flags=0x%x\n", 456 ncr_sc->sc_dev.dv_xname, dh->dh_len, dh->dh_flags); 457 #endif 458 459 /* 460 * Setup for a possible bus error caused by SCSI controller 461 * switching out of DATA-IN/OUT before we're done with the 462 * current transfer. 463 */ 464 nofault = &faultbuf; 465 466 if (setjmp(nofault)) { 467 nofault = (label_t *)0; 468 if ((dh->dh_flags & SBC_DH_DONE) == 0) { 469 count = (( (u_long)m68k_fault_addr 470 - (u_long)sc->sc_drq_addr)); 471 472 if ((count < 0) || (count > dh->dh_len)) { 473 printf("%s: complete=0x%x (pending 0x%x)\n", 474 ncr_sc->sc_dev.dv_xname, count, dh->dh_len); 475 panic("something is wrong"); 476 } 477 478 dh->dh_addr += count; 479 dh->dh_len -= count; 480 } else 481 count = 0; 482 483 #ifdef SBC_DEBUG 484 if (sbc_debug & SBC_DB_INTR) 485 printf("%s: drq /berr, complete=0x%x (pending 0x%x)\n", 486 ncr_sc->sc_dev.dv_xname, count, dh->dh_len); 487 #endif 488 m68k_fault_addr = 0; 489 490 return; 491 } 492 493 if (dh->dh_flags & SBC_DH_OUT) { /* Data Out */ 494 dcount = 0; 495 496 /* 497 * Get the source address aligned. 498 */ 499 resid = 500 count = min(dh->dh_len, 4 - (((int)dh->dh_addr) & 0x3)); 501 if (count && count < 4) { 502 drq = (volatile u_int8_t *)sc->sc_drq_addr; 503 data = (u_int8_t *)dh->dh_addr; 504 505 #define W1 *drq++ = *data++ 506 while (count) { 507 W1; count--; 508 } 509 #undef W1 510 dh->dh_addr += resid; 511 dh->dh_len -= resid; 512 } 513 514 /* 515 * Start the transfer. 516 */ 517 while (dh->dh_len) { 518 dcount = count = min(dh->dh_len, MAX_DMA_LEN); 519 long_drq = (volatile u_int32_t *)sc->sc_drq_addr; 520 long_data = (u_int32_t *)dh->dh_addr; 521 522 #define W4 *long_drq++ = *long_data++ 523 while (count >= 64) { 524 W4; W4; W4; W4; W4; W4; W4; W4; 525 W4; W4; W4; W4; W4; W4; W4; W4; /* 64 */ 526 count -= 64; 527 } 528 while (count >= 4) { 529 W4; count -= 4; 530 } 531 #undef W4 532 data = (u_int8_t *)long_data; 533 drq = (u_int8_t *)long_drq; 534 535 #define W1 *drq++ = *data++ 536 while (count) { 537 W1; count--; 538 } 539 #undef W1 540 dh->dh_len -= dcount; 541 dh->dh_addr += dcount; 542 } 543 dh->dh_flags |= SBC_DH_DONE; 544 545 /* 546 * XXX -- Read a byte from the SBC to trigger a /BERR. 547 * This seems to be necessary for us to notice that 548 * the target has disconnected. Ick. 06 jun 1996 (sr) 549 */ 550 if (dcount >= MAX_DMA_LEN) 551 drq = (volatile u_int8_t *)sc->sc_drq_addr; 552 tmp = *drq; 553 } else { /* Data In */ 554 /* 555 * Get the dest address aligned. 556 */ 557 resid = 558 count = min(dh->dh_len, 4 - (((int)dh->dh_addr) & 0x3)); 559 if (count && count < 4) { 560 data = (u_int8_t *)dh->dh_addr; 561 drq = (volatile u_int8_t *)sc->sc_drq_addr; 562 563 #define R1 *data++ = *drq++ 564 while (count) { 565 R1; count--; 566 } 567 #undef R1 568 dh->dh_addr += resid; 569 dh->dh_len -= resid; 570 } 571 572 /* 573 * Start the transfer. 574 */ 575 while (dh->dh_len) { 576 dcount = count = min(dh->dh_len, MAX_DMA_LEN); 577 long_data = (u_int32_t *)dh->dh_addr; 578 long_drq = (volatile u_int32_t *)sc->sc_drq_addr; 579 580 #define R4 *long_data++ = *long_drq++ 581 while (count >= 64) { 582 R4; R4; R4; R4; R4; R4; R4; R4; 583 R4; R4; R4; R4; R4; R4; R4; R4; /* 64 */ 584 count -= 64; 585 } 586 while (count >= 4) { 587 R4; count -= 4; 588 } 589 #undef R4 590 data = (u_int8_t *)long_data; 591 drq = (volatile u_int8_t *)long_drq; 592 593 #define R1 *data++ = *drq++ 594 while (count) { 595 R1; count--; 596 } 597 #undef R1 598 dh->dh_len -= dcount; 599 dh->dh_addr += dcount; 600 } 601 dh->dh_flags |= SBC_DH_DONE; 602 } 603 604 /* 605 * OK. No bus error occurred above. Clear the nofault flag 606 * so we no longer short-circuit bus errors. 607 */ 608 nofault = (label_t *)0; 609 610 #ifdef SBC_DEBUG 611 if (sbc_debug & (SBC_DB_REG | SBC_DB_INTR)) 612 printf("%s: drq intr complete: csr=0x%x, bus_csr=0x%x\n", 613 ncr_sc->sc_dev.dv_xname, *ncr_sc->sci_csr, 614 *ncr_sc->sci_bus_csr); 615 #endif 616 } 617 618 void 619 sbc_dma_alloc(ncr_sc) 620 struct ncr5380_softc *ncr_sc; 621 { 622 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 623 struct sci_req *sr = ncr_sc->sc_current; 624 struct scsipi_xfer *xs = sr->sr_xs; 625 struct sbc_pdma_handle *dh; 626 int i, xlen; 627 628 #ifdef DIAGNOSTIC 629 if (sr->sr_dma_hand != NULL) 630 panic("sbc_dma_alloc: already have PDMA handle"); 631 #endif 632 633 /* Polled transfers shouldn't allocate a PDMA handle. */ 634 if (sr->sr_flags & SR_IMMED) 635 return; 636 637 xlen = ncr_sc->sc_datalen; 638 639 /* Make sure our caller checked sc_min_dma_len. */ 640 if (xlen < MIN_DMA_LEN) 641 panic("sbc_dma_alloc: len=0x%x\n", xlen); 642 643 /* 644 * Find free PDMA handle. Guaranteed to find one since we 645 * have as many PDMA handles as the driver has processes. 646 * (instances?) 647 */ 648 for (i = 0; i < SCI_OPENINGS; i++) { 649 if ((sc->sc_pdma[i].dh_flags & SBC_DH_BUSY) == 0) 650 goto found; 651 } 652 panic("sbc: no free PDMA handles"); 653 found: 654 dh = &sc->sc_pdma[i]; 655 dh->dh_flags = SBC_DH_BUSY; 656 dh->dh_addr = ncr_sc->sc_dataptr; 657 dh->dh_len = xlen; 658 659 /* Copy the 'write' flag for convenience. */ 660 if (xs->flags & SCSI_DATA_OUT) 661 dh->dh_flags |= SBC_DH_OUT; 662 663 sr->sr_dma_hand = dh; 664 } 665 666 void 667 sbc_dma_free(ncr_sc) 668 struct ncr5380_softc *ncr_sc; 669 { 670 struct sci_req *sr = ncr_sc->sc_current; 671 struct sbc_pdma_handle *dh = sr->sr_dma_hand; 672 673 #ifdef DIAGNOSTIC 674 if (sr->sr_dma_hand == NULL) 675 panic("sbc_dma_free: no DMA handle"); 676 #endif 677 678 if (ncr_sc->sc_state & NCR_DOINGDMA) 679 panic("sbc_dma_free: free while in progress"); 680 681 if (dh->dh_flags & SBC_DH_BUSY) { 682 dh->dh_flags = 0; 683 dh->dh_addr = NULL; 684 dh->dh_len = 0; 685 } 686 sr->sr_dma_hand = NULL; 687 } 688 689 void 690 sbc_dma_poll(ncr_sc) 691 struct ncr5380_softc *ncr_sc; 692 { 693 struct sci_req *sr = ncr_sc->sc_current; 694 695 /* 696 * We shouldn't arrive here; if SR_IMMED is set, then 697 * dma_alloc() should have refused to allocate a handle 698 * for the transfer. This forces the polled PDMA code 699 * to handle the request... 700 */ 701 #ifdef SBC_DEBUG 702 if (sbc_debug & SBC_DB_DMA) 703 printf("%s: lost DRQ interrupt?\n", ncr_sc->sc_dev.dv_xname); 704 #endif 705 sr->sr_flags |= SR_OVERDUE; 706 } 707 708 void 709 sbc_dma_setup(ncr_sc) 710 struct ncr5380_softc *ncr_sc; 711 { 712 /* Not needed; we don't have real DMA */ 713 } 714 715 void 716 sbc_dma_start(ncr_sc) 717 struct ncr5380_softc *ncr_sc; 718 { 719 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 720 struct sci_req *sr = ncr_sc->sc_current; 721 struct sbc_pdma_handle *dh = sr->sr_dma_hand; 722 723 /* 724 * Match bus phase, clear pending interrupts, set DMA mode, and 725 * assert data bus (for writing only), then start the transfer. 726 */ 727 if (dh->dh_flags & SBC_DH_OUT) { 728 *ncr_sc->sci_tcmd = PHASE_DATA_OUT; 729 SCI_CLR_INTR(ncr_sc); 730 if (sc->sc_clrintr) 731 (*sc->sc_clrintr)(ncr_sc); 732 *ncr_sc->sci_mode |= SCI_MODE_DMA; 733 *ncr_sc->sci_icmd = SCI_ICMD_DATA; 734 *ncr_sc->sci_dma_send = 0; 735 } else { 736 *ncr_sc->sci_tcmd = PHASE_DATA_IN; 737 SCI_CLR_INTR(ncr_sc); 738 if (sc->sc_clrintr) 739 (*sc->sc_clrintr)(ncr_sc); 740 *ncr_sc->sci_mode |= SCI_MODE_DMA; 741 *ncr_sc->sci_icmd = 0; 742 *ncr_sc->sci_irecv = 0; 743 } 744 ncr_sc->sc_state |= NCR_DOINGDMA; 745 746 #ifdef SBC_DEBUG 747 if (sbc_debug & SBC_DB_DMA) 748 printf("%s: PDMA started, va=%p, len=0x%x\n", 749 ncr_sc->sc_dev.dv_xname, dh->dh_addr, dh->dh_len); 750 #endif 751 } 752 753 void 754 sbc_dma_eop(ncr_sc) 755 struct ncr5380_softc *ncr_sc; 756 { 757 /* Not used; the EOP pin is wired high (GMFH, pp. 389-390) */ 758 } 759 760 void 761 sbc_dma_stop(ncr_sc) 762 struct ncr5380_softc *ncr_sc; 763 { 764 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 765 struct sci_req *sr = ncr_sc->sc_current; 766 struct sbc_pdma_handle *dh = sr->sr_dma_hand; 767 int ntrans; 768 769 if ((ncr_sc->sc_state & NCR_DOINGDMA) == 0) { 770 #ifdef SBC_DEBUG 771 if (sbc_debug & SBC_DB_DMA) 772 printf("%s: dma_stop: DMA not running\n", 773 ncr_sc->sc_dev.dv_xname); 774 #endif 775 return; 776 } 777 ncr_sc->sc_state &= ~NCR_DOINGDMA; 778 779 if ((ncr_sc->sc_state & NCR_ABORTING) == 0) { 780 ntrans = ncr_sc->sc_datalen - dh->dh_len; 781 782 #ifdef SBC_DEBUG 783 if (sbc_debug & SBC_DB_DMA) 784 printf("%s: dma_stop: ntrans=0x%x\n", 785 ncr_sc->sc_dev.dv_xname, ntrans); 786 #endif 787 788 if (ntrans > ncr_sc->sc_datalen) 789 panic("sbc_dma_stop: excess transfer\n"); 790 791 /* Adjust data pointer */ 792 ncr_sc->sc_dataptr += ntrans; 793 ncr_sc->sc_datalen -= ntrans; 794 795 /* Clear any pending interrupts. */ 796 SCI_CLR_INTR(ncr_sc); 797 if (sc->sc_clrintr) 798 (*sc->sc_clrintr)(ncr_sc); 799 } 800 801 /* Put SBIC back into PIO mode. */ 802 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 803 *ncr_sc->sci_icmd = 0; 804 805 #ifdef SBC_DEBUG 806 if (sbc_debug & SBC_DB_REG) 807 printf("%s: dma_stop: csr=0x%x, bus_csr=0x%x\n", 808 ncr_sc->sc_dev.dv_xname, *ncr_sc->sci_csr, 809 *ncr_sc->sci_bus_csr); 810 #endif 811 } 812
Indexes created Thu Sep 25 16:09:42 GMT 2025