sbc.c revision 1.36
1 /* $NetBSD: sbc.c,v 1.36 1998/07/04 22:18:27 jonathan Exp $ */ 2 3 /* 4 * Copyright (C) 1996 Scott Reynolds. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * This file contains only the machine-dependent parts of the mac68k 31 * NCR 5380 SCSI driver. (Autoconfig stuff and PDMA functions.) 32 * The machine-independent parts are in ncr5380sbc.c 33 * 34 * Supported hardware includes: 35 * Macintosh II family 5380-based controller 36 * 37 * Credits, history: 38 * 39 * Scott Reynolds wrote this module, based on work by Allen Briggs 40 * (mac68k), Gordon W. Ross and David Jones (sun3), and Leo Weppelman 41 * (atari). Thanks to Allen for supplying crucial interpretation of the 42 * NetBSD/mac68k 1.1 'ncrscsi' driver. Also, Allen, Gordon, and Jason 43 * Thorpe all helped to refine this code, and were considerable sources 44 * of moral support. 45 */ 46 #include "opt_ddb.h" 47 48 #include <sys/types.h> 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/kernel.h> 52 #include <sys/errno.h> 53 #include <sys/device.h> 54 #include <sys/buf.h> 55 #include <sys/proc.h> 56 #include <sys/user.h> 57 58 #include <dev/scsipi/scsi_all.h> 59 #include <dev/scsipi/scsipi_all.h> 60 #include <dev/scsipi/scsipi_debug.h> 61 #include <dev/scsipi/scsiconf.h> 62 63 #include <dev/ic/ncr5380reg.h> 64 #include <dev/ic/ncr5380var.h> 65 66 #include <machine/cpu.h> 67 #include <machine/viareg.h> 68 69 #include <mac68k/dev/sbcreg.h> 70 #include <mac68k/dev/sbcvar.h> 71 72 /* SBC_DEBUG -- relies on DDB */ 73 #ifdef SBC_DEBUG 74 # define SBC_DB_INTR 0x01 75 # define SBC_DB_DMA 0x02 76 # define SBC_DB_REG 0x04 77 # define SBC_DB_BREAK 0x08 78 # ifndef DDB 79 # define Debugger() printf("Debug: sbc.c:%d\n", __LINE__) 80 # endif 81 # define SBC_BREAK \ 82 do { if (sbc_debug & SBC_DB_BREAK) Debugger(); } while (0) 83 #else 84 # define SBC_BREAK 85 #endif 86 87 88 int sbc_debug = 0 /* | SBC_DB_INTR | SBC_DB_DMA */; 89 int sbc_link_flags = 0 /* | SDEV_DB2 */; 90 int sbc_options = 0 /* | SBC_PDMA */; 91 92 struct scsipi_adapter sbc_ops = { 93 ncr5380_scsi_cmd, /* scsi_cmd() */ 94 minphys, /* scsi_minphys() */ 95 NULL, /* open_target_lu() */ 96 NULL, /* close_target_lu() */ 97 }; 98 99 /* This is copied from julian's bt driver */ 100 /* "so we have a default dev struct for our link struct." */ 101 struct scsipi_device sbc_dev = { 102 NULL, /* Use default error handler. */ 103 NULL, /* Use default start handler. */ 104 NULL, /* Use default async handler. */ 105 NULL, /* Use default "done" routine. */ 106 }; 107 108 extern label_t *nofault; 109 extern caddr_t m68k_fault_addr; 110 111 static int sbc_wait_busy __P((struct ncr5380_softc *)); 112 static int sbc_ready __P((struct ncr5380_softc *)); 113 static int sbc_wait_dreq __P((struct ncr5380_softc *)); 114 115 116 /*** 117 * General support for Mac-specific SCSI logic. 118 ***/ 119 120 /* These are used in the following inline functions. */ 121 int sbc_wait_busy_timo = 1000 * 5000; /* X2 = 10 S. */ 122 int sbc_ready_timo = 1000 * 5000; /* X2 = 10 S. */ 123 int sbc_wait_dreq_timo = 1000 * 5000; /* X2 = 10 S. */ 124 125 /* Return zero on success. */ 126 static __inline__ int 127 sbc_wait_busy(sc) 128 struct ncr5380_softc *sc; 129 { 130 int timo = sbc_wait_busy_timo; 131 for (;;) { 132 if (SCI_BUSY(sc)) { 133 timo = 0; /* return 0 */ 134 break; 135 } 136 if (--timo < 0) 137 break; /* return -1 */ 138 delay(2); 139 } 140 return (timo); 141 } 142 143 static __inline__ int 144 sbc_ready(sc) 145 struct ncr5380_softc *sc; 146 { 147 int timo = sbc_ready_timo; 148 149 for (;;) { 150 if ((*sc->sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) 151 == (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 152 timo = 0; 153 break; 154 } 155 if (((*sc->sci_csr & SCI_CSR_PHASE_MATCH) == 0) 156 || (SCI_BUSY(sc) == 0)) { 157 timo = -1; 158 break; 159 } 160 if (--timo < 0) 161 break; /* return -1 */ 162 delay(2); 163 } 164 return (timo); 165 } 166 167 static __inline__ int 168 sbc_wait_dreq(sc) 169 struct ncr5380_softc *sc; 170 { 171 int timo = sbc_wait_dreq_timo; 172 173 for (;;) { 174 if ((*sc->sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) 175 == (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 176 timo = 0; 177 break; 178 } 179 if (--timo < 0) 180 break; /* return -1 */ 181 delay(2); 182 } 183 return (timo); 184 } 185 186 void 187 sbc_irq_intr(p) 188 void *p; 189 { 190 struct ncr5380_softc *ncr_sc = p; 191 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 192 int claimed = 0; 193 extern int cold; 194 195 /* How we ever arrive here without IRQ set is a mystery... */ 196 if (*ncr_sc->sci_csr & SCI_CSR_INT) { 197 #ifdef SBC_DEBUG 198 if (sbc_debug & SBC_DB_INTR) 199 decode_5380_intr(ncr_sc); 200 #endif 201 if (!cold) 202 claimed = ncr5380_intr(ncr_sc); 203 if (!claimed) { 204 if (((*ncr_sc->sci_csr & ~SCI_CSR_PHASE_MATCH) == SCI_CSR_INT) 205 && ((*ncr_sc->sci_bus_csr & ~SCI_BUS_RST) == 0)) { 206 SCI_CLR_INTR(ncr_sc); /* RST interrupt */ 207 if (sc->sc_clrintr) 208 (*sc->sc_clrintr)(ncr_sc); 209 } 210 #ifdef SBC_DEBUG 211 else { 212 printf("%s: spurious intr\n", 213 ncr_sc->sc_dev.dv_xname); 214 SBC_BREAK; 215 } 216 #endif 217 } 218 } 219 } 220 221 #ifdef SBC_DEBUG 222 void 223 decode_5380_intr(ncr_sc) 224 struct ncr5380_softc *ncr_sc; 225 { 226 u_int8_t csr = *ncr_sc->sci_csr; 227 u_int8_t bus_csr = *ncr_sc->sci_bus_csr; 228 229 if (((csr & ~(SCI_CSR_PHASE_MATCH | SCI_CSR_ATN)) == SCI_CSR_INT) && 230 ((bus_csr & ~(SCI_BUS_MSG | SCI_BUS_CD | SCI_BUS_IO | SCI_BUS_DBP)) == SCI_BUS_SEL)) { 231 if (csr & SCI_BUS_IO) 232 printf("%s: reselect\n", ncr_sc->sc_dev.dv_xname); 233 else 234 printf("%s: select\n", ncr_sc->sc_dev.dv_xname); 235 } else if (((csr & ~SCI_CSR_ACK) == (SCI_CSR_DONE | SCI_CSR_INT)) && 236 ((bus_csr & (SCI_BUS_RST | SCI_BUS_BSY | SCI_BUS_SEL)) == SCI_BUS_BSY)) 237 printf("%s: dma eop\n", ncr_sc->sc_dev.dv_xname); 238 else if (((csr & ~SCI_CSR_PHASE_MATCH) == SCI_CSR_INT) && 239 ((bus_csr & ~SCI_BUS_RST) == 0)) 240 printf("%s: bus reset\n", ncr_sc->sc_dev.dv_xname); 241 else if (((csr & ~(SCI_CSR_DREQ | SCI_CSR_ATN | SCI_CSR_ACK)) == (SCI_CSR_PERR | SCI_CSR_INT | SCI_CSR_PHASE_MATCH)) && 242 ((bus_csr & (SCI_BUS_RST | SCI_BUS_BSY | SCI_BUS_SEL)) == SCI_BUS_BSY)) 243 printf("%s: parity error\n", ncr_sc->sc_dev.dv_xname); 244 else if (((csr & ~SCI_CSR_ATN) == SCI_CSR_INT) && 245 ((bus_csr & (SCI_BUS_RST | SCI_BUS_BSY | SCI_BUS_REQ | SCI_BUS_SEL)) == (SCI_BUS_BSY | SCI_BUS_REQ))) 246 printf("%s: phase mismatch\n", ncr_sc->sc_dev.dv_xname); 247 else if (((csr & ~SCI_CSR_PHASE_MATCH) == (SCI_CSR_INT | SCI_CSR_DISC)) && 248 (bus_csr == 0)) 249 printf("%s: disconnect\n", ncr_sc->sc_dev.dv_xname); 250 else 251 printf("%s: unknown intr: csr=%x, bus_csr=%x\n", 252 ncr_sc->sc_dev.dv_xname, csr, bus_csr); 253 } 254 #endif 255 256 257 /*** 258 * The following code implements polled PDMA. 259 ***/ 260 261 int 262 sbc_pdma_in(ncr_sc, phase, datalen, data) 263 struct ncr5380_softc *ncr_sc; 264 int phase; 265 int datalen; 266 u_char *data; 267 { 268 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 269 volatile u_int32_t *long_data = (u_int32_t *)sc->sc_drq_addr; 270 volatile u_int8_t *byte_data = (u_int8_t *)sc->sc_nodrq_addr; 271 int resid, s; 272 273 if (datalen < ncr_sc->sc_min_dma_len || 274 (sc->sc_options & SBC_PDMA) == 0) 275 return ncr5380_pio_in(ncr_sc, phase, datalen, data); 276 277 s = splbio(); 278 if (sbc_wait_busy(ncr_sc)) { 279 splx(s); 280 return 0; 281 } 282 283 *ncr_sc->sci_mode |= SCI_MODE_DMA; 284 *ncr_sc->sci_irecv = 0; 285 286 #define R4 *((u_int32_t *)data)++ = *long_data 287 #define R1 *((u_int8_t *)data)++ = *byte_data 288 for (resid = datalen; resid >= 128; resid -= 128) { 289 if (sbc_ready(ncr_sc)) 290 goto interrupt; 291 R4; R4; R4; R4; R4; R4; R4; R4; 292 R4; R4; R4; R4; R4; R4; R4; R4; 293 R4; R4; R4; R4; R4; R4; R4; R4; 294 R4; R4; R4; R4; R4; R4; R4; R4; /* 128 */ 295 } 296 while (resid) { 297 if (sbc_ready(ncr_sc)) 298 goto interrupt; 299 R1; 300 resid--; 301 } 302 #undef R4 303 #undef R1 304 305 interrupt: 306 SCI_CLR_INTR(ncr_sc); 307 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 308 *ncr_sc->sci_icmd = 0; 309 splx(s); 310 return (datalen - resid); 311 } 312 313 int 314 sbc_pdma_out(ncr_sc, phase, datalen, data) 315 struct ncr5380_softc *ncr_sc; 316 int phase; 317 int datalen; 318 u_char *data; 319 { 320 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 321 volatile u_int32_t *long_data = (u_int32_t *)sc->sc_drq_addr; 322 volatile u_int8_t *byte_data = (u_int8_t *)sc->sc_nodrq_addr; 323 label_t faultbuf; 324 int resid, s; 325 u_int8_t icmd; 326 327 #if 1 328 /* Work around lame gcc initialization bug */ 329 (void)&data; 330 #endif 331 332 if (datalen < ncr_sc->sc_min_dma_len || 333 (sc->sc_options & SBC_PDMA) == 0) 334 return ncr5380_pio_out(ncr_sc, phase, datalen, data); 335 336 s = splbio(); 337 if (sbc_wait_busy(ncr_sc)) { 338 splx(s); 339 return 0; 340 } 341 342 icmd = *(ncr_sc->sci_icmd) & SCI_ICMD_RMASK; 343 *ncr_sc->sci_icmd = icmd | SCI_ICMD_DATA; 344 *ncr_sc->sci_mode |= SCI_MODE_DMA; 345 *ncr_sc->sci_dma_send = 0; 346 347 /* 348 * Setup for a possible bus error caused by SCSI controller 349 * switching out of DATA OUT before we're done with the 350 * current transfer. (See comment before sbc_drq_intr().) 351 */ 352 nofault = &faultbuf; 353 354 if (setjmp(nofault)) { 355 printf("buf = 0x%lx, fault = 0x%lx\n", 356 (u_long)sc->sc_drq_addr, (u_long)m68k_fault_addr); 357 panic("Unexpected bus error in sbc_pdma_out()"); 358 } 359 360 #define W1 *byte_data = *((u_int8_t *)data)++ 361 #define W4 *long_data = *((u_int32_t *)data)++ 362 for (resid = datalen; resid >= 64; resid -= 64) { 363 if (sbc_ready(ncr_sc)) 364 goto interrupt; 365 W1; 366 if (sbc_ready(ncr_sc)) 367 goto interrupt; 368 W1; 369 if (sbc_ready(ncr_sc)) 370 goto interrupt; 371 W1; 372 if (sbc_ready(ncr_sc)) 373 goto interrupt; 374 W1; 375 if (sbc_ready(ncr_sc)) 376 goto interrupt; 377 W4; W4; W4; W4; 378 W4; W4; W4; W4; 379 W4; W4; W4; W4; 380 W4; W4; W4; 381 } 382 while (resid) { 383 if (sbc_ready(ncr_sc)) 384 goto interrupt; 385 W1; 386 resid--; 387 } 388 #undef W1 389 #undef W4 390 if (sbc_wait_dreq(ncr_sc)) 391 printf("%s: timeout waiting for DREQ.\n", 392 ncr_sc->sc_dev.dv_xname); 393 394 *byte_data = 0; 395 goto done; 396 397 interrupt: 398 if ((*ncr_sc->sci_csr & SCI_CSR_PHASE_MATCH) == 0) { 399 *ncr_sc->sci_icmd = icmd & ~SCI_ICMD_DATA; 400 --resid; 401 } 402 403 done: 404 SCI_CLR_INTR(ncr_sc); 405 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 406 *ncr_sc->sci_icmd = icmd; 407 splx(s); 408 return (datalen - resid); 409 } 410 411 412 /*** 413 * The following code implements interrupt-driven PDMA. 414 ***/ 415 416 /* 417 * This is the meat of the PDMA transfer. 418 * When we get here, we shove data as fast as the mac can take it. 419 * We depend on several things: 420 * * All macs after the Mac Plus that have a 5380 chip should have a general 421 * logic IC that handshakes data for blind transfers. 422 * * If the SCSI controller finishes sending/receiving data before we do, 423 * the same general logic IC will generate a /BERR for us in short order. 424 * * The fault address for said /BERR minus the base address for the 425 * transfer will be the amount of data that was actually written. 426 * 427 * We use the nofault flag and the setjmp/longjmp in locore.s so we can 428 * detect and handle the bus error for early termination of a command. 429 * This is usually caused by a disconnecting target. 430 */ 431 void 432 sbc_drq_intr(p) 433 void *p; 434 { 435 struct sbc_softc *sc = (struct sbc_softc *)p; 436 struct ncr5380_softc *ncr_sc = (struct ncr5380_softc *)p; 437 struct sci_req *sr = ncr_sc->sc_current; 438 struct sbc_pdma_handle *dh = sr->sr_dma_hand; 439 label_t faultbuf; 440 volatile u_int32_t *long_drq; 441 u_int32_t *long_data; 442 volatile u_int8_t *drq; 443 u_int8_t *data; 444 int count, dcount, resid; 445 u_int8_t tmp; 446 447 /* Work around lame gcc initialization bug */ 448 (void)&drq; 449 450 /* 451 * If we're not ready to xfer data, or have no more, just return. 452 */ 453 if ((*ncr_sc->sci_csr & SCI_CSR_DREQ) == 0 || dh->dh_len == 0) 454 return; 455 456 #ifdef SBC_DEBUG 457 if (sbc_debug & SBC_DB_INTR) 458 printf("%s: drq intr, dh_len=0x%x, dh_flags=0x%x\n", 459 ncr_sc->sc_dev.dv_xname, dh->dh_len, dh->dh_flags); 460 #endif 461 462 /* 463 * Setup for a possible bus error caused by SCSI controller 464 * switching out of DATA-IN/OUT before we're done with the 465 * current transfer. 466 */ 467 nofault = &faultbuf; 468 469 if (setjmp(nofault)) { 470 nofault = (label_t *)0; 471 if ((dh->dh_flags & SBC_DH_DONE) == 0) { 472 count = (( (u_long)m68k_fault_addr 473 - (u_long)sc->sc_drq_addr)); 474 475 if ((count < 0) || (count > dh->dh_len)) { 476 printf("%s: complete=0x%x (pending 0x%x)\n", 477 ncr_sc->sc_dev.dv_xname, count, dh->dh_len); 478 panic("something is wrong"); 479 } 480 481 dh->dh_addr += count; 482 dh->dh_len -= count; 483 } else 484 count = 0; 485 486 #ifdef SBC_DEBUG 487 if (sbc_debug & SBC_DB_INTR) 488 printf("%s: drq /berr, complete=0x%x (pending 0x%x)\n", 489 ncr_sc->sc_dev.dv_xname, count, dh->dh_len); 490 #endif 491 m68k_fault_addr = 0; 492 493 return; 494 } 495 496 if (dh->dh_flags & SBC_DH_OUT) { /* Data Out */ 497 dcount = 0; 498 499 /* 500 * Get the source address aligned. 501 */ 502 resid = 503 count = min(dh->dh_len, 4 - (((int)dh->dh_addr) & 0x3)); 504 if (count && count < 4) { 505 drq = (volatile u_int8_t *)sc->sc_drq_addr; 506 data = (u_int8_t *)dh->dh_addr; 507 508 #define W1 *drq++ = *data++ 509 while (count) { 510 W1; count--; 511 } 512 #undef W1 513 dh->dh_addr += resid; 514 dh->dh_len -= resid; 515 } 516 517 /* 518 * Start the transfer. 519 */ 520 while (dh->dh_len) { 521 dcount = count = min(dh->dh_len, MAX_DMA_LEN); 522 long_drq = (volatile u_int32_t *)sc->sc_drq_addr; 523 long_data = (u_int32_t *)dh->dh_addr; 524 525 #define W4 *long_drq++ = *long_data++ 526 while (count >= 64) { 527 W4; W4; W4; W4; W4; W4; W4; W4; 528 W4; W4; W4; W4; W4; W4; W4; W4; /* 64 */ 529 count -= 64; 530 } 531 while (count >= 4) { 532 W4; count -= 4; 533 } 534 #undef W4 535 data = (u_int8_t *)long_data; 536 drq = (u_int8_t *)long_drq; 537 538 #define W1 *drq++ = *data++ 539 while (count) { 540 W1; count--; 541 } 542 #undef W1 543 dh->dh_len -= dcount; 544 dh->dh_addr += dcount; 545 } 546 dh->dh_flags |= SBC_DH_DONE; 547 548 /* 549 * XXX -- Read a byte from the SBC to trigger a /BERR. 550 * This seems to be necessary for us to notice that 551 * the target has disconnected. Ick. 06 jun 1996 (sr) 552 */ 553 if (dcount >= MAX_DMA_LEN) 554 drq = (volatile u_int8_t *)sc->sc_drq_addr; 555 tmp = *drq; 556 } else { /* Data In */ 557 /* 558 * Get the dest address aligned. 559 */ 560 resid = 561 count = min(dh->dh_len, 4 - (((int)dh->dh_addr) & 0x3)); 562 if (count && count < 4) { 563 data = (u_int8_t *)dh->dh_addr; 564 drq = (volatile u_int8_t *)sc->sc_drq_addr; 565 566 #define R1 *data++ = *drq++ 567 while (count) { 568 R1; count--; 569 } 570 #undef R1 571 dh->dh_addr += resid; 572 dh->dh_len -= resid; 573 } 574 575 /* 576 * Start the transfer. 577 */ 578 while (dh->dh_len) { 579 dcount = count = min(dh->dh_len, MAX_DMA_LEN); 580 long_data = (u_int32_t *)dh->dh_addr; 581 long_drq = (volatile u_int32_t *)sc->sc_drq_addr; 582 583 #define R4 *long_data++ = *long_drq++ 584 while (count >= 64) { 585 R4; R4; R4; R4; R4; R4; R4; R4; 586 R4; R4; R4; R4; R4; R4; R4; R4; /* 64 */ 587 count -= 64; 588 } 589 while (count >= 4) { 590 R4; count -= 4; 591 } 592 #undef R4 593 data = (u_int8_t *)long_data; 594 drq = (volatile u_int8_t *)long_drq; 595 596 #define R1 *data++ = *drq++ 597 while (count) { 598 R1; count--; 599 } 600 #undef R1 601 dh->dh_len -= dcount; 602 dh->dh_addr += dcount; 603 } 604 dh->dh_flags |= SBC_DH_DONE; 605 } 606 607 /* 608 * OK. No bus error occurred above. Clear the nofault flag 609 * so we no longer short-circuit bus errors. 610 */ 611 nofault = (label_t *)0; 612 613 #ifdef SBC_DEBUG 614 if (sbc_debug & (SBC_DB_REG | SBC_DB_INTR)) 615 printf("%s: drq intr complete: csr=0x%x, bus_csr=0x%x\n", 616 ncr_sc->sc_dev.dv_xname, *ncr_sc->sci_csr, 617 *ncr_sc->sci_bus_csr); 618 #endif 619 } 620 621 void 622 sbc_dma_alloc(ncr_sc) 623 struct ncr5380_softc *ncr_sc; 624 { 625 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 626 struct sci_req *sr = ncr_sc->sc_current; 627 struct scsipi_xfer *xs = sr->sr_xs; 628 struct sbc_pdma_handle *dh; 629 int i, xlen; 630 631 #ifdef DIAGNOSTIC 632 if (sr->sr_dma_hand != NULL) 633 panic("sbc_dma_alloc: already have PDMA handle"); 634 #endif 635 636 /* Polled transfers shouldn't allocate a PDMA handle. */ 637 if (sr->sr_flags & SR_IMMED) 638 return; 639 640 xlen = ncr_sc->sc_datalen; 641 642 /* Make sure our caller checked sc_min_dma_len. */ 643 if (xlen < MIN_DMA_LEN) 644 panic("sbc_dma_alloc: len=0x%x\n", xlen); 645 646 /* 647 * Find free PDMA handle. Guaranteed to find one since we 648 * have as many PDMA handles as the driver has processes. 649 * (instances?) 650 */ 651 for (i = 0; i < SCI_OPENINGS; i++) { 652 if ((sc->sc_pdma[i].dh_flags & SBC_DH_BUSY) == 0) 653 goto found; 654 } 655 panic("sbc: no free PDMA handles"); 656 found: 657 dh = &sc->sc_pdma[i]; 658 dh->dh_flags = SBC_DH_BUSY; 659 dh->dh_addr = ncr_sc->sc_dataptr; 660 dh->dh_len = xlen; 661 662 /* Copy the 'write' flag for convenience. */ 663 if (xs->flags & SCSI_DATA_OUT) 664 dh->dh_flags |= SBC_DH_OUT; 665 666 sr->sr_dma_hand = dh; 667 } 668 669 void 670 sbc_dma_free(ncr_sc) 671 struct ncr5380_softc *ncr_sc; 672 { 673 struct sci_req *sr = ncr_sc->sc_current; 674 struct sbc_pdma_handle *dh = sr->sr_dma_hand; 675 676 #ifdef DIAGNOSTIC 677 if (sr->sr_dma_hand == NULL) 678 panic("sbc_dma_free: no DMA handle"); 679 #endif 680 681 if (ncr_sc->sc_state & NCR_DOINGDMA) 682 panic("sbc_dma_free: free while in progress"); 683 684 if (dh->dh_flags & SBC_DH_BUSY) { 685 dh->dh_flags = 0; 686 dh->dh_addr = NULL; 687 dh->dh_len = 0; 688 } 689 sr->sr_dma_hand = NULL; 690 } 691 692 void 693 sbc_dma_poll(ncr_sc) 694 struct ncr5380_softc *ncr_sc; 695 { 696 struct sci_req *sr = ncr_sc->sc_current; 697 698 /* 699 * We shouldn't arrive here; if SR_IMMED is set, then 700 * dma_alloc() should have refused to allocate a handle 701 * for the transfer. This forces the polled PDMA code 702 * to handle the request... 703 */ 704 #ifdef SBC_DEBUG 705 if (sbc_debug & SBC_DB_DMA) 706 printf("%s: lost DRQ interrupt?\n", ncr_sc->sc_dev.dv_xname); 707 #endif 708 sr->sr_flags |= SR_OVERDUE; 709 } 710 711 void 712 sbc_dma_setup(ncr_sc) 713 struct ncr5380_softc *ncr_sc; 714 { 715 /* Not needed; we don't have real DMA */ 716 } 717 718 void 719 sbc_dma_start(ncr_sc) 720 struct ncr5380_softc *ncr_sc; 721 { 722 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 723 struct sci_req *sr = ncr_sc->sc_current; 724 struct sbc_pdma_handle *dh = sr->sr_dma_hand; 725 726 /* 727 * Match bus phase, clear pending interrupts, set DMA mode, and 728 * assert data bus (for writing only), then start the transfer. 729 */ 730 if (dh->dh_flags & SBC_DH_OUT) { 731 *ncr_sc->sci_tcmd = PHASE_DATA_OUT; 732 SCI_CLR_INTR(ncr_sc); 733 if (sc->sc_clrintr) 734 (*sc->sc_clrintr)(ncr_sc); 735 *ncr_sc->sci_mode |= SCI_MODE_DMA; 736 *ncr_sc->sci_icmd = SCI_ICMD_DATA; 737 *ncr_sc->sci_dma_send = 0; 738 } else { 739 *ncr_sc->sci_tcmd = PHASE_DATA_IN; 740 SCI_CLR_INTR(ncr_sc); 741 if (sc->sc_clrintr) 742 (*sc->sc_clrintr)(ncr_sc); 743 *ncr_sc->sci_mode |= SCI_MODE_DMA; 744 *ncr_sc->sci_icmd = 0; 745 *ncr_sc->sci_irecv = 0; 746 } 747 ncr_sc->sc_state |= NCR_DOINGDMA; 748 749 #ifdef SBC_DEBUG 750 if (sbc_debug & SBC_DB_DMA) 751 printf("%s: PDMA started, va=%p, len=0x%x\n", 752 ncr_sc->sc_dev.dv_xname, dh->dh_addr, dh->dh_len); 753 #endif 754 } 755 756 void 757 sbc_dma_eop(ncr_sc) 758 struct ncr5380_softc *ncr_sc; 759 { 760 /* Not used; the EOP pin is wired high (GMFH, pp. 389-390) */ 761 } 762 763 void 764 sbc_dma_stop(ncr_sc) 765 struct ncr5380_softc *ncr_sc; 766 { 767 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 768 struct sci_req *sr = ncr_sc->sc_current; 769 struct sbc_pdma_handle *dh = sr->sr_dma_hand; 770 int ntrans; 771 772 if ((ncr_sc->sc_state & NCR_DOINGDMA) == 0) { 773 #ifdef SBC_DEBUG 774 if (sbc_debug & SBC_DB_DMA) 775 printf("%s: dma_stop: DMA not running\n", 776 ncr_sc->sc_dev.dv_xname); 777 #endif 778 return; 779 } 780 ncr_sc->sc_state &= ~NCR_DOINGDMA; 781 782 if ((ncr_sc->sc_state & NCR_ABORTING) == 0) { 783 ntrans = ncr_sc->sc_datalen - dh->dh_len; 784 785 #ifdef SBC_DEBUG 786 if (sbc_debug & SBC_DB_DMA) 787 printf("%s: dma_stop: ntrans=0x%x\n", 788 ncr_sc->sc_dev.dv_xname, ntrans); 789 #endif 790 791 if (ntrans > ncr_sc->sc_datalen) 792 panic("sbc_dma_stop: excess transfer\n"); 793 794 /* Adjust data pointer */ 795 ncr_sc->sc_dataptr += ntrans; 796 ncr_sc->sc_datalen -= ntrans; 797 798 /* Clear any pending interrupts. */ 799 SCI_CLR_INTR(ncr_sc); 800 if (sc->sc_clrintr) 801 (*sc->sc_clrintr)(ncr_sc); 802 } 803 804 /* Put SBIC back into PIO mode. */ 805 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 806 *ncr_sc->sci_icmd = 0; 807 808 #ifdef SBC_DEBUG 809 if (sbc_debug & SBC_DB_REG) 810 printf("%s: dma_stop: csr=0x%x, bus_csr=0x%x\n", 811 ncr_sc->sc_dev.dv_xname, *ncr_sc->sci_csr, 812 *ncr_sc->sci_bus_csr); 813 #endif 814 } 815
Indexes created Mon Sep 22 05:09:51 GMT 2025