sbc.c revision 1.37
1 /* $NetBSD: sbc.c,v 1.37 1998/10/10 00:28:38 thorpej Exp $ */ 2 3 /* 4 * Copyright (C) 1996 Scott Reynolds. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * This file contains only the machine-dependent parts of the mac68k 31 * NCR 5380 SCSI driver. (Autoconfig stuff and PDMA functions.) 32 * The machine-independent parts are in ncr5380sbc.c 33 * 34 * Supported hardware includes: 35 * Macintosh II family 5380-based controller 36 * 37 * Credits, history: 38 * 39 * Scott Reynolds wrote this module, based on work by Allen Briggs 40 * (mac68k), Gordon W. Ross and David Jones (sun3), and Leo Weppelman 41 * (atari). Thanks to Allen for supplying crucial interpretation of the 42 * NetBSD/mac68k 1.1 'ncrscsi' driver. Also, Allen, Gordon, and Jason 43 * Thorpe all helped to refine this code, and were considerable sources 44 * of moral support. 45 */ 46 #include "opt_ddb.h" 47 48 #include <sys/types.h> 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/kernel.h> 52 #include <sys/errno.h> 53 #include <sys/device.h> 54 #include <sys/buf.h> 55 #include <sys/proc.h> 56 #include <sys/user.h> 57 58 #include <dev/scsipi/scsi_all.h> 59 #include <dev/scsipi/scsipi_all.h> 60 #include <dev/scsipi/scsipi_debug.h> 61 #include <dev/scsipi/scsiconf.h> 62 63 #include <dev/ic/ncr5380reg.h> 64 #include <dev/ic/ncr5380var.h> 65 66 #include <machine/cpu.h> 67 #include <machine/viareg.h> 68 69 #include <mac68k/dev/sbcreg.h> 70 #include <mac68k/dev/sbcvar.h> 71 72 /* SBC_DEBUG -- relies on DDB */ 73 #ifdef SBC_DEBUG 74 # define SBC_DB_INTR 0x01 75 # define SBC_DB_DMA 0x02 76 # define SBC_DB_REG 0x04 77 # define SBC_DB_BREAK 0x08 78 # ifndef DDB 79 # define Debugger() printf("Debug: sbc.c:%d\n", __LINE__) 80 # endif 81 # define SBC_BREAK \ 82 do { if (sbc_debug & SBC_DB_BREAK) Debugger(); } while (0) 83 #else 84 # define SBC_BREAK 85 #endif 86 87 88 int sbc_debug = 0 /* | SBC_DB_INTR | SBC_DB_DMA */; 89 int sbc_link_flags = 0 /* | SDEV_DB2 */; 90 int sbc_options = 0 /* | SBC_PDMA */; 91 92 struct scsipi_adapter sbc_ops = { 93 ncr5380_scsi_cmd, /* scsipi_cmd */ 94 minphys, /* scsipi_minphys */ 95 NULL, /* scsipi_ioctl */ 96 }; 97 98 /* This is copied from julian's bt driver */ 99 /* "so we have a default dev struct for our link struct." */ 100 struct scsipi_device sbc_dev = { 101 NULL, /* Use default error handler. */ 102 NULL, /* Use default start handler. */ 103 NULL, /* Use default async handler. */ 104 NULL, /* Use default "done" routine. */ 105 }; 106 107 extern label_t *nofault; 108 extern caddr_t m68k_fault_addr; 109 110 static int sbc_wait_busy __P((struct ncr5380_softc *)); 111 static int sbc_ready __P((struct ncr5380_softc *)); 112 static int sbc_wait_dreq __P((struct ncr5380_softc *)); 113 114 115 /*** 116 * General support for Mac-specific SCSI logic. 117 ***/ 118 119 /* These are used in the following inline functions. */ 120 int sbc_wait_busy_timo = 1000 * 5000; /* X2 = 10 S. */ 121 int sbc_ready_timo = 1000 * 5000; /* X2 = 10 S. */ 122 int sbc_wait_dreq_timo = 1000 * 5000; /* X2 = 10 S. */ 123 124 /* Return zero on success. */ 125 static __inline__ int 126 sbc_wait_busy(sc) 127 struct ncr5380_softc *sc; 128 { 129 int timo = sbc_wait_busy_timo; 130 for (;;) { 131 if (SCI_BUSY(sc)) { 132 timo = 0; /* return 0 */ 133 break; 134 } 135 if (--timo < 0) 136 break; /* return -1 */ 137 delay(2); 138 } 139 return (timo); 140 } 141 142 static __inline__ int 143 sbc_ready(sc) 144 struct ncr5380_softc *sc; 145 { 146 int timo = sbc_ready_timo; 147 148 for (;;) { 149 if ((*sc->sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) 150 == (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 151 timo = 0; 152 break; 153 } 154 if (((*sc->sci_csr & SCI_CSR_PHASE_MATCH) == 0) 155 || (SCI_BUSY(sc) == 0)) { 156 timo = -1; 157 break; 158 } 159 if (--timo < 0) 160 break; /* return -1 */ 161 delay(2); 162 } 163 return (timo); 164 } 165 166 static __inline__ int 167 sbc_wait_dreq(sc) 168 struct ncr5380_softc *sc; 169 { 170 int timo = sbc_wait_dreq_timo; 171 172 for (;;) { 173 if ((*sc->sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) 174 == (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 175 timo = 0; 176 break; 177 } 178 if (--timo < 0) 179 break; /* return -1 */ 180 delay(2); 181 } 182 return (timo); 183 } 184 185 void 186 sbc_irq_intr(p) 187 void *p; 188 { 189 struct ncr5380_softc *ncr_sc = p; 190 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 191 int claimed = 0; 192 extern int cold; 193 194 /* How we ever arrive here without IRQ set is a mystery... */ 195 if (*ncr_sc->sci_csr & SCI_CSR_INT) { 196 #ifdef SBC_DEBUG 197 if (sbc_debug & SBC_DB_INTR) 198 decode_5380_intr(ncr_sc); 199 #endif 200 if (!cold) 201 claimed = ncr5380_intr(ncr_sc); 202 if (!claimed) { 203 if (((*ncr_sc->sci_csr & ~SCI_CSR_PHASE_MATCH) == SCI_CSR_INT) 204 && ((*ncr_sc->sci_bus_csr & ~SCI_BUS_RST) == 0)) { 205 SCI_CLR_INTR(ncr_sc); /* RST interrupt */ 206 if (sc->sc_clrintr) 207 (*sc->sc_clrintr)(ncr_sc); 208 } 209 #ifdef SBC_DEBUG 210 else { 211 printf("%s: spurious intr\n", 212 ncr_sc->sc_dev.dv_xname); 213 SBC_BREAK; 214 } 215 #endif 216 } 217 } 218 } 219 220 #ifdef SBC_DEBUG 221 void 222 decode_5380_intr(ncr_sc) 223 struct ncr5380_softc *ncr_sc; 224 { 225 u_int8_t csr = *ncr_sc->sci_csr; 226 u_int8_t bus_csr = *ncr_sc->sci_bus_csr; 227 228 if (((csr & ~(SCI_CSR_PHASE_MATCH | SCI_CSR_ATN)) == SCI_CSR_INT) && 229 ((bus_csr & ~(SCI_BUS_MSG | SCI_BUS_CD | SCI_BUS_IO | SCI_BUS_DBP)) == SCI_BUS_SEL)) { 230 if (csr & SCI_BUS_IO) 231 printf("%s: reselect\n", ncr_sc->sc_dev.dv_xname); 232 else 233 printf("%s: select\n", ncr_sc->sc_dev.dv_xname); 234 } else if (((csr & ~SCI_CSR_ACK) == (SCI_CSR_DONE | SCI_CSR_INT)) && 235 ((bus_csr & (SCI_BUS_RST | SCI_BUS_BSY | SCI_BUS_SEL)) == SCI_BUS_BSY)) 236 printf("%s: dma eop\n", ncr_sc->sc_dev.dv_xname); 237 else if (((csr & ~SCI_CSR_PHASE_MATCH) == SCI_CSR_INT) && 238 ((bus_csr & ~SCI_BUS_RST) == 0)) 239 printf("%s: bus reset\n", ncr_sc->sc_dev.dv_xname); 240 else if (((csr & ~(SCI_CSR_DREQ | SCI_CSR_ATN | SCI_CSR_ACK)) == (SCI_CSR_PERR | SCI_CSR_INT | SCI_CSR_PHASE_MATCH)) && 241 ((bus_csr & (SCI_BUS_RST | SCI_BUS_BSY | SCI_BUS_SEL)) == SCI_BUS_BSY)) 242 printf("%s: parity error\n", ncr_sc->sc_dev.dv_xname); 243 else if (((csr & ~SCI_CSR_ATN) == SCI_CSR_INT) && 244 ((bus_csr & (SCI_BUS_RST | SCI_BUS_BSY | SCI_BUS_REQ | SCI_BUS_SEL)) == (SCI_BUS_BSY | SCI_BUS_REQ))) 245 printf("%s: phase mismatch\n", ncr_sc->sc_dev.dv_xname); 246 else if (((csr & ~SCI_CSR_PHASE_MATCH) == (SCI_CSR_INT | SCI_CSR_DISC)) && 247 (bus_csr == 0)) 248 printf("%s: disconnect\n", ncr_sc->sc_dev.dv_xname); 249 else 250 printf("%s: unknown intr: csr=%x, bus_csr=%x\n", 251 ncr_sc->sc_dev.dv_xname, csr, bus_csr); 252 } 253 #endif 254 255 256 /*** 257 * The following code implements polled PDMA. 258 ***/ 259 260 int 261 sbc_pdma_in(ncr_sc, phase, datalen, data) 262 struct ncr5380_softc *ncr_sc; 263 int phase; 264 int datalen; 265 u_char *data; 266 { 267 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 268 volatile u_int32_t *long_data = (u_int32_t *)sc->sc_drq_addr; 269 volatile u_int8_t *byte_data = (u_int8_t *)sc->sc_nodrq_addr; 270 int resid, s; 271 272 if (datalen < ncr_sc->sc_min_dma_len || 273 (sc->sc_options & SBC_PDMA) == 0) 274 return ncr5380_pio_in(ncr_sc, phase, datalen, data); 275 276 s = splbio(); 277 if (sbc_wait_busy(ncr_sc)) { 278 splx(s); 279 return 0; 280 } 281 282 *ncr_sc->sci_mode |= SCI_MODE_DMA; 283 *ncr_sc->sci_irecv = 0; 284 285 #define R4 *((u_int32_t *)data)++ = *long_data 286 #define R1 *((u_int8_t *)data)++ = *byte_data 287 for (resid = datalen; resid >= 128; resid -= 128) { 288 if (sbc_ready(ncr_sc)) 289 goto interrupt; 290 R4; R4; R4; R4; R4; R4; R4; R4; 291 R4; R4; R4; R4; R4; R4; R4; R4; 292 R4; R4; R4; R4; R4; R4; R4; R4; 293 R4; R4; R4; R4; R4; R4; R4; R4; /* 128 */ 294 } 295 while (resid) { 296 if (sbc_ready(ncr_sc)) 297 goto interrupt; 298 R1; 299 resid--; 300 } 301 #undef R4 302 #undef R1 303 304 interrupt: 305 SCI_CLR_INTR(ncr_sc); 306 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 307 *ncr_sc->sci_icmd = 0; 308 splx(s); 309 return (datalen - resid); 310 } 311 312 int 313 sbc_pdma_out(ncr_sc, phase, datalen, data) 314 struct ncr5380_softc *ncr_sc; 315 int phase; 316 int datalen; 317 u_char *data; 318 { 319 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 320 volatile u_int32_t *long_data = (u_int32_t *)sc->sc_drq_addr; 321 volatile u_int8_t *byte_data = (u_int8_t *)sc->sc_nodrq_addr; 322 label_t faultbuf; 323 int resid, s; 324 u_int8_t icmd; 325 326 #if 1 327 /* Work around lame gcc initialization bug */ 328 (void)&data; 329 #endif 330 331 if (datalen < ncr_sc->sc_min_dma_len || 332 (sc->sc_options & SBC_PDMA) == 0) 333 return ncr5380_pio_out(ncr_sc, phase, datalen, data); 334 335 s = splbio(); 336 if (sbc_wait_busy(ncr_sc)) { 337 splx(s); 338 return 0; 339 } 340 341 icmd = *(ncr_sc->sci_icmd) & SCI_ICMD_RMASK; 342 *ncr_sc->sci_icmd = icmd | SCI_ICMD_DATA; 343 *ncr_sc->sci_mode |= SCI_MODE_DMA; 344 *ncr_sc->sci_dma_send = 0; 345 346 /* 347 * Setup for a possible bus error caused by SCSI controller 348 * switching out of DATA OUT before we're done with the 349 * current transfer. (See comment before sbc_drq_intr().) 350 */ 351 nofault = &faultbuf; 352 353 if (setjmp(nofault)) { 354 printf("buf = 0x%lx, fault = 0x%lx\n", 355 (u_long)sc->sc_drq_addr, (u_long)m68k_fault_addr); 356 panic("Unexpected bus error in sbc_pdma_out()"); 357 } 358 359 #define W1 *byte_data = *((u_int8_t *)data)++ 360 #define W4 *long_data = *((u_int32_t *)data)++ 361 for (resid = datalen; resid >= 64; resid -= 64) { 362 if (sbc_ready(ncr_sc)) 363 goto interrupt; 364 W1; 365 if (sbc_ready(ncr_sc)) 366 goto interrupt; 367 W1; 368 if (sbc_ready(ncr_sc)) 369 goto interrupt; 370 W1; 371 if (sbc_ready(ncr_sc)) 372 goto interrupt; 373 W1; 374 if (sbc_ready(ncr_sc)) 375 goto interrupt; 376 W4; W4; W4; W4; 377 W4; W4; W4; W4; 378 W4; W4; W4; W4; 379 W4; W4; W4; 380 } 381 while (resid) { 382 if (sbc_ready(ncr_sc)) 383 goto interrupt; 384 W1; 385 resid--; 386 } 387 #undef W1 388 #undef W4 389 if (sbc_wait_dreq(ncr_sc)) 390 printf("%s: timeout waiting for DREQ.\n", 391 ncr_sc->sc_dev.dv_xname); 392 393 *byte_data = 0; 394 goto done; 395 396 interrupt: 397 if ((*ncr_sc->sci_csr & SCI_CSR_PHASE_MATCH) == 0) { 398 *ncr_sc->sci_icmd = icmd & ~SCI_ICMD_DATA; 399 --resid; 400 } 401 402 done: 403 SCI_CLR_INTR(ncr_sc); 404 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 405 *ncr_sc->sci_icmd = icmd; 406 splx(s); 407 return (datalen - resid); 408 } 409 410 411 /*** 412 * The following code implements interrupt-driven PDMA. 413 ***/ 414 415 /* 416 * This is the meat of the PDMA transfer. 417 * When we get here, we shove data as fast as the mac can take it. 418 * We depend on several things: 419 * * All macs after the Mac Plus that have a 5380 chip should have a general 420 * logic IC that handshakes data for blind transfers. 421 * * If the SCSI controller finishes sending/receiving data before we do, 422 * the same general logic IC will generate a /BERR for us in short order. 423 * * The fault address for said /BERR minus the base address for the 424 * transfer will be the amount of data that was actually written. 425 * 426 * We use the nofault flag and the setjmp/longjmp in locore.s so we can 427 * detect and handle the bus error for early termination of a command. 428 * This is usually caused by a disconnecting target. 429 */ 430 void 431 sbc_drq_intr(p) 432 void *p; 433 { 434 struct sbc_softc *sc = (struct sbc_softc *)p; 435 struct ncr5380_softc *ncr_sc = (struct ncr5380_softc *)p; 436 struct sci_req *sr = ncr_sc->sc_current; 437 struct sbc_pdma_handle *dh = sr->sr_dma_hand; 438 label_t faultbuf; 439 volatile u_int32_t *long_drq; 440 u_int32_t *long_data; 441 volatile u_int8_t *drq; 442 u_int8_t *data; 443 int count, dcount, resid; 444 u_int8_t tmp; 445 446 /* Work around lame gcc initialization bug */ 447 (void)&drq; 448 449 /* 450 * If we're not ready to xfer data, or have no more, just return. 451 */ 452 if ((*ncr_sc->sci_csr & SCI_CSR_DREQ) == 0 || dh->dh_len == 0) 453 return; 454 455 #ifdef SBC_DEBUG 456 if (sbc_debug & SBC_DB_INTR) 457 printf("%s: drq intr, dh_len=0x%x, dh_flags=0x%x\n", 458 ncr_sc->sc_dev.dv_xname, dh->dh_len, dh->dh_flags); 459 #endif 460 461 /* 462 * Setup for a possible bus error caused by SCSI controller 463 * switching out of DATA-IN/OUT before we're done with the 464 * current transfer. 465 */ 466 nofault = &faultbuf; 467 468 if (setjmp(nofault)) { 469 nofault = (label_t *)0; 470 if ((dh->dh_flags & SBC_DH_DONE) == 0) { 471 count = (( (u_long)m68k_fault_addr 472 - (u_long)sc->sc_drq_addr)); 473 474 if ((count < 0) || (count > dh->dh_len)) { 475 printf("%s: complete=0x%x (pending 0x%x)\n", 476 ncr_sc->sc_dev.dv_xname, count, dh->dh_len); 477 panic("something is wrong"); 478 } 479 480 dh->dh_addr += count; 481 dh->dh_len -= count; 482 } else 483 count = 0; 484 485 #ifdef SBC_DEBUG 486 if (sbc_debug & SBC_DB_INTR) 487 printf("%s: drq /berr, complete=0x%x (pending 0x%x)\n", 488 ncr_sc->sc_dev.dv_xname, count, dh->dh_len); 489 #endif 490 m68k_fault_addr = 0; 491 492 return; 493 } 494 495 if (dh->dh_flags & SBC_DH_OUT) { /* Data Out */ 496 dcount = 0; 497 498 /* 499 * Get the source address aligned. 500 */ 501 resid = 502 count = min(dh->dh_len, 4 - (((int)dh->dh_addr) & 0x3)); 503 if (count && count < 4) { 504 drq = (volatile u_int8_t *)sc->sc_drq_addr; 505 data = (u_int8_t *)dh->dh_addr; 506 507 #define W1 *drq++ = *data++ 508 while (count) { 509 W1; count--; 510 } 511 #undef W1 512 dh->dh_addr += resid; 513 dh->dh_len -= resid; 514 } 515 516 /* 517 * Start the transfer. 518 */ 519 while (dh->dh_len) { 520 dcount = count = min(dh->dh_len, MAX_DMA_LEN); 521 long_drq = (volatile u_int32_t *)sc->sc_drq_addr; 522 long_data = (u_int32_t *)dh->dh_addr; 523 524 #define W4 *long_drq++ = *long_data++ 525 while (count >= 64) { 526 W4; W4; W4; W4; W4; W4; W4; W4; 527 W4; W4; W4; W4; W4; W4; W4; W4; /* 64 */ 528 count -= 64; 529 } 530 while (count >= 4) { 531 W4; count -= 4; 532 } 533 #undef W4 534 data = (u_int8_t *)long_data; 535 drq = (u_int8_t *)long_drq; 536 537 #define W1 *drq++ = *data++ 538 while (count) { 539 W1; count--; 540 } 541 #undef W1 542 dh->dh_len -= dcount; 543 dh->dh_addr += dcount; 544 } 545 dh->dh_flags |= SBC_DH_DONE; 546 547 /* 548 * XXX -- Read a byte from the SBC to trigger a /BERR. 549 * This seems to be necessary for us to notice that 550 * the target has disconnected. Ick. 06 jun 1996 (sr) 551 */ 552 if (dcount >= MAX_DMA_LEN) 553 drq = (volatile u_int8_t *)sc->sc_drq_addr; 554 tmp = *drq; 555 } else { /* Data In */ 556 /* 557 * Get the dest address aligned. 558 */ 559 resid = 560 count = min(dh->dh_len, 4 - (((int)dh->dh_addr) & 0x3)); 561 if (count && count < 4) { 562 data = (u_int8_t *)dh->dh_addr; 563 drq = (volatile u_int8_t *)sc->sc_drq_addr; 564 565 #define R1 *data++ = *drq++ 566 while (count) { 567 R1; count--; 568 } 569 #undef R1 570 dh->dh_addr += resid; 571 dh->dh_len -= resid; 572 } 573 574 /* 575 * Start the transfer. 576 */ 577 while (dh->dh_len) { 578 dcount = count = min(dh->dh_len, MAX_DMA_LEN); 579 long_data = (u_int32_t *)dh->dh_addr; 580 long_drq = (volatile u_int32_t *)sc->sc_drq_addr; 581 582 #define R4 *long_data++ = *long_drq++ 583 while (count >= 64) { 584 R4; R4; R4; R4; R4; R4; R4; R4; 585 R4; R4; R4; R4; R4; R4; R4; R4; /* 64 */ 586 count -= 64; 587 } 588 while (count >= 4) { 589 R4; count -= 4; 590 } 591 #undef R4 592 data = (u_int8_t *)long_data; 593 drq = (volatile u_int8_t *)long_drq; 594 595 #define R1 *data++ = *drq++ 596 while (count) { 597 R1; count--; 598 } 599 #undef R1 600 dh->dh_len -= dcount; 601 dh->dh_addr += dcount; 602 } 603 dh->dh_flags |= SBC_DH_DONE; 604 } 605 606 /* 607 * OK. No bus error occurred above. Clear the nofault flag 608 * so we no longer short-circuit bus errors. 609 */ 610 nofault = (label_t *)0; 611 612 #ifdef SBC_DEBUG 613 if (sbc_debug & (SBC_DB_REG | SBC_DB_INTR)) 614 printf("%s: drq intr complete: csr=0x%x, bus_csr=0x%x\n", 615 ncr_sc->sc_dev.dv_xname, *ncr_sc->sci_csr, 616 *ncr_sc->sci_bus_csr); 617 #endif 618 } 619 620 void 621 sbc_dma_alloc(ncr_sc) 622 struct ncr5380_softc *ncr_sc; 623 { 624 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 625 struct sci_req *sr = ncr_sc->sc_current; 626 struct scsipi_xfer *xs = sr->sr_xs; 627 struct sbc_pdma_handle *dh; 628 int i, xlen; 629 630 #ifdef DIAGNOSTIC 631 if (sr->sr_dma_hand != NULL) 632 panic("sbc_dma_alloc: already have PDMA handle"); 633 #endif 634 635 /* Polled transfers shouldn't allocate a PDMA handle. */ 636 if (sr->sr_flags & SR_IMMED) 637 return; 638 639 xlen = ncr_sc->sc_datalen; 640 641 /* Make sure our caller checked sc_min_dma_len. */ 642 if (xlen < MIN_DMA_LEN) 643 panic("sbc_dma_alloc: len=0x%x\n", xlen); 644 645 /* 646 * Find free PDMA handle. Guaranteed to find one since we 647 * have as many PDMA handles as the driver has processes. 648 * (instances?) 649 */ 650 for (i = 0; i < SCI_OPENINGS; i++) { 651 if ((sc->sc_pdma[i].dh_flags & SBC_DH_BUSY) == 0) 652 goto found; 653 } 654 panic("sbc: no free PDMA handles"); 655 found: 656 dh = &sc->sc_pdma[i]; 657 dh->dh_flags = SBC_DH_BUSY; 658 dh->dh_addr = ncr_sc->sc_dataptr; 659 dh->dh_len = xlen; 660 661 /* Copy the 'write' flag for convenience. */ 662 if (xs->flags & SCSI_DATA_OUT) 663 dh->dh_flags |= SBC_DH_OUT; 664 665 sr->sr_dma_hand = dh; 666 } 667 668 void 669 sbc_dma_free(ncr_sc) 670 struct ncr5380_softc *ncr_sc; 671 { 672 struct sci_req *sr = ncr_sc->sc_current; 673 struct sbc_pdma_handle *dh = sr->sr_dma_hand; 674 675 #ifdef DIAGNOSTIC 676 if (sr->sr_dma_hand == NULL) 677 panic("sbc_dma_free: no DMA handle"); 678 #endif 679 680 if (ncr_sc->sc_state & NCR_DOINGDMA) 681 panic("sbc_dma_free: free while in progress"); 682 683 if (dh->dh_flags & SBC_DH_BUSY) { 684 dh->dh_flags = 0; 685 dh->dh_addr = NULL; 686 dh->dh_len = 0; 687 } 688 sr->sr_dma_hand = NULL; 689 } 690 691 void 692 sbc_dma_poll(ncr_sc) 693 struct ncr5380_softc *ncr_sc; 694 { 695 struct sci_req *sr = ncr_sc->sc_current; 696 697 /* 698 * We shouldn't arrive here; if SR_IMMED is set, then 699 * dma_alloc() should have refused to allocate a handle 700 * for the transfer. This forces the polled PDMA code 701 * to handle the request... 702 */ 703 #ifdef SBC_DEBUG 704 if (sbc_debug & SBC_DB_DMA) 705 printf("%s: lost DRQ interrupt?\n", ncr_sc->sc_dev.dv_xname); 706 #endif 707 sr->sr_flags |= SR_OVERDUE; 708 } 709 710 void 711 sbc_dma_setup(ncr_sc) 712 struct ncr5380_softc *ncr_sc; 713 { 714 /* Not needed; we don't have real DMA */ 715 } 716 717 void 718 sbc_dma_start(ncr_sc) 719 struct ncr5380_softc *ncr_sc; 720 { 721 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 722 struct sci_req *sr = ncr_sc->sc_current; 723 struct sbc_pdma_handle *dh = sr->sr_dma_hand; 724 725 /* 726 * Match bus phase, clear pending interrupts, set DMA mode, and 727 * assert data bus (for writing only), then start the transfer. 728 */ 729 if (dh->dh_flags & SBC_DH_OUT) { 730 *ncr_sc->sci_tcmd = PHASE_DATA_OUT; 731 SCI_CLR_INTR(ncr_sc); 732 if (sc->sc_clrintr) 733 (*sc->sc_clrintr)(ncr_sc); 734 *ncr_sc->sci_mode |= SCI_MODE_DMA; 735 *ncr_sc->sci_icmd = SCI_ICMD_DATA; 736 *ncr_sc->sci_dma_send = 0; 737 } else { 738 *ncr_sc->sci_tcmd = PHASE_DATA_IN; 739 SCI_CLR_INTR(ncr_sc); 740 if (sc->sc_clrintr) 741 (*sc->sc_clrintr)(ncr_sc); 742 *ncr_sc->sci_mode |= SCI_MODE_DMA; 743 *ncr_sc->sci_icmd = 0; 744 *ncr_sc->sci_irecv = 0; 745 } 746 ncr_sc->sc_state |= NCR_DOINGDMA; 747 748 #ifdef SBC_DEBUG 749 if (sbc_debug & SBC_DB_DMA) 750 printf("%s: PDMA started, va=%p, len=0x%x\n", 751 ncr_sc->sc_dev.dv_xname, dh->dh_addr, dh->dh_len); 752 #endif 753 } 754 755 void 756 sbc_dma_eop(ncr_sc) 757 struct ncr5380_softc *ncr_sc; 758 { 759 /* Not used; the EOP pin is wired high (GMFH, pp. 389-390) */ 760 } 761 762 void 763 sbc_dma_stop(ncr_sc) 764 struct ncr5380_softc *ncr_sc; 765 { 766 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 767 struct sci_req *sr = ncr_sc->sc_current; 768 struct sbc_pdma_handle *dh = sr->sr_dma_hand; 769 int ntrans; 770 771 if ((ncr_sc->sc_state & NCR_DOINGDMA) == 0) { 772 #ifdef SBC_DEBUG 773 if (sbc_debug & SBC_DB_DMA) 774 printf("%s: dma_stop: DMA not running\n", 775 ncr_sc->sc_dev.dv_xname); 776 #endif 777 return; 778 } 779 ncr_sc->sc_state &= ~NCR_DOINGDMA; 780 781 if ((ncr_sc->sc_state & NCR_ABORTING) == 0) { 782 ntrans = ncr_sc->sc_datalen - dh->dh_len; 783 784 #ifdef SBC_DEBUG 785 if (sbc_debug & SBC_DB_DMA) 786 printf("%s: dma_stop: ntrans=0x%x\n", 787 ncr_sc->sc_dev.dv_xname, ntrans); 788 #endif 789 790 if (ntrans > ncr_sc->sc_datalen) 791 panic("sbc_dma_stop: excess transfer\n"); 792 793 /* Adjust data pointer */ 794 ncr_sc->sc_dataptr += ntrans; 795 ncr_sc->sc_datalen -= ntrans; 796 797 /* Clear any pending interrupts. */ 798 SCI_CLR_INTR(ncr_sc); 799 if (sc->sc_clrintr) 800 (*sc->sc_clrintr)(ncr_sc); 801 } 802 803 /* Put SBIC back into PIO mode. */ 804 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 805 *ncr_sc->sci_icmd = 0; 806 807 #ifdef SBC_DEBUG 808 if (sbc_debug & SBC_DB_REG) 809 printf("%s: dma_stop: csr=0x%x, bus_csr=0x%x\n", 810 ncr_sc->sc_dev.dv_xname, *ncr_sc->sci_csr, 811 *ncr_sc->sci_bus_csr); 812 #endif 813 } 814
Indexes created Thu Oct 02 14:10:14 GMT 2025